REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8322
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
5 V CATV Line Driver
Coarse Step Output Power Control
FUNCTIONAL BLOCK DIAGRAM
DECODE
SHIFT
REGISTER
DATA LATCH
AD8322
V
IN+
V
IN
V
OUT+
V
OUT
BUFFER
R1
R2
ATTENUATION
CORE
8
8
8
POWER-DOWN
LOGIC
POWER
AMP
PD
GND (12 PINS)
DATEN
DATA CLK
Z
IN
(SINGLE) = 210
Z
IN
(DIFF) = 235
Z
OUT
DIFF =
75
V
CC
(7 PINS)
DIFF
OR SINGLE
INPUT
AMP
FEATURES
Supports DOCSIS Standard for Reverse Path
Transmission
Gain Programmable in 6 dB Steps Over a 42 dB
Range
Low Distortion at 60 dBmV Output
58 dBc SFDR at 21 MHz
56 dBc SFDR at 42 MHz
Output Noise Level
46 dBmV in 160 kHz Bandwidth
Maintains 75 Output Impedance
Power-Up and Power-Down Condition
180 MHz Bandwidth
5 V Supply Operation
Supports SPI Interfaces
APPLICATIONS
Gain Programmable Line Driver
DOCSIS-Compliant Data Modems
Interactive Set-Top Boxes
PC Plug-in Modems
General-Purpose Digitally Controlled Variable Gain Block
GENERAL DESCRIPTION
The AD8322 is a low-cost, digitally controlled variable gain ampli-
fier optimized for coaxial line driving applications such as cable
modems that are designed to the MCNS-DOCSIS upstream
standard. An 8-bit serial word determines the desired output
gain over a 42.14 dB range, with gain steps of 6.02 dB/major
carry.
The AD8322 comprises a digitally controlled variable attenuator
of 0 dB to 42.14 dB, which is preceded by a low-noise, fixed-gain
buffer and is followed by a low-distortion, high-power ampli-
fier. The AD8322 accepts a differential or single-ended input
signal. The output is specified for driving a 75
load, such as
coaxial cable.
Distortion performance of 58 dBc is achieved with an output level
up to 60 dBmV at 21 MHz bandwidth. A key performance and
cost advantage of the AD8322 results from the ability to maintain
a constant 75
output impedance during power-up and power-
down conditions. This eliminates the need for external 75
termination resulting in twice the effective output voltage when
compared to a standard operational amplifier.
The AD8322 is packaged in a low-cost 28-lead TSSOP, operates
from a single 5 V supply, and has an operational temperature
range of 40
C to +85C.
GAIN CODE Decimal
1
55
DISTORTION
dBc
60
65
70
75
2
4
8
16
32
64
128
f
O
= 42MHz
V
O
= 60dBmV
@ MAX GAIN
HD3
HD2
Figure 1. Harmonic Distortion vs. Gain Control
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2
AD8322SPECIFICATIONS
(T
A
= 25 C, V
S
= 5 V, R
L
= R
IN
= 75
, V
IN
= 92 mV p-p differential, V
OUT
measured through
a 1:1 transformer
1
with insertion loss of 0.5 dB @ 10 MHz unless otherwise noted)
Parameter
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Specified AC Voltage
P
OUT
= 60 dBmV, Max Gain
92
mV p-p
Noise Figure
Max Gain, f = 10 MHz
11.8
dB
Input Resistance
Single-Ended Input
210
Differential Input
235
Input Capacitance
2
pF
GAIN CONTROL INTERFACE
Gain Range
41.0
42.14
43.2
dB
Maximum Gain
Gain Code = 1xxxxxxx
27.5
29.5
31.5
dB
Minimum Gain
Gain Code = 00000001
14.64 12.64
10.64
dB
Gain Scaling Factor
6.02
dB/Major Carry
OUTPUT CHARACTERISTICS
Bandwidth (3 dB)
All Gain Codes
180
MHz
Bandwidth Roll-Off
f = 65 MHz
0.25
dB
Bandwidth Peaking
f = 65 MHz
0.05
dB
Output Noise
Max Gain, f = 10 MHz
32
dBmV in 160 kHz BW
Min Gain, f = 10 MHz
46
dBmV in 160 kHz BW
Power-Down Mode, f = 10 MHz
68
dBmV in 160 kHz BW
1 dB Compression Point
Max Gain, f = 10 MHz
19
dBm
Differential Output Impedance
Power-Up and Power-Down
75
20%
OVERALL PERFORMANCE
Second Order Harmonic Distortion
2
f = 5 MHz, P
OUT
= 60 dBmV @ Max Gain
64
dBc
f = 14 MHz, P
OUT
= 60 dBmV @ Max Gain
60
dBc
f = 21 MHz, P
OUT
= 60 dBmV @ Max Gain
58
dBc
f = 32 MHz, P
OUT
= 60 dBmV @ Max Gain
57
dBc
f = 42 MHz, P
OUT
= 60 dBmV @ Max Gain
56
dBc
f = 65 MHz, P
OUT
= 60 dBmV @ Max Gain
52
dBc
Third Order Harmonic Distortion
f = 5 MHz, P
OUT
= 60 dBmV @ Max Gain
67
dBc
f = 14 MHz, P
OUT
= 60 dBmV @ Max Gain
64
dBc
f = 21 MHz, P
OUT
= 60 dBmV @ Max Gain
61
dBc
f = 32 MHz, P
OUT
= 60 dBmV @ Max Gain
58
dBc
f = 42 MHz, P
OUT
= 60 dBmV @ Max Gain
56
dBc
f = 65 MHz, P
OUT
= 60 dBmV @ Max Gain
53
dBc
Gain Linearity Error
f = 10 MHz, Code to Code
0.2
dB
Output Settling to 1 mV
Due to Gain Change
Min to Max Gain
60
ns
Due to Input Change
Max Gain, V
IN
= 0 V to 0.09 V p-p
30
ns
Signal Feedthrough
Max Gain, Power-Down, f = 42 MHz,
24
dBc
V
IN
= 0.09 V p-p
POWER CONTROL
Power-Up Settling Time to 1 mV
Max Gain, V
IN
= 0
300
ns
Power-Down Settling Time to 1 mV
Max Gain, V
IN
= 0
40
ns
Between Burst Transients
3
Equivalent P
OUT
= 17.6 to 35.67 dBmV
3
mV p-p
Equivalent P
OUT
= 60 dBmV
16
mV p-p
POWER SUPPLY
Operating Range
4.75
5
5.25
V
Quiescent Current
Power-Up Mode
100
113
126
mA
Power-Down Mode
44
54
60
mA
OPERATING TEMPERATURE
40
+85
C
RANGE
NOTES
1
TOKO # 617 DB-A0070 used for above specifications. MACOM ETC-1-IT-15 can be substituted.
2
All distortion measurements taken with differential input signal and represent worst distortion across all gain codes.
3
Between burst transients measured at the output of PULSE B5008 42 MHz diplexer.
Specifications subject to change without notice.
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AD8322
3
LOGIC INPUTS (TTL/CMOS Compatible Logic)
Parameter
Min
Typ
Max
Unit
Logic "1" Voltage
2.1
5.0
V
Logic "0" Voltage
0
0.8
V
Logic "1" Current (V
INH
= 5 V) CLK, SDATA,
DATEN
0
20
nA
Logic "0" Current (V
INL
= 0 V) CLK, SDATA,
DATEN
600
100
nA
Logic "1" Current (V
INH
= 5 V)
PD
50
190
A
Logic "0" Current (V
INL
= 0 V)
PD
250
30
A
TIMING REQUIREMENTS
Parameter
Min
Typ
Max
Unit
Clock Pulsewidth (T
WH
)
16.0
ns
Clock Period (T
C
)
32.0
ns
Setup Time SDATA vs. Clock (T
DS
)
5.0
ns
Setup Time
DATEN vs. Clock (T
ES
)
15.0
ns
Hold Time SDATA vs. Clock (T
DH
)
5.0
ns
Hold Time
DATEN vs. Clock (T
EH
)
3.0
ns
Input Rise and Fall Times, SDATA,
DATEN, Clock (T
R
, T
F
)
10
ns
(Full Temperature Range, V
CC
= 5 V, T
R
= T
F
= 4 ns, f
CLK
= 8 MHz unless otherwise noted.)
(
DATEN, CLK, SDATA, PD, V
CC
= 5 V: Full Temperature Range)
T
ES
VALID DATA WORD G1
MSB. . . .LSB
GAIN TRANSFER (G1)
T
DS
T
EH
8 CLOCK CYCLES
GAIN TRANSFER (G2)
T
OFF
T
GS
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
PD
PEDESTAL
CLK
SDATA
DATEN
T
ON
T
C
T
WH
VALID DATA WORD G2
Figure 2. Serial Interface Timing
VALID DATA BIT
MSB
MSB-1
MSB-2
T
DS
T
DH
SDATA
CLK
Figure 3. SDATA Timing
Table I. Gain vs. Gain Code
Decimal
8-Bit SPI Data Word
Gain Code
MSB
LSB
Nominal Gain (dB)
1
0 0 0 0 0 0 0 1
12.64
2
0 0 0 0 0 0 1 0
6.62
4
0 0 0 0 0 1 0 0
0.60
8
0 0 0 0 1 0 0 0
5.42
16
0 0 0 1 0 0 0 0
11.44
32
0 0 1 0 0 0 0 0
17.46
64
0 1 0 0 0 0 0 0
23.48
128
1 x x x x x x x
29.50
0 = low, 1 = high, x = don't care.
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AD8322
4
ORDERING GUIDE
Model
Temperature Range
Package Description
JA
Package Option
AD8322ARU
40
C to +85C
28-Lead TSSOP
67.7
C/W*
RU-28
AD8322ARU-REEL
40
C to +85C
28-Lead TSSOP
67.7
C/W*
RU-28
AD8322-EVAL
Evaluation Board
*Thermal Resistance measured on SEMI standard 4-layer board.
ABSOLUTE MAXIMUM RATINGS
*
Supply Voltage +V
S
Pins 6, 8, 9, 20, 21, 23, 27 . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltages
Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.5 V
Pins 1, 2, 3, 7 . . . . . . . . . . . . . . . . . . . . . . . 0.8 V to +5.5 V
Internal Power Dissipation
TSSOP (RU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.90 W
Operating Temperature Range . . . . . . . . . . . 40
C to +85C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD8322
DATEN
GND
SDATA
VCC
CLK
VIN
GND
VIN+
VCC
GND
PD
VCC
GND
GND
GND
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
OUT
OUT+
BYP
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8322 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
SDATA
Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal
register with the MSB (Most Significant Bit) first.
2
CLK
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave
register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave.
This requires the input serial data word to be valid at or before this clock transition.
3
DATEN
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1
transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits
serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous gain
state) and simultaneously enables the register for serial data load.
4, 11, 12, 13,
GND
Common External Ground Reference.
14, 15, 16, 17,
18, 22, 24, 28
5
BYP
Internal Bypass. This pin must be externally ac-decoupled (0.1
F capacitor).
6, 8, 9, 20,
VCC
Common Positive External Supply Voltage. A 0.1
F capacitor must decouple each pin.
21, 23, 27
7
PD
Logic "0" powers down the part. Logic "1" powers up the part.
10
OUT
Negative Output Signal.
19
OUT+
Positive Output Signal.
25
VIN+
Noninverting Input. DC-biased to approximately V
CC
/2. Refer to Applications section for proper
termination.
26
VIN
Inverting Input. DC-biased to approximately V
CC
/2. Refer to Applications section for proper termination.
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AD8322
5
Typical Performance Characteristics
GAIN CONTROL Decimal
1
0.15
GAIN ERROR
dB
2
4
8
16
32
64
128
0.10
0.05
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
f = 5MHz
f = 10MHz
f = 42MHz
f = 65MHz
TPC 2. Gain Error vs. Gain Control
FREQUENCY MHz
36
1
1k
GAIN
dB
100
10
30
24
18
12
6
0
6
12
18
GC64
GC32
GC16
GC8
GC4
GC2
GC1
GC128
TPC 3. AC Response vs. Gain Control
V
IN+
V
IN
V
CC
GND
OUT
AD8322
BYP
OUT+
0.1 F
0.1 F
1:1
TOKO
617DB-A0070
C
L
0.1 F
0.1 F
432
75
75
75
+
V
O
5V
10 F
0.1 F
+1/2 V
IN
1/2 V
IN
0.1 F
DEVICE UNDER TEST
TPC 1. Test Circuit
FREQUENCY MHz
32
1
100
10
GAIN
dB
30
28
26
24
P
O
= 60dBmV
@ MAX GAIN
C
L
= 0pF
C
L
= 10pF
C
L
= 20pF
C
L
= 50pF
TPC 4. AC Response for Various Capacitor Loads
GAIN CODE Decimal
1
32
OUTPUT NOISE
dBmV in 160 kHz BW
2
4
8
16
32
64
128
36
40
44
48
f = 10MHz
PD = 1
TPC 5. Output Noise vs. Gain Code
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AD8322
6
FREQUENCY MHz
0
1
1k
FEEDTHROUGH
dBc
100
10
10
20
30
40
50
60
70
80
90
100
MAX GAIN
MIN GAIN
GAIN CODE 0
PD = 0
TPC 6. Input Signal Feedthrough vs. Frequency
FUNDAMENTAL FREQUENCY MHz
45
5
65
DISTORTION
dBc
50
55
60
65
55
45
35
25
15
P
O
= 58dBmV
at MAX GAIN
P
O
= 62dBmV
at MAX GAIN
P
O
= 60dBmV
at MAX GAIN
TPC 7. Second Order Harmonic Distortion vs.
Frequency for Various Output Levels
FUNDAMENTAL FREQUENCY MHz
45
5
65
DISTORTION
dBc
50
60
70
75
55
45
35
25
15
55
65
P
O
= 62dBmV
at MAX GAIN
P
O
= 58dBmV
at MAX GAIN
P
O
= 60dBmV
at MAX GAIN
TPC 8. Third Order Harmonic Distortion vs. Frequency
for Various Output Levels
FREQUENCY MHz
1
1k
IMPEDANCE
100
10
170
150
130
110
90
70
50
30
170
PD = 1
PD = 0
TPC 9. Input Impedance vs. Frequency (Inputs Shunted
with 432
)
FREQUENCY MHz
150
0.1
IMPEDANCE
125
100
75
50
25
1
10
100
1k
PD = 1
PD = 0
TPC 10. Output Impedance vs. Frequency
REV. 0
AD8322
7
APPLICATIONS
General Application
The AD8322 is primarily intended for use as the upstream power
amplifier (PA) in DOCSIS (Data Over Cable Service Interface
Specifications) certified cable modems and CATV set-top boxes.
Upstream data is modulated in QPSK or QAM format. This is
done with DSP or a dedicated QPSK/QAM modulator. The
amplifier receives its input signal from the QPSK/QAM modula-
tor or from a DAC. In either case the signal must be low-pass
filtered before being applied to the amplifier. Because the distance
from the cable modem to the central office will vary with each
subscriber, the AD8322 must be capable of varying its output
power by applying gain or attenuation to ensure that all signals
arriving at the central office are of the same amplitude. The
upstream signal path contains components such as a transformer
and diplexer that will result in some amount of power loss. There-
fore, the amplifier must be capable of providing enough power
into a 75
load to overcome these losses without sacrificing the
integrity of the output signal.
Operational Description
The AD8322 is composed of three analog functions in the power-
up or forward mode. The input amplifier (preamp) can be used
single-ended or differentially. If the input is used in the differen-
tial configuration, it is imperative that the input signals be 180
degrees out of phase and of equal amplitudes. This will ensure
the proper gain accuracy and harmonic performance. The preamp
stage drives a DAC, which provides the bulk of the AD8322's
attenuation (7 bits or 42.14 dB). The signals in the preamp and
DAC gain blocks are differential to improve the PSRR and linear-
ity. A differential current is fed from the DAC into the output
stage, which amplifies these currents to the appropriate levels
necessary to drive a 75
load. The output stage utilizes negative
feedback to implement a differential 75
output impedance.
This eliminates the need for external matching resistors.
SPI Programming and Gain Adjustment
Gain programming of the AD8322 is accomplished using a serial
peripheral interface (SPI) and three digital control lines,
DATEN,
SDATA, and CLK. To change the gain, eight bits of data are
streamed into the serial shift register through the SDATA port.
The SDATA load sequence begins with a falling edge on the
DATEN pin, thus activating the CLK line. Although the CLK
line is now activated, no change in gain is observed. With the
CLK line activated, data on the SDATA line is clocked into the
serial shift register, Most Significant Bit (MSB) first, on the
rising edge of each CLK pulse. A rising edge on the
DATEN line
latches the contents of the shift register into the attenuator core
resulting in a well-controlled change in the output signal level.
The serial interface timing for the AD8322 is shown in Fig-
ures 2 and 3. The programmable gain range of the AD8322 is
12.64 dB to +29.5 dB and scales 6.02 dB for each major carry.
Because the AD8322 was characterized with a TOKO transformer,
the stated gain values already take into account the losses asso-
ciated with the transformer. Valid gain codes are the major carries
from decimal 1128 (decimal values 1, 2, 4, 8, 16, 32, 64, 128).
The resulting gain for each code can be seen in Table I. Although
the AD8322 is designed for use with the previous eight codes,
the intermediate codes can be used.
The gain transfer function is as follows:
A
V
= 20
LOG (0.2332 CODE) for 1 CODE 128
A
V
= 29.5 dB for CODE
128
where A
V
is the gain in dB and CODE is the decimal equivalent
of the 8-bit word.
Figure 4 shows the gain characteristic for all possible values
(except 0) in an 8-bit word. Code 0 may be used if more
feedthrough isolation is required. It typically provides 85 dB of
isolation across the 5 MHz to 65 MHz upstream band.
GAIN CODE Decimal
35
0
GAIN
dB
30
25
20
15
10
0
5
10
15
20
32
64
96
128
160
192
224
256
5
Figure 4. Gain vs. Gain Code
Input Bias, Impedance, and Termination
The V
IN+
and V
IN
inputs have a dc bias level of approximately
V
CC
/2, therefore the input signal should be ac-coupled. The
differential input impedance is approximately 235
while the
single-ended input impedance is 210
. If the AD8322 is being
operated in a single-ended input configuration with a desired
input impedance of 75
, the V
IN+
and V
IN
inputs should be
terminated as shown in Figure 5. For input impedances other
than 75
, the value of R1 in Figure 5 can be calculated using
the following equation:
Z
R
IN
= 1 210
Z
IN
= 75
AD8322
R1 = 118
Figure 5. Single-Ended Input Termination
REV. 0
AD8322
8
Output Bias, Impedance, and Termination
The differential output pins V
OUT+
and V
OUT
are also biased to
a dc level of approximately V
CC
/2. Therefore, the outputs should
be ac-coupled before being applied to the load. This may be
accomplished by connecting 0.1
F capacitors in series with the
outputs as shown in the typical applications circuit of Figure 6.
The differential output impedance of the AD8322 is internally
maintained at 75
, regardless of whether the amplifier is in
forward transmit mode or reverse power-down mode, elimi-
nating the need for external back termination resistors. A 1:1
transformer (TOKO #617DB-A0070) is used to couple the
amplifier's differential output to the coaxial cable while main-
taining a proper impedance match. If the output signal is being
evaluated on standard 50
test equipment, a 75 to 50
pad must be used to provide the test circuit with the correct
impedance match.
Power Supply Decoupling, Grounding, and Layout
Considerations
Careful attention to printed circuit board layout details will
prevent problems due to associated board parasitics. Proper RF
design technique is mandatory. The 5 V supply power should be
delivered to each of the VCC pins via a low impedance power bus
to ensure that each pin is at the same potential. The power bus
should be decoupled to ground with a 10
F tantalum capacitor
located in close proximity to the AD8322. In addition to the
10
F capacitor, each VCC pin should be individually decoupled
to ground with a 0.1
F ceramic chip capacitor located as close
to the pin as possible. The pin labeled BYP (Pin 5) should also
be decoupled with a 0.1
F capacitor. The PCB should have a
low impedance ground plane covering all unused portions of the
component side of the board, except in the area of the input and
output traces (see Figure 11). It is important to connect all of
the AD8322 ground pins to ensure proper grounding of all
internal nodes. The differential input and output traces should
be kept as short and as symmetrical as possible. In addition, the
input and output traces should be kept far apart in order to
minimize coupling (crosstalk) through the board. Following these
guidelines will improve the overall performance of the AD8322
in all applications.
Initial Power-Up
When the 5 V supply is first applied to the VCC pins of the
AD8322, the gain setting of the amplifier is indeterminate.
Therefore, as power is first applied to the amplifier, the
PD pin
should be held low (Logic 0) thus preventing forward signal
transmission. After power has been applied to the amplifier, the
gain can be set to the desired level by following the procedure in
the SPI Programming and Gain Adjustment section. The
PD pin
can then be brought from Logic 0 to 1, enabling forward signal
transmission at the desired gain level.
Asynchronous Power-Down
The asynchronous
PD pin is used to place the AD8322 into
"Between Burst" mode while maintaining a differential output
impedance of 75
. Applying a Logic 0 to the PD pin activates
the on-chip reverse amplifier, providing a 52% reduction in con-
sumed power. The supply current is reduced from approximately
113 mA to approximately 54 mA. In this mode of operation,
between burst noise is minimized and the amplifier can no longer
transmit in the upstream direction.
Distortion, Adjacent Channel Power, and DOCSIS
In order to deliver 58 dBmV of high-fidelity output power
required by DOCSIS, the PA should be able to deliver about
60 to 61 dBmV in order to make up for losses associated with the
transformer and diplexer. It should be noted that the AD8322
was characterized with the TOKO 617DB-A0070 transformer.
TPC 7 and TPC 8 show the AD8322 second and third harmonic
distortion performance versus fundamental frequency for vari-
ous output power levels. These figures are useful for determining
the in-band harmonic levels from 5 MHz to 65 MHz. Harmonics
higher in frequency will be sharply attenuated by the low-pass
filter function of the diplexer. Another measure of signal integ-
rity is adjacent channel power or ACP. DOCSIS section 4.2.9.1.1
states, "Spurious emissions from a transmitted carrier may occur
SDATA
CLK
DATEN
GND1
BYP
VCC
PD
VCC1
VCC2
OUT
GND2
GND3
GND4
GND5
GND12
VCC6
VIN
VIN+
GND11
VCC5
GND10
VCC4
VCC3
OUT+
GND9
GND8
GND7
GND6
AD8322TSSOP
5V
PD
DATEN
SDATA
CLK
10 F
25V
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
TOKO 617DB-A0070
TO DIPLEXER
Z
IN
= 75
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
432
V
IN
V
IN+
Z
IN
= 150
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
27
26
25
24
23
22
21
20
19
18
17
16
15
0.1 F
0.1 F
Figure 6. Typical Applications Circuit
REV. 0
AD8322
9
in an adjacent channel which could be occupied by a carrier of
the same or different symbol rates." Figure 7 shows the measured
ACP, for a 16 QAM, 60 dBmV signal, taken at the output of the
AD8322 evaluation board (see Figure 13 for evaluation board
schematic). The transmit channel width and adjacent channel
width in Figure 7 correspond to symbol rates of 160 K
SYM/SEC
.
Table II shows the ACP results for the AD8322 for all conditions
in DOCSIS Table 4-7 "Adjacent Channel Spurious Emissions."
10
20
30
40
70
50
60
80
CENTER 10MHz
60kHz
SPAN 600kHz
CL1
C0
C0
CU1
CL1
RBW 500Hz RF ATT 40dB
VBW 5kHz
SWT 12s UNIT dBm
CH PWR 5.39dBm
ACP UP 54.22dB
ACP LOW 56.84dB
F1
CU1
Figure 7. Adjacent Channel Power
Table II. ACP Performance for All DOCSIS Conditions
(All Values in dBc)
TRANSMIT
CHANNEL
SYMBOL RATE
2560 K
SYM/SEC
54.2
160 K
SYM/SEC
320 K
SYM/SEC
640 K
SYM/SEC
1280 K
SYM/SEC
2560 K
SYM/SEC
ADJACENT CHANNEL SYMBOL RATE
54.7
55.4
53.8
54.6
54.6
54.0
54.1
54.5
53.9
54.1
53.9
54.2
54.2
54.2
160 K
SYM/SEC
320 K
SYM/SEC
640 K
SYM/SEC
1280 K
SYM/SEC
56.6
55.1
54.4
54.3
53.8
55.9
54.8
54.1
53.7
53.5
Noise and DOCSIS
At minimum gain, the AD8322's output noise spectral density is
12 nV/
Hz measured at 10 MHz. DOCSIS Table 4-8, "Spurious
Emissions in 5 MHz to 42 MHz" specifies the output noise for
various symbol rates. The calculated noise power in dBmV for
160 K
SYM/SEC
is:
20
12
160
60
46 4
2
log
.
nV
Hz
kHz
dBmV
+
=
Comparing the computed noise power of 46.4 dBmV to the
8 dBmV signal yields 54.4 dBc, which meets the required level
of 53 dBc set forth in DOCSIS Table 4-8. As the AD8322's
gain is increased from this minimum value, the output signal
increases at a faster rate than the noise, resulting in a signal-to-
noise ratio that improves with gain. In transmit disable mode
the output noise spectral density computed over 160 K
SYM/SEC
is
1.0 nV/
Hz or 68 dBmV.
Evaluation Board Features and Operation
The AD8322 evaluation board (Part # AD8322-EVAL) and
control software can be used to control the AD8322 upstream
cable driver via the parallel port of a PC. A standard printer cable
connected between the parallel port and the evaluation board is
used to feed all the necessary data to the AD8322 by means of the
Windows
based, Microsoft Visual Basic control software. This
package provides a means of evaluating the amplifier by provid-
ing a convenient way to program the gain/attenuation as well
as offering easy control of the amplifiers asynchronous
PD pin.
With this evaluation kit the AD8322 can be evaluated with either
a single-ended or differential input configuration. The amplifier
can also be evaluated with or without the PULSE diplexer in the
output signal path. To remove the diplexer from the signal path,
move the two 0
chip resistors R18 and R10 to locations R11 and
R20. A schematic of the evaluation board is provided in Figure 13.
Overshoot on PC Printer Ports
The data lines on some PC parallel printer ports have excessive
overshoot that may cause communications problems when pre-
sented to the CLK pin of the AD8322 (TP5 on the evaluation
board). The evaluation board was designed to accommodate
a series resistor and shunt capacitor (R1 and C15) to filter the
CLK signal if required.
Transformer and Diplexer
A 1:1 transformer is needed to couple the differential outputs of
the AD8322 to the cable while maintaining a proper impedance
match. The specified transformer is available from TOKO (Part
# 617DB-A0070), however, MA/COM part # ETC-1-1T-15
can also be used. The evaluation board is equipped with the
TOKO transformer, but is also designed to accept the MA/COM
transformer. The PULSE diplexer included on the evaluation
board provides a high-order low-pass filter function, typically
used in the upstream path. The ability of the PULSE diplexer to
achieve DOCSIS compliance is neither expressed nor implied by
Analog Devices Inc. Data on the diplexer should be obtained
from PULSE.
Differential Inputs
The AD8322-EVAL evaluation board is designed to accommo-
date a Mini-Circuits T1-6T-KK81 1:1 transformer for the purpose
of converting a single-ended (ground referenced) input signal to
differential inputs. Figure 8 and the following paragraphs iden-
tify three options for providing differential input signals to the
AD8322 evaluation board.
Windows is a registered trademark of Microsoft Corporation.
REV. 0
AD8322
10
Single-Ended-to-Differential Input (Figure 8 Option 1)
Install the Mini-Circuits T1-6T-KK81 1:1 transformer in the T1
location of the evaluation board. Install 0
chip resistors in R12,
R13, and R17, and leave R14, R16, and R19 open. For 75
input impedance, install a 110
resistor in R7 located on the back
side of the evaluation board and leave R5 and R6 open. In this
configuration the input signal must be applied to the V
IN+
port of
the evaluation board from a single-ended 75
signal source. For
input impedances other than 75
, use the following equation
to compute the correct value for R7.
Desired Input Impedance = R7 235
Single-Ended-to-Differential Input (Figure 8 Option 2)
Install the Mini-Circuits T1-6T-KK81 1:1 transformer in the T1
location of the evaluation board. Install 0
chip resistors in R12,
R13, R17, and R19, and leave R14 and R16 open. For 75
input
impedance, install 55
resistors in R5 and R6 located on the back
side of the evaluation board and leave R7 open. In this configu-
ration the input signal must be applied to the V
IN+
port of the
evaluation board from a single-ended 75
signal source. For
input impedances other than 75
, use the following equation
to compute the correct values for R5 and R6.
R5 = R6 = R, Desired Input Impedance = 2
(R 117.5)
Differential Input (Figure 8 Option 3)
If a differential signal source is available, it may be applied directly
to both the V
IN+
and V
IN
input ports of the evaluation board. In
this case, install 0
chip resistors in R8, R14, R15, and R16, and
leave R12, R13, and R19 open. Referring to Figure 8 Option 3 and
the AD8322 evaluation board, a differential input impedance
of 150
can be achieved by installing a 432 resistor in R7,
leaving R5 and R6 open. If another input impedance is desired,
the following equation can be used to compute the correct
value for R7.
Desired Input Impedance = R7 235
DIFF IN
T1
AD8322
R7
OPTION 1 DIFFERENTIAL INPUT TERMINATION
DIFF IN
T1
R5
R6
AD8322
OPTION 2 DIFFERENTIAL INPUT TERMINATION
R7
VIN+
AD8322
VIN
OPTION 3 DIFFERENTIAL INPUT TERMINATION
Figure 8. Differential Input Termination Options
Installing the Visual Basic Control Software
To install the "CABDRIVE_22" evaluation board control soft-
ware, first close all Windows applications and run "SETUP.EXE"
located on Disk 1 of the AD8322 Evaluation Software. Follow
the on-screen instructions and insert Disk 2 when prompted to
do so. Enter the path of the directory into which the software
will be installed and select the button in the upper left corner to
complete the installation.
Running the Software
To invoke the control software, go to START -> PROGRAMS
-> CABDRIVE_22, or select the AD8322.EXE icon from the
directory containing the software.
Controlling the Gain/Attenuation of the AD8322
The slide bar controls the AD8322's gain/attenuation, which is
displayed in dB and in V/V. Although the AD8322 is designed
for use at the eight gain codes described in the SPI Programming
and Gain Adjustment section, all of the intermediate codes are
included in the software. Code 0 is also included because of the
high isolation it provides. The gain code (i.e., position of the slide
bar) is displayed in decimal, binary, and hexadecimal (see
Figure 9).
POWER-UP AND POWER-DOWN
The "Power-Up" and "Power-Down" buttons select the mode of
operation of the AD8322 by controlling the logic level on the
asynchronous
PD pin. The "Power-Up" button applies a Logic
1 to the
PD pin putting the AD8322 in forward transmit mode.
The "Power-Down" button applies a Logic 0 to the
PD pin select-
ing reverse mode, where the forward signal transmission is disabled
while a back termination of 75
is maintained.
Memory Section
The "MEMORY" section of the software provides a convenient
way to alternate between two gain settings. The "X->M1" but-
ton stores the current value of the gain slide bar into memory
while the "RM1" button recalls the stored value, returning the
gain slide bar to that level. The "X->M2" and "RM2" buttons
work in the same manner.
REV. 0
AD8322
11
Figure 9. Screen Display of Windows-Based Control Software
REV. 0
AD8322
12
Figure 10. Evaluation Board--Assembly (Component Side)
Figure 11. Evaluation Board Layout (Component Side)
REV. 0
AD8322
13
Figure 12. Evaluation Board--Solder Side
REV. 0
AD8322
14
NC = 5
T1
1:1
NC = 2
T2B
1:1
T2A
DNI
1:1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0.1 F
0.1 F
0.1 F
0.1 F
C8
C7
C6
C5
C13
0.1 F
C12
0.1 F
R5
DNI
R7
118
TP14
YEL
TP13
YEL
4
6
3
1
2
R8
0
R9
DNI
VIN
VIN+
S2
S3
G1
G2
G3
G4
G5
G6
G7
G8
G9
18
17
16
15
14
13
12
11
10
PULSEB5008
A
A
B
B
U2
S4
S1
TP21
DNI
TP22
DNI
1
3
5
9
TP10
DNI
R4
DNI
R3
0
CABLE
HPP
TP9
DNI
TP11
DNI
TP12
DNI
C11
0.1 F
TOKO-B4F
ETCC1-1T
4
3
4
5
5
1
3
1
2
TP8
DNI
TP7
DNI
C10
0.1 F
TP4
TP6
R2
0
WHT
WHT
PD
C14
DNI
TP2
TP5
R1
0
WHT
WHT
CLK
C15
DNI
TP17
TP19
WHT
TP1
WHT
SDATA
TP3
WHT
DATEN
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
AMP-552742
VCC
J1
J2
AGND
BLK
TP20
C18
10 F
25V
TP15
RED
+
1
1
DATEN
SDATA
CLK
PD
0.1 F
0.1 F
0.1 F
0.1 F
C3
C4
C2
C1
DATEN
SDATA
CLK
GND1
BYP
VCC
PD
VCC1
VCC2
OUT
GND2
GND3
GND4
GND5
GND12
VCC6
VIN
VIN+
GND11
VCC5
GND10
VCC4
VCC3
OUT+
GND9
GND8
GND7
GND6
U1
AD8322TSSOP
R6
0
R14
0
R13
DNI
R12
DNI
R19
DNI
R15
0
R16
0
R17
DNI
R18
0
R11
DNI
R10
0
R20
DNI
C16
DNI
C9
DNI
WHT
Figure 13.
Evaluation Board Schematic
REV. 0
AD8322
15
EVALUATION BOARD BILL OF MATERIALS
AD8322 Evaluation Board Rev. DC SINGLE-ENDED INVERTING INPUT Revised June 22, 2000
Qty.
Description
Vendor
Ref Desc.
1
10
F 16 V. `C' size tantalum chip capacitor
ADS# 4-7-6
C18
12
0.1
F 50 V. 1206 size ceramic chip capacitor
ADS# 4-5-18
C18, 1013
10
0
1/8 W. 1206 size chip resistor
ADS# 3-18-88
R1, 2, 3, 6, 8, 10, 1416, 18
1
118
1% 1/8 W. 1206 size chip resistor
ADS# 3-18-106
R7
8
White Test Point (CLK,
PD, CP, SDATA, DATEN)
ADS# 12-18-42
TP16, 17, 19
1
Black Test Point (GND)
ADS# 12-18-44
TP20
1
Red Test Point (VCC)
ADS# 12-18-43
TP15
2
Yellow Test Point (+/- INPUT)
ADS# 12-18-32
TP13 & TP14
4
75
right-angle BNC Telegartner # J01003A1949
ADS# 12-6-28
S14 (INPUT, OUTPUT)
1
Centronics type 36-pin Right-Angle female connector
ADS# 12-3-50
P1
2
5-way Metal Binding Post
ADS# 12-7-7
J1, 2 (VCC, GND)
1
TOKO # 617 DB-A0070 transformer
Toko # 617DB-A0070
T2B
1
Diplexer PULSE
*
PULSE
U2
1
AD8322 (TSSOP)
ADS# AD8322
D.U.T. (U1)
1
AD8322 REV. E Evaluation PC board
D.S.C.
Evaluation PC board
4
#4 40
1/4 inch ss panhead machine screw
ADS# 30-1-1
4
#4 40
3/4 inch long aluminum round stand-off
ADS# 30-16-3
2
# 2 56
3/8 inch ss panhead machine screw
ADS# 30-1-17
(p1 hardware)
2
# 2 steel flat washer
ADS# 30-6-6
(p1 hardware)
2
# 2 steel internal tooth lockwasher
ADS# 30-5-2
(p1 hardware)
2
# 2 ss hex. machine nut
ADS# 30-7-6
(p1 hardware)
DO NOT INSTALL C9, C14C16, TP7TP12, TP21, TP22, R4, R5, R9, R11R13, R17, R19, R20, T1, T2A.
*PULSE Diplexer Part #'s B5008 (42 MHz), CX6002 (42 MHz), B5009 (65 MHz).
REV. 0
16
C020492.57/00 (rev. 0)
PRINTED IN U.S.A.
AD8322
28-Lead TSSOP
(RU-28)
0.177 (4.50)
0.169 (4.30)
28
15
14
1
0.386 (9.80)
0.378 (9.60)
0.256 (6.50)
0.246 (6.25)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433 (1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
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