Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
-
-
-
-
-
3.3 V Upstream
Cable Line Driver
AD8324
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2003 Analog Devices, Inc. All rights reserved.
FEATURES
Supports DOCSIS 2.0 and Euro-DOCSIS standards for
reverse path transmission systems
Gain programmable in 1 dB steps over a 59 dB range
Low distortion at 61 dBmV output:
59 dBc SFDR at 21 MHz
54 dBc SFDR at 65 MHz
Output noise level @ minimum gain 1.3 nV/Hz
Maintains 75 output impedance in TX-enable and
Transmit-disable
condition
Upper bandwidth: 100 MHz (full gain range)
3.3 V supply operation
Supports SPI interfaces
APPLICATIONS
DOCSIS 2.0 and Euro-DOCSIS cable modems
CATV set-top boxes
CATV telephony modems
Coaxial and twisted pair line drivers
GENERAL DESCRIPTION
The AD8324
1
is a low cost amplifier designed for coaxial line
driving. The features and specifications make the AD8324
ideally suited for DOCSIS 2.0 and Euro-DOCSIS applications.
The gain of the AD8324 is digitally controlled. An 8-bit serial
word determines the desired output gain over a 59 dB range,
resulting in gain changes of 1 dB/LSB.
The AD8324 accepts a differential or single-ended input signal.
The output is specified for driving a 75 load through a 1:1
transformer.
Distortion performance of 54 dBc is achieved with an output
level up to 61 dBmV at 65 MHz bandwidth.
This device has a sleep mode function that reduces the quies-
cent current to 30 A and a full power-down function that
reduces power-down current to 2.5 mA.
The AD8324 is packaged in a low cost 20-lead LFCSP package
and a 20-lead QSOP package. The AD8324 operates from a
single 3.3 V supply.
FUNCTIONAL BLOCK DIAGRAM
V
IN+
V
IN
V
OUT+
V
OUT
Z
IN
(SINGLE) = 550
Z
IN
(DIFF) = 1100
RAMP
Z
OUT
DIFF =
75
SHIFT
REGISTER
DATA LATCH
DECODE
POWER-
DOWN LOGIC
GND
DATEN
DATA CLK
TXEN
SLEEP
8
8
8
AD8324
VERNIER
DIFF
OR SINGLE
INPUT
AMP
OUTPUT
STAGE
BYP
ATTENUATION
CORE
04339-
0-
001
Figure 1. Functional Block Diagram
FREQUENCY (MHz)
DISTORTION (
d
Bc)
5
15
80
70
50
60
40
25
35
45
55
65
04339-0-002
V
OUT
= 61dBmV @ DEC 60
SECOND HARMONIC
V
OUT
= 61dBmV @ DEC 60
THIRD HARMONIC
Figure 2. Worst Harmonic Distortion vs. Frequency
1
Patent pending.
AD8324
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Logic Inputs (TTL/CMOS Compatible Logic)......................... 4
Timing Requirements .................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Functional Descriptions ........................ 6
Typical Performance Characteristics ............................................. 7
Applications..................................................................................... 10
General Applications.................................................................. 10
Circuit Description..................................................................... 10
Gain Programming for the AD8324 ........................................ 10
Input Bias, Impedance, and Termination ................................ 10
Output Bias, Impedance, and Termination ............................. 10
Power Supply............................................................................... 11
Signal Integrity Layout Considerations ................................... 11
Initial Power-Up ......................................................................... 11
RAMP Pin and BYP Pin Features ............................................ 11
Power Saving Features ............................................................... 12
Distortion, Adjacent Channel Power, and DOCSIS............... 12
Utilizing Diplex Filters............................................................... 12
Noise and DOCSIS..................................................................... 12
Evaluation Board Features and Operation.............................. 13
Differential Signal Source.......................................................... 13
Differential Signal from Single-Ended Source ....................... 13
Single-Ended Source.................................................................. 13
Overshoot on PC Printer Ports ................................................ 14
Installing Visual Basic Control Software................................. 14
Running AD8324 Software ....................................................... 14
Controlling Gain/Attenuation of the AD8324 ...................... 14
Transmit Enable and Sleep Mode............................................. 14
Memory Functions..................................................................... 14
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
Revision 0: Initial Version
AD8324
Rev. 0 | Page 3 of 16
SPECIFICATIONS
Table 1. T
A
= 25C, V
CC
= 3.3 V, R
L
= R
IN
= 75 , V
IN
(Differential) = 27.5 dBmV, unless otherwise noted. The AD8324 is characterized
using a 1:1 transformer
1
at the device output.
Parameter
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Specified AC Voltage
Output = 61 dBmV, Max Gain
27.5
dBmV
Input Resistance
Single-Ended Input
550
Differential Input
1100
Input Capacitance
2
pF
GAIN CONTROL INTERFACE
Voltage Gain Range
58
59.0
60
dB
Max Gain
Gain Code = 60 Dec
32.5
33.5
34.5
dB
Min Gain
Gain Code = 1 Dec
26.5
25.5
24.5
dB
Output Step Size
2
0.6
1.0
1.4
dB/LSB
Output Step Size Temperature Coefficient
T
A
= 40C to +85C
0.004
dB/C
OUTPUT CHARACTERISTICS
Bandwidth (3 dB)
All Gain Codes (160 Decimal Codes)
100
MHz
Bandwidth Roll-Off
f = 65 MHz
1.7
dB
1 dB Compression Point
3
Max Gain, f = 10 MHz, Output Referred
19.6
21
dBm
Min Gain, f = 10 MHz, Input Referred
2.1
3.7
dBm
Output Noise
2
Max Gain
f = 10 MHz
157
166
nV/Hz
Min Gain
f = 10 MHz
1.3
1.5
nV/Hz
Transmit Disable
f = 10 MHz
1.1
1.2
nV/Hz
Noise Figure
2
Max Gain
f = 10 MHz
15.5
16.0
dB
Differential Output Impedance
TX Enable and TX Disable
75 30%
4
OVERALL PERFORMANCE
Second-Order Harmonic Distortion
5, 3
f = 33 MHz, V
OUT
= 61 dBmV @ Max Gain
66
60
dBc
f = 65 MHz, V
OUT
= 61 dBmV @ Max Gain
58
53
dBc
Third-Order Harmonic Distortion
5, 3
f = 21 MHz, V
OUT
= 61 dBmV @ Max Gain
59
57.5
dBc
f = 65 MHz, V
OUT
= 61 dBmV @ Max Gain
54
52.5
dBc
ACPR
2, 6
61
58
dBc
Isolation (Transmit Disable)
2
Max Gain, f = 65 MHz
75
70
dB
POWER CONTROL
TX Enable Settling Time
Max Gain, V
IN
= 0
2.5
s
TX Disable Settling Time
Max Gain, V
IN
= 0
3.8
s
Output Switching Transients
3
Equivalent Output = 31 dBmV
2.5
6
mV p-p
Equivalent Output = 61 dBmV
27
71
mV p-p
Output Settling
Due to Gain Change
Min to Max Gain
60
ns
Due to Input Step Change
Max Gain, V
IN
= 27.5 dBmV
30
ns
POWER SUPPLY
Operating Range
3.13
3.3
3.47
V
Quiescent Current
Max Gain
195
207
235
mA
Min Gain
25
39
50
mA
Transmit Disable (TXEN = 0)
1
2.5
4
mA
SLEEP Mode (Power-Down)
30
500
A
OPERATING TEMPERATURE RANGE
LFCSP
40
+85
C
QSOP
25
+70
C
AD8324
Rev. 0 | Page 4 of 16
1
TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB @ 10 MHz.
2
Guaranteed by design and characterization to 6 sigma for T
A
= 25C.
3
Guaranteed by design and characterization to 3 sigma for T
A
= 25C.
4
Measured through a 1:1 transformer.
5
Specification is worst case over all gain codes.
6
V
IN
= 27.5 dBmV, QPSK modulation, 160 kSPS symbol rate.
LOGIC INPUTS (TTL/CMOS COMPATIBLE LOGIC)
Table 2. DATEN, CLK, SDATA, TXEN, SLEEP, V
CC
= 3.3 V, unless otherwise noted
Parameter
Min
Typ
Max
Unit
Logic 1 Voltage
2.1
3.3 V
Logic 0 Voltage
0
0.8 V
Logic 1 Current (V
INH
= 3.3 V), CLK, SDATA, DATEN
0
20
nA
Logic 0 Current (V
INL
= 0 V), CLK, SDATA, DATEN
-600
-100 nA
Logic 1 Current (V
INH
= 3.3 V), TXEN
50
190 A
Logic 0 Current (V
INL
= 0 V), TXEN
-250
-30 A
Logic 1 Current (V
INH
= 3.3 V), SLEEP
50
190 A
Logic 0 Current (V
INL
= 0 V), SLEEP
-250
-30 A
TIMING REQUIREMENTS
Table 3. V
CC
= 3.3 V, t
R
= t
F
= 4 ns, f
CLK
= 8 MHz, unless otherwise noted
Parameter Min
Typ
Max
Unit
Clock Pulse Width (t
WH
)
16.0
ns
Clock Period (t
C
)
32.0
ns
Setup Time SDATA vs. Clock (t
DS
)
5.0
ns
Setup Time DATEN vs. Clock (t
ES
)
15.0
ns
Hold Time SDATA vs. Clock (t
DH
)
5.0
ns
Hold Time DATEN vs. Clock (t
EH
)
3.0
ns
Input Rise and Fall Times, SDATA, DATEN, Clock (t
R
, t
F
)
10 ns
t
DS
CLK
VALID DATA WORD G1
MSB . . . LSB
SDATA
DATEN
TXEN
ANALOG
OUTPUT
VALID DATA WORD G2
8 CLOCK CYCLES
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
SIGNAL AMPLITUDE (p-p)
t
C
t
VUH
t
ES
t
EH
t
OFF
t
GS
t
CN
04339-0-0030
Figure 3. Serial Interface Timing
CLK
SDATA
MSB
MSB-1
MSB-2
VALID DATA BIT
t
DS
t
DH
04339-0-004
Figure 4. SDATA Timng
AD8324
Rev. 0 | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 4. AD8324 Stress Ratings
Parameter Rating
Supply Voltage V
CC
3.63
V
Input Voltage
VIN+, VIN
1.5 V p-p
DATEN, SDATA, CLK, SLEEP, TXEN
0.5 V to +3.63 V
Internal Power Dissipation
QSOP, LFCSP
776 mW
Operating Temperature Range
LFCSP
40C to +85C
QSOP
25C to +70C
Storage Temperature Range
65C to +150C
Lead Temperature (Soldering, 60 sec)
300C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8324
Rev. 0 | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
TOP VIEW
(Not to Scale)
AD8324
1
2
3
4
5
15
14
13
12
11
16
17
20 19 18
6
7
8
9 10
GND
GND
GND
V
IN+
V
IN
GND
GND
V
CC
V
CC
TXEN
GND
SLEEP
DATE
N
S
DATA
CLK
RAMP
V
OUT+
V
OUT
BYP
NC
04339-0-006
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD8324
TXEN
SDATA
V
CC
CLK
V
IN+
SLEEP
BYP
NC
V
OUT+
NC = NO CONNECT
GND
GND
GND
GND
V
IN
GND
RAMP
V
OUT
GND
V
CC
DATEN
04339-0-005
Figure 5. 20-Lead LFCSP
Figure 6. 20-Lead QSOP
Table 5. Pin Function Descriptions
Pin No.
Pin No.
20-Lead
LFCSP
20-Lead
QSOP Mnemonic
Description
1, 2, 5, 9,
18, 19
1, 3, 4, 7,
11, 20
GND
Common External Ground Reference.
17, 20
2, 19
V
CC
Common Positive External Supply Voltage.
3
5
V
IN+
Noninverting Input. DC-biased to approximately V
CC
/2. Should be ac-coupled with a 0.1 F
capacitor.
4
6
V
IN
Inverting Input. DC-biased to approximately V
CC
/2. Should be ac-coupled with a 0.1 F capacitor.
6
8
DATEN
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A
Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and
simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data
latch (holds the previous and simultaneously enables the register for serial data load).
7
9
SDATA
Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the internal
register with the MSB (most significant bit) first.
8
10
CLK
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-
slave shift register. Logic 0-to-1 transition latches the data bit, and a 1-to-0 transfers the data bit
to the slave. This requires the input serial data-word to be valid at or before this clock transition.
10
12
SLEEP
Low Power Sleep Mode. In the sleep mode, the AD8324's supply current is reduced to 30 A. A
Logic 0 powers down the part (high Z
OUT
state), and a Logic 1 powers up the part.
12
14
BYP
Internal Bypass. This pin must be externally decoupled (0.1 F capacitor).
13
15
V
OUT
Negative Output Signal. Must be biased to V
CC
. See Figure 23.
14
16
V
OUT+
Positive Output Signal. Must be biased to V
CC
. See Figure 23.
15
17
RAMP
External RAMP Capacitor (Optional).
16
18
TXEN
Logic 0 disables forward transmission. Logic 1 enables forward transmission.
AD8324
Rev. 0 | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
DISTORTION (
d
Bc)
5
15
80
70
50
60
40
25
35
45
55
65
04339-0-007
V
OUT
= 62dBmV @ DEC 60
V
OUT
= 60dBmV @ DEC 60
V
OUT
= 61dBmV @ DEC 60
Figure 7. Second-Order Harmonic Distortion vs. Frequency
for Various Output Powers
FREQUENCY (MHz)
5
DISTORTION (
d
Bc)
80
V
OUT
= 61dBmV @ DEC 60
15
25
35
45
55
65
60
50
40
70
T
A
= +25C
T
A
= 40C
T
A
= +85C
04339-0-008
Figure 8. LFSCP Second-Order Harmonic Distortion
vs. Frequency vs. Temperature
FREQUENCY (MHz)
5
DISTORTION (
d
Bc)
80
V
OUT
= 61dBmV @ DEC 60
15
25
35
45
55
65
60
50
40
70
T
A
= 25C
T
A
= +25C
T
A
= +70C
04339-0-009
Figure 9. QSOP Second-Order Harmonic Distortion
vs. Frequency vs. Temperature
FREQUENCY (MHz)
DISTORTION (
d
Bc)
5
15
80
70
50
60
40
25
35
45
55
65
04339-0-010
V
OUT
= 62dBmV @ DEC 60
V
OUT
= 60dBmV @ DEC 60
V
OUT
= 61dBmV @ DEC 60
Figure 10. Third-Order Harmonic Distortion vs. Frequency
for Various Output Powers
FREQUENCY (MHz)
DISTORTION (
d
Bc)
5
15
80
70
50
60
40
25
35
45
55
65
04339-0-011
T
A
= +85C
T
A
= +25C
T
A
= 40C
V
OUT
= 61dBmV @ DEC 60
Figure 11. LFCSP Third-Order Harmonic Distortion
vs. Frequency vs. Temperature
FREQUENCY (MHz)
DISTORTION (
d
Bc)
5
15
80
70
50
60
40
25
35
45
55
65
04339-0-012
T
A
= +70C
T
A
= +25C
T
A
= 25C
V
OUT
= 61dBmV @ DEC 60
Figure 12. QSOP Third-Order Harmonic Distortion
vs. Frequency vs. Temperature
AD8324
Rev. 0 | Page 8 of 16
CENTER 21 MHz
100
90
80
70
0
10
20
30
40
60
50
100 kHz/DIV
SPAN 1 MHz
04339-0-013
CH PWR
WORST ACP
12dBm
61dBc
CL1
CL1
CU1
CU1
C0
C0
P
OUT
(dBm)
Figure 13. Adjacent Channel Power
FREQUENCY (MHz)
0.1
GAIN (
d
B)
40
30
20
10
10
20
30
40
0
1
10
100
1000
DEC60
DEC54
DEC48
DEC42
DEC36
DEC30
DEC24
DEC18
DEC12
DEC 1 TO DEC 6
04339-0-014
Figure 14. AC Response
GAIN CONTROL (Decimal Code)
0
6
12
18
24
30
36
42
48
54
60
OU
TPU
T
STEP SIZE (
d
B
)
f
= 10MHz
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
04339-0-015
Figure 15. Output Step Size vs. Gain Control
FREQUENCY (MHz)
V
OUT
(dBmV
)
41.6
41.7
40
30
20
10
60
50
40
30
20
0
10
41.8
41.9
42.0
42.1
42.2
42.3
42.4
42.5
04339-0-016
V
OUT
= 57dBmV/TONE
@ MAX GAIN
Figure 16. Two-Tone Intermodulation Distortion
FREQUENCY (MHz)
0
0
IS
OLATION (dB)
10
10
20
30
40
50
60
70
80
90
100
100
1000
MAX GAIN
MIN GAIN
TXEN = 0
V
IN
= 27.5dBmV
04339-0-017
Figure 17. Isolation in Transmit Disable Mode vs. Frequency
GAIN CONTROL (Decimal Code)
0
6
12
24
18
30
36
42
48
54
60
GAIN E
RROR (dB)
f
= 10MHz
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
f
= 5MHz
f
= 42MHz
f
= 65MHz
04339-0-018
Figure 18. Gain Error vs. Gain Control
AD8324
Rev. 0 | Page 9 of 16
GAIN CONTROL (Decimal Code)
0
6
12
30
36
42
48
54
60
24
18
f
= 10MHz
TXEN = 1
160
140
120
100
80
60
40
20
0
180
OUTP
UT RE
FE
RRE
D V
O
LTAGE
NOIS
E
(nV
/
Hz)
04339-0-019
Figure 19. Output Referred Voltage Noise vs. Gain Control
GAIN CONTROL (Decimal Code)
0
QUIE
S
C
E
N
T S
U
P
P
L
Y
CURRE
NT (mA)
110
90
70
50
30
130
150
170
190
210
6
12
30
36
42
48
54
60
24
18
T
A
= 25C
04339-0-020
Figure 20. Supply Current vs. Gain Control
GAIN CONTROL (Decimal Code)
0
BE
TWE
E
N
BURS
TS
TRANS
IE
NTS
(mV
p-p)
70
60
50
40
30
80
90
100
110
20
10
0
DOCSIS 2.0 BETWEEN BURST
TRANSIENT SPECIFICATION
AD8324
6
12
30
36
42
48
54
60
24
18
04339-0-021
Figure 21. Between Burst Transient vs. Gain Control
AD8324
OUT+
OUT
GND
BYP
3.3V
1:1
10
F
39.5
75
18.7
18.7
0.1
F
0.1
F
0.1
F
V
IN+
1/2 V
IN
1/2 V
IN
V
CC
R
L
V
IN
04339-0-022
Figure 22. Typical Characterization Circuit
AD8324
Rev. 0 | Page 10 of 16
APPLICATIONS
GENERAL APPLICATIONS
The AD8324 is primarily intended for use as the upstream
power amplifier (PA) in DOCSIS (data over cable service
interface specification) certified cable modems and CATV set-
top boxes. The upstream signal is either a QPSK or QAM signal
generated by a DSP, a dedicated QPSK/QAM modulator, or a
DAC. In all cases, the signal must be low-pass filtered before
being applied to the PA in order to filter out-of-band noise and
higher order harmonics from the amplified signal.
Due to the varying distances between the cable modem and the
head-end, the upstream PA must be capable of varying the
output power by applying gain or attenuation. The ability to
vary the output power of the AD8324 ensures that the signal
from the cable modem will have the proper level once it arrives
at the head-end. The upstream signal path commonly includes a
diplexer and cable splitters. The AD8324 has been designed to
overcome losses associated with these passive components in
the upstream cable path.
CIRCUIT DESCRIPTION
The AD8324 is composed of three analog functions in the
transmit-enable mode. The input amplifier (preamp) can be
used in a single-ended or differential configuration. If the input
is used in the differential configuration, the input signals should
be 180 degrees out of phase and of equal amplitude. A vernier is
used in the input stage for controlling the fine 1 dB gain steps.
This stage then drives a DAC, which provides the bulk of the
AD8324's attenuation. The signals in the preamp and DAC
blocks are differential to improve the PSRR and linearity. A
differential current is fed from the DAC into the output stage.
The output stage maintains 75 differential output impedance
in all power modes.
GAIN PROGRAMMING FOR THE AD8324
The AD8324 features a serial peripheral interface (SPI) for
programming the gain code settings. The SPI interface consists
of three digital data lines: CLK, DATEN, and SDATA. The
DATEN pin should be held low while the AD8324 is being
programmed. The SDATA pin accepts the serial data stream for
programming the AD8324 gain code. The CLK pin accepts the
clock signal to latch in the data from the SDATA line.
The AD8324 utilizes a 6-bit shift register for clocking in the
data. The shift register is designed to be programmed MSB first.
The timing interface for programming the AD8324 can be seen
in Table 2, Table 3, Figure 3, and Figure 4. While the DATEN pin
is held low, the serial bits on the SDATA line are shifted into the
register on the rising edge of the CLK pin. For existing software
that uses 8-bits to program the cable driver, the 2 MSBs will be
ignored. This allows the AD8324 to be compatible with some
existing system designs.
The AD8324 recognizes gain codes 1 through 60 (all gain codes
are in decimal, unless otherwise noted). When the AD8324 is
programmed with 61 to 63, it will internally default to max gain
(gain code 60). If the programmed gain code is above 63, the
AD8324 will recognize only the 6 LSBs. For example, gain code
75 (01001011 binary) will be interpreted as gain code 11
(001011 binary) since the 2 MSBs are ignored.
The programming range of the AD8324 is from 25.5 dB (gain
code 1) to +33.5 dB (gain code 60). The 60 dB gain range is
linear with a 1 dB change in a 1 LSB change in gain code.
Figure 15 illustrates the gain step size of the AD8324 versus gain
code. The AD8324 was characterized with a differential input
signal and a TOKO 458PT-1457 1:1 transformer at the output.
INPUT BIAS, IMPEDANCE, AND TERMINATION
The V
IN+
and V
IN
inputs have a dc bias level of V
CC
/2; therefore
the input signal should be ac-coupled as seen in the typical
application circuit (Figure 23). The differential input impedance
of the AD8324 is approximately 1.1 k, while the single-ended
input is 550 . The high input impedance of the AD8324 allows
flexibility in termination and properly matching filter networks.
The AD8324 will exhibit optimum performance when driven
with a pure differential signal.
OUTPUT BIAS, IMPEDANCE, AND TERMINATION
.
The output stage of the AD8324 requires a bias of 3.3 V. The
3.3 V power supply should be connected to the center tap of the
output transformer. Also, the V
CC
that is being applied to the
center tap of the transformer should be decoupled as seen in the
typical application circuit (Figure 23).
The output impedance of the AD8324 is 75 , regardless of
whether the amplifier is in transmit enable, transmit disable, or
sleep mode. This, when combined with a 1:1 voltage ratio trans-
former, eliminates the need for external back termination resis-
tors. If the output signal is being evaluated using standard 50
test equipment, a minimum loss 75 to 50 pad must be used
to provide the test circuit with the proper impedance match.
The AD8324 evaluation board provides a convenient means to
implement a matching attenuator. Soldering a 43.3 resistor in
the R15 placeholder and an 86.6 resistor in the R16 place-
holder will allow testing on a 50 system. When using a
matching attenuator, it should be noted that there will be 5.7 dB
of power loss (7.5 dB voltage) through the network.
AD8324
Rev. 0 | Page 11 of 16
CLK
SDATA
DATEN
TXEN
GND
V
CC
V
CC
Z
IN
= 150
V
CC
GND
GND
GND
DATEN
SDATA
CLK
GND
TXEN
RAMP
BYP
SLEEP
NC
GND
AD8324-JRQ
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1k
174
1k
1k
1k
1k
SLEEP
TO DIPLEXER
Z
IN
= 75
TOKO 458PT-1556
V
IN+
V
IN
V
IN+
V
IN
V
OUT+
V
OUT
10
F
0.1
F
0.1
F
1:1
0.1
F
0.1
F
04339-0-023
Figure 23. Typical Application Circuit
Table 6. Adjacent Channel Power
Adjacent Channel Symbol Rate (kSym/s)
Channel Symbol Rate (kSym/s)
160
320
640
1280
2560
5120
160
63 64
68
71 72 66
320
63
64
66
70
72
67
640
64
64
65
67
71
67
1280
67
65
65
66
68
67
2560
70
67
66
66
67
65
5120
72
70
67
67
64
64
POWER SUPPLY
The 3.3 V supply should be delivered to each of the V
CC
pins via
a low impedance power bus. This ensures that each pin is at the
same potential. The power bus should be decoupled to ground
using a 10 F tantalum capacitor located close to the AD8324.
In addition to the 10 F capacitor, V
CC
pins should be decoupled
to ground with ceramic chip capacitors located close to the pins.
The bypass pin, labeled BYP, should also be decoupled. The PCB
should have a low impedance ground plane covering all unused
portions of the board, except in areas of the board where input
and output traces are in close proximity to the AD8324 and the
output transformer. All AD8324 ground pins must be connected
to the ground plane to ensure proper grounding of all internal
nodes.
SIGNAL INTEGRITY LAYOUT CONSIDERATIONS
Careful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
techniques are mandatory. The differential input and output
traces should be kept as short as possible. Keeping the traces
short will minimize parasitic capacitance and inductance, which
is most critical between the outputs of the AD8324 and the 1:1
output transformer. It is also critical that all differential signal
paths be symmetrical in length and width. In addition, the input
and output traces should be adequately spaced to minimize
coupling (crosstalk) through the board. Following these guide-
lines will optimize the overall performance of the AD8324 in all
applications.
INITIAL POWER-UP
When the supply voltage is first applied to the AD8324, the gain
of the amplifier is initially set to gain code 1. As power is first
applied to the amplifier, the TXEN pin should be held low
(Logic 0) to prevent forward signal transmission. After power
has been applied to the amplifier, the gain can be set to the
desired level by following the procedure provided in the Gain
Programming for the AD8324 section. The TXEN pin can then
be brought from Logic 0 to Logic 1, enabling forward signal
transmission at the desired gain level.
RAMP PIN AND BYP PIN FEATURES
The RAMP pin (Pin 15) is used to control the length of the
burst on and off transients. By default, leaving the RAMP pin
unconnected will result in a transient that is fully compliant
with DOCSIS 2.0 Section 6.2.21.2, Spurious Emissions During
Burst On/Off Transients. DOCSIS requires that all between
burst transients must be dissipated no faster than 2 s. Adding
capacitance to the RAMP pin will slow the dissipation even
more.
AD8324
Rev. 0 | Page 12 of 16
The BYP pin is used to decouple the output stage to ground.
Typically, for normal DOCSIS operation, the BYP pin should be
decoupled to ground with a 0.1 F capacitor. However, in
applications that may require transient on/off times faster than
2 s, smaller capacitors may be used, but it should be noted that
the BYP pin should always be decoupled to ground.
POWER SAVING FEATURES
The AD8324 incorporates three distinct methods of reducing
power consumption: transmit disable and sleep modes for
between-burst and shutdown modes, as well as gain dependent
quiescent current for transmit enable mode.
The asynchronous TXEN pin is used to place the AD8324 into
between-burst mode. In this reduced current state, the 75
output impedance is maintained. Applying Logic 0 to the TXEN
pin deactivates the on-chip amplifier, providing a 98.8% reduc-
tion in consumed power. For 3.3 V operation, the supply current
is typically reduced from 207 mA to 2.5 mA. In this mode of
operation, between-burst noise is minimized and high input to
output isolation is achieved. In addition to the TXEN pin, the
AD8324 also incorporates an asynchronous SLEEP pin, which
may be used to further reduce the supply current to approx-
imately 30 A. Applying Logic 0 to the SLEEP pin places the
amplifier into SLEEP mode. Transitioning into or out of SLEEP
mode may result in a transient voltage at the output of the
amplifier.
In addition to the sleep and transmit disable functions, the
AD8324 provides yet another means of reducing system power
consumption. While in the transmit enable state, the AD8324
incorporates supply current scaling, which allows for lower
power consumption at lower gain codes. Figure 20 shows the
typical relationship between supply current and gain code.
DISTORTION, ADJACENT CHANNEL POWER, AND
DOCSIS
To deliver the DOCSIS required 58 dBmV of QPSK signal and
55 dBmV of 16 QAM signal, the PA is required to deliver up to
61 dBmV. This added power is required to compensate for
losses associated with the diplex filter or other passive compo-
nents that may be included in the upstream path of cable
modems or set-top boxes. It should be noted that the AD8324
was characterized with a differential input signal. Figures 7 to 10
show the AD8324 second and third harmonic distortion perfor-
mance versus the fundamental frequency for various output
power levels. These figures are useful for determining the in-
band harmonic levels from 5 MHz to 65 MHz. Harmonics
higher in frequency (above 42 MHz for DOCSIS and above
65 MHz for Euro-DOCSIS) will be sharply attenuated by the
low-pass filter function of the diplexer.
Another measure of signal integrity is adjacent channel power,
commonly referred to as ACP. DOCSIS 2.0, section 6.2.21.1.1
states, "Spurious emissions from a transmitted carrier may
occur in an adjacent channel that could be occupied by a carrier
of the same or different symbol rates." Figure 13 shows the
typical ACP for a 61 dBmV (approximately 12 dBm) QPSK
signal taken at the output of the AD8324 evaluation board. The
transmit channel width and adjacent channel width in Figure 13
correspond to the symbol rates of 160 kSym/s. Table 6 shows
the ACP results for the AD8324 driving a QPSK, 61 dBmV
signal for all conditions in DOCSIS Table 6-9, Adjacent Channel
Spurious Emissions.
UTILIZING DIPLEX FILTERS
The AD8324 was designed to drive 61 dBmV without any
external filtering and still meet DOCSIS spurious emissions and
distortion requirements. However, in most upstream CATV
applications, a diplex filter is used to separate the upstream and
downstream signal paths from one another. The diplex filter
does have insertion loss that the upstream driver needs to over-
come, but it also provides a low-pass filter. The addition of this
low-pass filter to the signal chain can greatly attenuate second
harmonic products of channels above 21 MHz and third
harmonic products of channels at or above 14 MHz up for
diplexers with a 42 MHz upstream cutoff. Similar performance
gains can be achieved using European-specified diplexers to
filter second harmonics for channels above 33 MHz and third
harmonics for channels above 22 MHz (65 MHz upstream
cutoff). This filtering allows the AD8324 to drive up to
63 dBmV of QPSK (this level can vary by application and
modulation type).
NOISE AND DOCSIS
At minimum gain, the AD8324 output noise spectral density is
1.3 nV/Hz measured at 10 MHz. DOCSIS Table 6-10, Spurious
Emissions in 5 MHz to 42 MHz, specifies the output noise for
various symbol rates. The calculated noise power in dBmV for
160 kSym/s is
20 log [(1.3 nV/Hz)
2
160 kHz] + 60 = 65.7 dBmV
Comparing the computed noise power of 65.7 dBmV to the
+8 dBmV signal yields 73.7 dBc, which meets the required
level set forth in DOCSIS Table 6-10. As the AD8324 gain is
increased above this minimum value, the output signal
increases at a faster rate than the noise, resulting in a signal-to-
noise ratio that improves with gain. In transmit disable mode,
the output noise spectral density is 1.1 nV/Hz, which results in
67 dBmV when computed over 160 kSym/s. The noise power
was measured directly at the AD8324AR-EVAL's output.
AD8324
Rev. 0 | Page 13 of 16
EVALUATION BOARD FEATURES AND OPERATION
The AD8324 evaluation board and control software can be used
to control the AD8324 upstream cable driver via the parallel
port of a personal computer. A standard printer cable connected
to the parallel port of the PC is used to feed all the necessary
data to the AD8324 using the Windows based control software.
This package provides a means of controlling the gain and the
power mode of the AD8324. With this evaluation kit, the
AD8324 can be evaluated in either a single-ended or differential
input configuration. A schematic of the evaluation board is
provided in Figure 29.
DIFFERENTIAL SIGNAL SOURCE
Typical applications for the AD8324 use a differential input
signal from a modulator or a DAC. Refer to Table 7 for common
values of R4, or calculate other input configurations using the
equation in Figure 24. This circuit configuration will give
optimal distortion results due to the symmetric input signals. It
should be noted that this is the configuration that was used to
characterize the AD8324.
AD8324
R4
R4 =
V
IN+
V
IN
Z
IN
Z
IN
1100
1100
Z
IN
04339-0-024
Figure 24. Differential Circuit
DIFFERENTIAL SIGNAL FROM
SINGLE-ENDED SOURCE
The default configuration of the evaluation board implements a
differential signal drive from a single-ended signal source. This
configuration uses a 1:1 balun transformer to approximate a
differential signal. Because of the non-ideal nature of real
transformers, the differential signal is not purely equal and
opposite in amplitude. Although this circuit slightly sacrifices
even order harmonic distortion due to asymmetry, it does
provide a convenient way to evaluate the AD8324 with a single-
ended source. The AD8324 evaluation board is populated with a
TOKO 617DB-A0070 1:1 for this purpose (T1).
Table 7 provides typical R4 values for common input
configurations. R16 must be removed, and R2 and R3 should be
shorted. Other input impedances may be calculated using the
equation in Figure 25. Refer to Figure 29 for an evaluation
board schematic. To use the transformer for converting a single
ended source into a differential signal, the input signal must be
applied to V
IN+
.
AD8324
R4
R4 =
V
IN+
Z
IN
Z
IN
1100
1100
Z
IN
04339-0-025
Figure 25. Single-to-Differential Circuit
SINGLE-ENDED SOURCE
Although the AD8324 was designed to have optimal DOCSIS
performance when used with a differential input signal, the
AD8324 may also be used as a single-ended receiver, or as an IF
digitally controlled amplifier. However, as with the single-ended
to differential configuration noted previously, even order
harmonic distortion will be slightly degraded.
When operating the AD8324 in a single-ended input mode,
terminate the part as illustrated in Figure 26. On the AD8324
evaluation boards, this termination method requires the
removal and shorting of R2 and R3, the removal of R4, as well
as the addition of 86.6 at R1 and 40.2 at R17 for 75
termination. Table 7 shows the correct values for R11 and R12
for some common input configurations. Other input impedance
configurations may be accommodated using the equations in
Figure 26.
AD8324
R1
R17
V
IN+
Z
IN
R1 =
Z
IN
550
550 Z
IN
R17 =
Z
IN
R1
R1 Z
IN
04339-0-026
Figure 26. Single-Ended Circuit
Table 7. Common Matching Resistors
Differential Input Termination
Z
IN
()
R2/R3 ()
R4 ()
R1/R17 ()
50 Open
52.3
Open/Open
75 Open
80.6
Open/Open
100 Open
110 Open/Open
150 Open
174 Open/Open
Single-Ended Input Termination
Z
IN
()
R2/R3 ()
R4 ()
R1/R17 ()
50 0/0 Open
54.9/26.1
75 0/0 Open
86.6/40.2
AD8324
Rev. 0 | Page 14 of 16
OVERSHOOT ON PC PRINTER PORTS
The data lines on some PC parallel printer ports have excessive
overshoot, which may cause communications problems when
presented to the CLK pin of the AD8324. The evaluation board
was designed to accommodate a series resistor and shunt
capacitor (R9 and C5 in Figure 29) to filter the CLK signal if
required. For parallel ports with logic levels above 3.3 V, R9 and
C5 may be used as an attenuator.
INSTALLING VISUAL BASIC CONTROL SOFTWARE
Install the CabDrive_24 software by running the setup.exe file
on disk one of the AD8324 evaluation software. Follow the on-
screen directions and insert disk two when prompted. Choose
the installation directory and then select the icon in the upper
left to complete the installation.
RUNNING AD8324 SOFTWARE
To load the control software, go to START, PROGRAMS,
CABDRIVE_24 or select the AD8324.exe file from the installed
directory. Once loaded, select the proper parallel port to
communicate with the AD8324 (Figure 27).
04339-0-027
Figure 27. Parallel Port Selection
CONTROLLING GAIN/ATTENUATION
OF THE AD8324
The slide bar controls the gain/attenuation of the AD8324,
which is displayed in dB and in V/V. The gain scales 1 dB per
LSB. The gain code from the position of the slide bar is
displayed in decimal, binary, and hexadecimal (Figure 28).
04339-
0-
028
Figure 28. Control Software Interface
TRANSMIT ENABLE AND SLEEP MODE
The Transmit Enable and Transmit Disable buttons select the
mode of operation of the AD8324 by asserting logic levels on
the asynchronous TXEN pin. The Transmit Disable button
applies Logic 0 to the TXEN pin, disabling forward transmis-
sion. The Transmit Enable button applies Logic 1 to the TXEN
pin, enabling the AD8324 for forward transmission. Checking
the Enable SLEEP Mode checkbox applies Logic 0 to the asyn-
chronous SLEEP pin, setting the AD8324 for SLEEP mode.
MEMORY FUNCTIONS
The Memory section of the software provides a way to alternate
between two gain settings. The X>M1 button stores the
current value of the gain slide bar into memory, while the RM1
button recalls the stored value, returning the gain slide bar to
the stored level. The same applies to the X>M2 and RM2
buttons.
AD8324
Rev. 0 | Page 15 of 16
GND
GND
GND
TXEN
GND
RAMP
V
IN+
GND
BYP
DATAEN
N
C
SDATA
SLEEP
CLK
GND
AD8324
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
2
6
3
4
TOKO1
TP4A
R13A
1k
R14A
0
R11A
1k
R12A
0
C7A
OPEN
C6A
OPEN
TP3A
R9A
1k
R10A
0
C5A
OPEN
TP2A
R7A
1k
R8A
0
R15A
0
C4A
OPEN
R17A
OPEN
R3A
OPEN
R16A
OPEN
R2A
OPEN
R1A
OPEN
TP1A
R5A
1k
R6A
0
R4A
73.4
C3A
OPEN
TP5A
TP9A
VCC1
1
2
6
3
4
TOKOB5F
VCC1
CABLE_0A
C13A
0.1
F
T2A
TP10A
TP11A
TP12A
TP_AGND1
AGND1
TP_VCC1
VCC1
P1 19
P1 20
P1 21
P1 22
P1 23
P1 24
P1 25
P1 26
P1 27
P1 28
P1 29
P1 30
P1 31
P1 16
P1 7
P1 6
P1 5
P1 3
P1 2
VIN_A
VIN+_A
T1A
DUT1
C1A
0.1
F
C9A
OPEN
C8A
10
F
C10A
0.1
F
C11A
OPEN
C12A
0.1
F
C2A
0.1
F
V
CC
V
IN
V
CC
V
OUT+
V
OUT
04339-0-029
Figure 29. AD8324 Evaluation Board Schematic
AD8324
Rev. 0 | Page 16 of 16
OUTLINE DIMENSIONS
1
20
5
6
11
16
15
BOTTOM
VIEW
10
2.25
2.10 SQ
1.95
0.75
0.55
0.35
0.30
0.23
0.18
0.50
BSC
12 MAX
0.20
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
SEATING
PLANE
PIN 1
INDICATOR
TOP
VIEW
3.75
BSC SQ
4.0
BSC SQ
COPLANARITY
0.08
0.60
MAX
0.60
MAX
0.25 MIN
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 30. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm 4 mm Body (CP-20)
Dimensions shown in millimeters
20
11
10
1
PIN 1
8
0
0.236
BSC
0.154
BSC
0.010
0.004
0.012
0.008
0.025
BSC
COPLANARITY
0.004
0.065
0.049
0.069
0.053
SEATING
PLANE
0.010
0.006
0.050
0.016
0.341
BSC
COMPLIANT TO JEDEC STANDARDS MO-137AD
Figure 31. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20)
Dimensions shown in inches
ORDERING GUIDE
Model
Temperature Range
Package Description
JA
(C/W)
Package Option
AD8324JRQ
25C to +70C
20-Lead QSOP
83.2
1
RQ-20
AD8324JRQ-REEL
25C to +70C
20-Lead QSOP
83.2
1
RQ-20
AD8324JRQ-REEL7
25C to +70C
20-Lead QSOP
83.2
1
RQ-20
AD8324JRQ-EVAL
Evaluation Board
AD8324ACP
40C to +85C
20-Lead LFCSP
30.4
2
CP-20
AD8324ACP-REEL7
40C to +85C
20-Lead LFCSP
30.4
2
CP-20
AD8324ACP-EVAL
Evaluation Board
1
Thermal resistance measured on SEMI standard 4-layer board.
2
Thermal resistance measured on SEMI standard 4-layer board, paddle soldered to board.
2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C04339010/03(0)
PDF 
ZIP