REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8361
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
LF to 2.5 GHz
TruPwr
TM
Detector
FUNCTIONAL BLOCK DIAGRAMS
micro_SOIC
RFIN
IREF
PWDN
VPOS
FLTR
SREF
VRMS
COMM
BAND-GAP
REFERENCE
ERROR
AMP
2
2
AD8361
INTERNAL FILTER
ADD
OFFSET
TRANS-
CONDUCTANCE
CELLS
i
i
7.5
BUFFER
SOT-23-6L
RFIN
PWDN
VPOS
FLTR
VRMS
COMM
BAND-GAP
REFERENCE
2
2
AD8361
INTERNAL FILTER
TRANS-
CONDUCTANCE
CELLS
i
i
ERROR
AMP
7.5
BUFFER
FEATURES
Calibrated RMS Response
Excellent Temperature Stability
Up to 30 dB Input Range at 2.5 GHz
700 mV rms, 10 dBm re 50 Maximum Input
0.25 dB Linear Response Up to 2.5 GHz
Single Supply Operation: 2.7 V to 5.5 V
Low Power: 3.3 mW at 3 V Supply
Rapid Power-Down to Less than 1 A
APPLICATIONS
Measurement of CDMA, W-CDMA, QAM, Other
Complex Modulation Waveforms
RF Transmitter or Receiver Power Measurement
PRODUCT DESCRIPTION
The AD8361 is a mean-responding power detector for use in high-
frequency receiver and transmitter signal chains, up to 2.5 GHz.
It is very easy to apply. It requires only a single supply between
2.7 V and 5.5 V, power supply decoupling capacitor and an
input coupling capacitor in most applications. The output is a
linear-responding dc voltage with a conversion gain of 7.5 V/V rms.
An external filter capacitor can be added to increase the averag-
ing time constant.
RFIN V rms
3.0
1.6
0
0.5
0.1
0.2
0.3
0.4
2.6
2.2
2.0
1.8
2.8
2.4
V rms Volts
1.4
1.2
1.0
0.6
0.8
0.4
0.2
0.0
SUPPLY
REFERENCE MODE
INTERNAL
REFERENCE MODE
GROUND
REFERENCE MODE
Figure 1. Output in the Three Reference Modes, Supply 3 V,
Frequency 1.9 GHz (SOT-23-6L Package Ground Reference
Mode Only)
TruPwr is a trademark of Analog Devices, Inc.
The AD8361 is intended for true power measurement of simple
and complex waveforms. The device is particularly useful for
measuring high crest-factor (high peak-to-rms ratio) signals, such
as CDMA and W-CDMA.
The AD8361 has three operating modes to accommodate a
variety of analog-to-digital converter requirements:
1. Ground referenced mode, in which the origin is zero;
2. Internal reference mode, which offsets the output 350 mV
above ground;
3. Supply reference mode, which offsets the output to V
S
/7.5.
The AD8361 is specified for operation from 40
C to +85C and
is available in 8-lead micro_SOIC and 6-lead SOT packages.
It is fabricated on a proprietary high f
T
silicon bipolar process.
2
REV. A
AD8361SPECIFICATIONS
(T
A
= 25 C, V
S
= 3 V, f
RF
= 900 MHz, ground reference output mode, unless otherwise
noted.)
Parameter
Condition
Min
Typ
Max
Unit
SIGNAL INPUT INTERFACE
(Input RFIN)
Frequency Range
1
2.5
GHz
Linear Response Upper Limit
V
S
= 3 V
390
mV rms
Equivalent dBm re 50
4.9
dBm
V
S
= 5 V
660
mV rms
Equivalent dBm re 50
9.4
dBm
Input Impedance
2
225 1
pF
RMS CONVERSION
(Input RFIN to Output V rms)
Conversion Gain
7.5
V/V rms
f
RF
= 100 MHz, V
S
= 5 V
6.5
8.5
V/V rms
Dynamic Range
Error Referred to Best Fit Line
3
0.25 dB Error
4
CW Input, 40
C < T
A
< +85
C
14
dB
1 dB Error
CW Input, 40
C < T
A
< +85
C
23
dB
2 dB Error
CW Input, 40
C < T
A
< +85
C
26
dB
CW Input, V
S
= 5 V, 40
C < T
A
< +85
C
30
dB
Intercept-Induced Dynamic
Internal Reference Mode
1
dB
Range Reduction
5, 6
Supply Reference Mode, V
S
= 3.0 V
1
dB
Supply Reference Mode, V
S
= 5.0 V
1.5
dB
Deviation from CW Response
5.5 dB Peak-to-Average Ratio (IS95 Reverse Link)
0.2
dB
12 dB Peak-to-Average Ratio (W-CDMA 4 Channels)
1.0
dB
18 dB Peak-to-Average Ratio (W-CDMA 15 Channels)
1.2
dB
OUTPUT INTERCEPT
5
Inferred from Best Fit Line
3
Ground Reference Mode (GRM)
0 V at SREF, V
S
at IREF
0
V
f
RF
= 100 MHz, V
S
= 5 V
50
+150
mV
Internal Reference Mode (IRM)
0 V at SREF, IREF Open
350
mV
f
RF
= 100 MHz, V
S
= 5 V
300
500
mV
Supply Reference Mode (SRM)
0 V at IREF, 3 V at SREF
400
mV
f
RF
= 100 MHz, V
S
= 5 V
590
750
mV
0 V at IREF, V
S
at SREF
V
S
/7.5
V
POWER-DOWN INTERFACE
PWDN HI Threshold
2.7
V
S
5.5 V, 40
C < T
A
< +85
C
V
S
0.5
V
PWDN LO Threshold
2.7
V
S
5.5 V, 40
C < T
A
< +85
C
0.1
V
Power-Up Response Time
2 pF at FLTR Pin, 224 mV rms at RFIN
5
s
100 nF at FLTR Pin, 224 mV rms at RFIN
320
s
PWDN Bias Current
<1
A
POWER SUPPLIES
Operating Range
40
C < T
A
< +85
C
2.7
5.5
V
Quiescent Current
0 mV rms at RFIN, PWDN Input LO
7
1.1
mA
Power-Down Current
GRM or IRM, 0 mV rms at RFIN, PWDN Input HI
<1
A
SRM, 0 mV rms at RFIN, PWDN Input HI
10
V
S
A
NOTES
1
Operation at arbitrarily low frequencies is possible; see Applications section.
2
Figure 13 and Figure 40 show impedance vs. frequency for the micro_SOIC and SOT respectively.
3
Calculated using linear regression.
4
Compensated for output reference temperature drift; see Applications section.
5
SOT-23-6L operates in ground reference mode only.
6
The available output swing, and hence the dynamic range, is altered by both supply voltage and reference mode; see Figures 35 and 36.
7
Supply current is input level dependant; see Figure 12.
Specifications subject to change without notice.
AD8361
3
REV. A
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
SREF, PWDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
S
IREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
S
0.3 V, V
S
RFIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V rms
Equivalent Power re 50
. . . . . . . . . . . . . . . . . . . 13 dBm
Internal Power Dissipation
2
. . . . . . . . . . . . . . . . . . . . 200 mW
SOT-23-6L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mW
micro_SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125
C
Operating Temperature Range . . . . . . . . . . . 40
C to +85C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for the device in free air.
SOT-23-6L:
JA
= 230
C/W;
JC
= 92
C/W.
micro_SOIC:
JA
= 200
C/W;
JC
= 44
C/W.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8361 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
Pin
Micro SOT Name
Description
1
6
VPOS
Supply Voltage Pin. Operational range
2.7 V to 5.5 V.
2
IREF
Output Reference Control Pin. Inter-
nal reference mode enabled when pin
is left open. Otherwise, this pin should
be tied to VPOS. DO NOT ground this
pin.
3
5
RFIN
Signal Input Pin. Must be driven from
an ac-coupled source. The low frequency
real input impedance is 225
.
4
4
PWDN
Power-Down Pin. For the device to
operate as a detector it needs a logical
low input (less than 100 mV). When
a logic high (greater than V
S
0.5 V)
is applied, the device is turned off and
the supply current goes to nearly zero
(ground and internal reference mode
less than 1
A, supply reference mode
V
S
divided by 100 k
).
5
2
COMM Device Ground Pin.
6
3
FLTR
By placing a capacitor between this pin
and VPOS, the corner frequency of the
modulation filter is lowered. The on-
chip filter is formed with 27 pF 2 k
for small input signals.
7
1
VRMS
Output Pin. Near-rail-to-rail voltage
output with limited current drive capa-
bilities. Expected load >10 k
to ground.
8
SREF
Supply Reference Control Pin. To en-
able supply reference mode this pin
must be connected to VPOS, other-
wise it should be connected to COMM
(ground).
PIN CONFIGURATIONS
micro_SOIC
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
1
2
3
4
5
6
7
8
SOT-23-6L
VPOS
RFIN
PWDN
VRMS
FLTR
COMM
1
2
3
4
5
6
AD8361
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD8361ARM
*
40
C to +85C
Tube, 8-Lead micro_SOIC
RM-8
AD8361ARM-REEL
13" Tape and Reel
AD8361ARM-REEL7
7" Tape and Reel
AD8361ART-REEL
13" Tape and Reel
RT-6
AD8361ART-REEL7
7" Tape and Reel
AD8361-EVAL
Evaluation Board micro_SOIC
AD8361ART-EVAL
Evaluation Board SOT-23-6L
*Device branded as J3A.
WARNING!
ESD SENSITIVE DEVICE
AD8361
4
REV. A
Typical Performance Characteristics
INPUT V rms
2.8
2.6
0.8
0
0.5
0.1
0.2
0.3
0.4
2.0
1.4
1.2
1.0
2.4
2.2
1.6
1.8
OUTPUT
Volts
0.6
0.4
0.2
0.0
900MHz
100MHz
1900MHz
2.5GHz
Figure 2. Output vs. Input Level, Frequencies 100 MHz,
900 MHz, 1900 MHz, and 2500 MHz, Supply 2.7 V, Ground
Reference Mode, micro_SOIC
INPUT V rms
5.5
1.5
0
0.5
0.1
0.2
0.3
0.4
4.0
3.0
2.5
2.0
5.0
4.5
3.5
OUTPUT
Volts
1.0
0.5
0.0
5.5V
5.0V
3.0V
2.7V
0.6
0.7
0.8
Figure 3. Output vs. Input Level, Supply 2.7 V, 3.0 V, 5.0 V,
and 5.5 V, Frequency 900 MHz
INPUT V rms
5.0
1.5
0
0.5
0.1
0.2
0.3
0.4
4.0
3.0
2.5
2.0
4.5
3.5
OUTPUT
Volts
1.0
0.5
0.0
0.6
0.7
0.8
CW
IS95
REVERSE LINK
WCDMA
4- AND 15-CHANNEL
Figure 4. Output vs. Input Level with Different Waveforms
Sine Wave (CW), IS95 Reverse Link, W-CDMA 4-Channel
and W-CDMA 15-Channel, Supply 5.0 V
INPUT V rms
3.0
2.5
1.0
0.4
(+5dBm)
0.01
1.5
0
0.5
2.0
0.5
1.0
ERROR
dB
1.5
2.0
2.5
3.0
0.1
(7dBm)
0.02
(21dBm)
MEAN 3 SIGMA
Figure 5. Error from Linear Reference vs. Input Level,
3 Sigma to Either Side of Mean, Sine Wave, Supply 3.0 V,
Frequency 900 MHz
INPUT V rms
3.0
2.5
1.0
0.6
(+8.6dBm)
0.01
1.5
0
0.5
2.0
0.5
1.0
ERROR
dB
1.5
2.0
2.5
3.0
0.1
(7dBm)
0.02
(21dBm)
MEAN 3 SIGMA
Figure 6. Error from Linear Reference vs. Input Level,
3 Sigma to Either Side of Mean, Sine-Wave, Supply 5.0 V,
Frequency 900 MHz
INPUT V rms
3.0
2.5
1.0
1.0
0.01
0.1
1.5
0.0
0.5
2.0
0.5
1.0
ERROR
dB
1.5
2.0
2.5
3.0
0.02
0.6
0.2
IS95
REVERSE LINK
CW
15-CHANNEL
4-CHANNEL
Figure 7. Error from CW Linear Reference vs. Input with
Different Waveforms Sine Wave (CW), IS95 Reverse Link,
W-CDMA 4-Channel and W-CDMA 15-Channel, Supply
3.0 V, Frequency 900 MHz
AD8361
5
REV. A
INPUT V rms
3.0
2.5
1.0
0.4
(+5dBm)
0.01
1.5
0
0.5
2.0
0.5
1.0
ERROR
dB
1.5
2.0
2.5
3.0
0.1
(7dBm)
0.02
(21dBm)
MEAN 3 SIGMA
Figure 8. Error from CW Linear Reference vs. Input,
3 Sigma to Either Side of Mean, IS95 Reverse Link Signal,
Supply 3.0 V, Frequency 900 MHz
INPUT V rms
3.0
2.5
1.0
0.6
(+8.6dBm)
0.01
1.5
0
0.5
2.0
0.5
1.0
ERROR
dB
1.5
2.0
2.5
3.0
0.1
(7dBm)
0.02
(21dBm)
MEAN 3 SIGMA
Figure 9. Error from CW Linear Reference vs. Input Level,
3 Sigma to Either Side of Mean, IS95 Reverse Link Signal,
Supply 5.0 V, Frequency 900 MHz
INPUT V rms
3.0
2.5
1.0
0.4
(+5dBm)
0.01
1.5
0
0.5
2.0
0.5
1.0
ERROR
dB
1.5
2.0
2.5
3.0
0.1
(7dBm)
0.02
(21dBm)
40 C
+85 C
Figure 10. Output Delta from +25
C vs. Input Level,
3 Sigma to Either Side of Mean Sine Wave, Supply 3.0 V,
Frequency 900 MHz, Temperature 40
C to +85C
INPUT V rms
3.0
2.5
1.0
0.4
(+5dBm)
0.01
1.5
0
0.5
2.0
0.5
1.0
ERROR
dB
1.5
2.0
2.5
3.0
0.1
(7dBm)
0.02
(21dBm)
40 C
+85 C
Figure 11. Output Delta from +25
C vs. Input Level,
3 Sigma to Either Side of Mean Sine Wave, Supply 3.0 V,
Frequency 1900 MHz, Temperature 40
C to +85C
INPUT V rms
11
3
0
0.5
0.1
0.2
0.3
0.4
8
6
5
4
10
9
7
SUPPLY CURRENT
mA
2
1
0
0.6
0.7
0.8
+85 C
40 C
+25 C
V
S
= 5V
INPUT OUT
OF RANGE
+25 C
+85 C
40 C
V
S
= 3V
INPUT OUT
OF RANGE
Figure 12. Supply Current vs. Input Level, Supplies 3.0 V,
and 5.0 V, Temperatures 40
C, +25C, and +85C
FREQUENCY MHz
0
500
1000
250
200
150
SHUNT RESISTANCE
100
50
0
2000
2500
1.4
1.2
1.0
SHUNT CAPACITANCE
pF
0.8
0.6
0.4
1500
+85 C
+25 C
40 C
+85 C
+25 C
40 C
1.6
1.8
Figure 13. Input Impedance vs. Frequency, Supply 3 V,
Temperatures 40
C, +25C, and +85C, micro_SOIC (See
Applications for SOT-23-6L Data)
AD8361
6
REV. A
TEMPERATURE C
0.02
40
40
20
0
20
0.03
0.01
0.00
0.01
0.02
INTERCEPT CHANGE
Volts
0.03
0.04
0.05
60
80
100
MEAN 3 SIGMA
Figure 14. Output Reference Change vs. Temperature,
Supply 3 V, Ground Reference Mode
TEMPERATURE C
0.01
40
40
20
0
20
0.02
0.01
0.00
INTERCEPT CHANGE
Volts
0.02
0.03
60
80
100
MEAN 3 SIGMA
Figure 15. Output Reference Change vs. Temperature,
Supply 3 V, Internal Reference Mode (micro_SOIC Only)
TEMPERATURE C
0.02
40
40
20
0
20
0.03
0.01
0.00
0.01
0.02
INTERCEPT CHANGE
Volts
0.03
0.04
0.05
60
80
100
MEAN 3 SIGMA
Figure 16. Output Reference Change vs. Temperature,
Supply 3 V, Supply Reference Mode (micro_SOIC Only)
TEMPERATURE C
0.02
40
40
20
0
20
0.12
0.08
0.06
0.04
0.10
GAIN CHANGE
V/V rms
0.00
0.02
0.04
60
80
100
MEAN 3 SIGMA
0.06
0.14
0.16
0.18
Figure 17. Conversion Gain Change vs. Temperature,
Supply 3 V, Ground Reference Mode, Frequency 900 MHz
TEMPERATURE C
0.02
40
40
20
0
20
0.12
0.08
0.06
0.04
0.10
GAIN CHANGE
V/V rms
0.00
0.02
0.04
60
80
100
MEAN 3 SIGMA
0.06
0.14
0.16
0.18
Figure 18. Conversion Gain Change vs. Temperature,
Supply 3 V, Internal Reference Mode, Frequency 900 MHz
(micro_SOIC Only)
TEMPERATURE C
0.02
40
40
20
0
20
0.12
0.08
0.06
0.04
0.10
GAIN CHANGE
V/V rms
0.00
0.02
0.04
60
80
100
MEAN 3 SIGMA
0.06
0.14
0.16
0.18
Figure 19. Conversion Gain Change vs. Temperature,
Supply 3 V, Supply Reference Mode, Frequency 900 MHz
(micro_SOIC Only)
AD8361
7
REV. A
67mV
370mV
270mV
25mV
5 s PER HORIZONTAL DIVISION
GATE PULSE FOR
900MHz RF TONE
RF INPUT
500mV PER
VERTICAL
DIVISION
Figure 20. Output Response to Modulated Pulse Input
for Various RF Input Levels, Supply 3 V, Modulation
Frequency 900 MHz, No Filter Capacitor
67mV
370mV
25mV
500mV PER
VERTICAL
DIVISION
50 s PER HORIZONTAL DIVISION
RF INPUT
GATE PULSE FOR
900MHz RF TONE
270mV
Figure 21. Output Response to Modulated Pulse Input
for Various RF Input Levels, Supply 3 V, Modulation
Frequency 900 MHz, 0.01
F Filter Capacitor
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
HPE3631A
POWER SUPPLY
C4
0.01 F
C2
100pF
HP8648B
SIGNAL
GENERATOR
C1
0.1 F
R1
75
C3
TEK TDS784C
SCOPE
C5
100pF
TEK P6204
FET PROBE
Figure 22. Hardware Configuration for Output Response
to Modulated Pulse Input
RF INPUT
67mV
370mV
270mV
25mV
500mV PER
VERTICAL
DIVISION
PWDN INPUT
2 s PER HORIZONTAL DIVISION
Figure 23. Output Response Using Power-Down Mode
for Various RF Input Levels, Supply 3 V, Frequency
900 MHz, No Filter Capacitor
67mV
370mV
270mV
25mV
500mV PER
VERTICAL
DIVISION
PWDN INPUT
20 s PER HORIZONTAL DIVISION
RF INPUT
Figure 24. Output Response Using Power-Down Mode
for Various RF Input Levels, Supply 3 V, Frequency
900 MHz, 0.01
F Filter Capacitor
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
HPE3631A
POWER SUPPLY
C2
100pF
HP8648B
SIGNAL
GENERATOR
C1
0.1 F
R1
75
C3
HP8110A
PULSE
GENERATOR
C4
0.01 F
C5
100pF
TEK P6204
FET PROBE
TEK TDS784C
SCOPE
Figure 25. Hardware Configuration for Output Response
Using Power-Down Mode
AD8361
8
REV. A
CARRIER FREQUENCY MHz
7.8
7.6
6.2
100
1000
7.2
6.6
6.4
7.4
6.8
7.0
CONVERSION GAIN
V/V rms
6.0
5.8
5.6
V
S
= 3V
Figure 26. Conversion Gain Change vs. Frequency, Supply
3 V, Ground Reference Mode, Frequency 100 MHz to
2500 MHz, Representative Device
67mV
370mV
270mV
25mV
500mV PER
VERTICAL
DIVISION
SUPPLY
20 s PER HORIZONTAL DIVISION
RF
INPUT
Figure 27. Output Response to Gating On Power Supply,
for Various RF Input Levels, Supply 3 V, Modulation
Frequency 900 MHz, 0.01
F Filter Capacitor
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
C2
100pF
HP8648B
SIGNAL
GENERATOR
C1
R1
75
HP8110A
PULSE
GENERATOR
50
732
C4
0.01 F
AD811
C5
100pF
TEK P6204
FET PROBE
TEK TDS784C
SCOPE
C3
0.1 F
Figure 28. Hardware Configuration for Output Response
to Power Supply Gating Measurements
CONVERSION GAIN V/V rms
7.6
6.9
7.0
7.2
16
PERCENT
7.4
7.8
14
12
10
8
6
4
2
0
Figure 29. Conversion Gain Distribution Frequency
100 MHz, Supply 5 V, Sample Size 3000
IREF MODE INTERCEPT Volts
0.40
0.32
0.34
0.36
PERCENT
0.38
0.44
12
10
8
6
4
2
0
0.42
12
Figure 30. Output Reference, Internal Reference Mode,
Supply 5 V, Sample Size 3000 (micro_SOIC Only)
SREF MODE INTERCEPT Volts
0.72
0.64
0.66
0.68
PERCENT
0.70
0.76
12
10
8
6
4
2
0
0.74
12
12
Figure 31. Output Reference, Supply Reference Mode,
Supply 5 V, Sample Size 3000 (micro_SOIC Only)
AD8361
9
REV. A
CIRCUIT DESCRIPTION
The AD8361 is an rms-responding (mean power) detector pro-
viding an approach to the exact measurement of RF power that
is basically independent of waveform. It achieves this function
through the use of a proprietary technique in which the outputs
of two identical squaring cells are balanced by the action of a
high-gain error amplifier.
The signal to be measured is applied to the input of the first
squaring cell, which presents a nominal (LF) resistance of 225
between the pin RFIN and COMM (connected to the ground
plane). Since the input pin is at a bias voltage of about 0.8 V
above ground, a coupling capacitor is required. By making this
an external component, the measurement range may be extended
to arbitrarily low frequencies.
The AD8361 responds to the voltage, V
IN
, at its input, by squaring
this voltage to generate a current proportional to V
IN
squared.
This is applied to an internal load resistor, across which is con-
nected a capacitor. These form a low-pass filter, which extracts
the mean of V
IN
squared. Although essentially voltage-responding,
the associated input impedance calibrates this port in terms of
equivalent power. Thus 1 mW corresponds to a voltage input of
447 mV rms. In the Application section it is shown how to match
this input to 50
.
The voltage across the low-pass filter, whose frequency may
be arbitrarily low, is applied to one input of an error-sensing
amplifier. A second identical voltage-squaring cell is used to
close a negative feedback loop around this error amplifier.
This second cell is driven by a fraction of the quasi-dc output
voltage of the AD8361. When the voltage at the input of the
second squaring cell is equal to the rms value of V
IN
, the loop
is in a stable state, and the output then represents the rms value of
the input. The feedback ratio is nominally 0.133, making the
rms-dc conversion gain
7.5, that is
V
OUT
= 7.5
V
IN
rms
By completing the feedback path through a second squaring cell,
identical to the one receiving the signal to be measured, several
benefits arise. First, scaling effects in these cells cancel; thus, the
overall calibration may be accurate, even though the open-loop
response of the squaring cells taken separately need not be.
Note that in implementing rms-dc conversion, no reference
voltage enters into the closed-loop scaling. Second, the tracking
in the responses of the dual cells remains very close over tempera-
ture, leading to excellent stability of calibration.
The squaring cells have very wide bandwidth with an intrinsic
response from dc to microwave. However, the dynamic range
of such a system is fairly small, due in part to the much larger
dynamic range at the output of the squaring cells. There are
practical limitations to the accuracy with which very small error
signals can be sensed at the bottom end of the dynamic range,
arising from small random offsets; these set the limit to the
attainable accuracy at small inputs.
On the other hand, the squaring cells in the AD8361 have
a "Class-AB" aspect; the peak input is not limited by their
quiescent bias condition, but is determined mainly by the
eventual loss of square-law conformance. Consequently, the top
end of their response range occurs at a fairly large input level
(about 700 mV rms) while preserving a reasonably accurate
square-law response. The maximum usable range is, in practice,
limited by the output swing. The rail-to-rail output stage can
swing from a few millivolts above ground to less than 100 mV
below the supply. An example of the output induced limit: given
a gain of 7.5 and assuming a maximum output of 2.9 V with a 3 V
supply; the maximum input is (2.9 V rms)/7.5 or 390 mV rms.
Filtering
An important aspect of rms-dc conversion is the need for
averaging (the function is root-MEAN-square). For complex RF
waveforms such as occur in CDMA, the filtering provided by
the on-chip low-pass filter, while satisfactory for CW signals above
100 MHz, will be inadequate when the signal has modulation
components that extend down into the kilohertz region. For this
reason, the FLTR pin is provided: a capacitor attached between
this pin and VPOS can extend the averaging time to very low
frequencies.
Offset
An offset voltage can be added to the output (when using the
micro_SOIC version) to allow the use of A/D converters whose
range does not extend down to ground. However, accuracy at
the low end will be degraded because of the inherent error in this
added voltage. This requires that the pin IREF (internal reference)
should be tied to VPOS and SREF (supply reference) to ground.
In the IREF mode, the intercept is generated by an internal
reference cell, and is a fixed 350 mV, independent of the supply
voltage. To enable this intercept, IREF should be open-circuited,
and SREF should be grounded.
In the SREF mode, the voltage is provided by the supply. To
implement this mode, tie IREF to VPOS and SREF to VPOS. The
offset is then proportional to the supply voltage, and is 400 mV
for a 3 V supply and 667 mV for a 5 V supply.
USING THE AD8361
Basic Connections
Figures 32, 33, and 34 show the basic connections for the
micro_SOIC version AD8361 in its three operating modes. In all
modes, the device is powered by a single supply of between 2.7 V
and 5.5 V. The VPOS pin is decoupled using 100 pF and 0.01
F
capacitors. The quiescent current of 1.1 mA in operating mode
can be reduced to 1
A by pulling the PWDN pin up to VPOS.
A 75
external shunt resistance combines with the ac-coupled
input to give an overall broadband input impedance near 50
.
Note that the coupling capacitor must be placed between the in-
put and the shunt impedance. Input impedance and input coupling
are discussed in more detail below.
The input coupling capacitor combines with the internal input
resistance (Figure 13) to give a high-pass corner frequency
given by the equation
f
C
R
dB
C
IN
3
1
2
=
AD8361
10
REV. A
With the 100 pF capacitor shown in Figures 3234, the high-
pass corner frequency is about 8 MHz.
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
C
C
100pF
R1
75
CFLTR
1
2
3
4
5
6
7
8
0.01 F
100pF
+V
S
2.7 5.5V
RFIN
V rms
Figure 32. Basic Connections for Ground Referenced Mode
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
C
C
100pF
R1
75
CFLTR
1
2
3
4
5
6
7
8
0.01 F
100pF
+V
S
2.7 5.5V
RFIN
V rms
Figure 33. Basic Connections for Internal Reference Mode
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
C
C
100pF
R1
75
CFLTR
1
2
3
4
5
6
7
8
0.01 F
100pF
+V
S
2.7 5.5V
RFIN
V rms
Figure 34. Basic Connections for Supply Referenced Mode
The output voltage is nominally 7.5 times the input rms voltage
(a conversion gain of 7.5 V/V rms). Three different modes of
operation are set by the pins SREF and IREF. In addition to the
ground referenced mode shown in Figure 32, where the output
voltage swings from around near ground to 4.9 V on a 5.0 V
supply, two additional modes allow an offset voltage to be added to
the output. In the internal reference mode, (Figure 33), the
output voltage swing is shifted upward by an internal reference
voltage of 350 mV. In supply referenced mode (Figure 34), an
offset voltage of V
S
/7.5 is added to the output voltage. Table I
summarizes the connections, output transfer function and mini-
mum output voltage (i.e., zero signal) for each mode.
Output Swing
Figure 35 shows the output swing of the AD8361 for a 5 V supply
voltage for each of the three modes. It is clear from Figure 35,
that operating the device in either internal reference mode or
supply referenced mode, will reduce the effective dynamic range as
the output headroom decreases. The response for lower supply
voltages is similar (in the supply referenced mode, the offset is
smaller), but the dynamic range will be reduced further, as head-
room decreases. Figure 36 shows the response of the AD8361 to
a CW input for various supply voltages.
INPUT V rms
5.0
4.5
0.0
0
0.5
0.1
0.2
0.3
0.4
3.0
1.5
1.0
0.5
4.0
3.5
2.0
2.5
OUTPUT
Volts
SUPPLY REF
INTERNAL REF
GROUND REF
0.6
0.7
0.8
Figure 35. Output Swing for Ground, Internal and Supply
Referenced Mode. VPOS = 5 V (micro_SOIC Only)
INPUT V rms
5.5
1.5
0
0.5
0.1
0.2
0.3
0.4
4.0
3.0
2.5
2.0
5.0
4.5
3.5
OUTPUT
Volts
1.0
0.5
0.0
5.5V
5.0V
3.0V
2.7V
0.6
0.7
0.8
Figure 36. Output Swing for Supply Voltages of 2.7 V,
3.0 V, 5.0 V and 5.5 V (micro_SOIC Only)
Dynamic Range
Because the AD8361 is a linear responding device with a nomi-
nal transfer function of 7.5 V/V rms, the dynamic range in dB is
not clear from plots such as Figure 35. As the input level is
increased in constant dB steps, the output step size (per dB)
will also increase. Figure 37 shows the relationship between the
output step size (i.e., mV/dB) and input voltage for a nominal
transfer function of 7.5 V/V rms.
Table I. Connections and Nominal Transfer Function for
Ground, Internal, and Supply Reference Modes
Output
Reference
Intercept
Mode
IREF
SREF
(No Signal)
Output
Ground
VPOS
COMM
Zero
7.5 V
IN
Internal
OPEN
COMM
0.350 V
7.5 V
IN
+ 0.350 V
Supply
VPOS
VPOS
V
S
/7.5
7.5 V
IN
+ V
S
/7.5
AD8361
11
REV. A
INPUT mV
700
200
0
500
100
200
300
400
500
400
300
600
mV/dB
100
0
600
700
800
Figure 37. Idealized Output Step Size as Function of Input
Voltage
Plots of output voltage vs. input voltage result in a straight line. It
may sometimes be more useful to plot the error on a logarith-
mic scale, as shown in Figure 38. The deviation of the plot for
the ideal straight line characteristic is caused by output clipping
at the high end and by signal offsets at the low end. It should
however be noted that offsets at the low end can be either posi-
tive or negative, so that this plot could also trend upwards at the
low end. Figures 5, 6, 8, and 9 show a
3 sigma distribution of
device error for a large population of devices.
INPUT V rms
2.0
0.5
0.01
0.5
0.0
1.5
1.0
ERROR
dB
1.0
1.5
2.0
1.0
1.9GHz
2.5GHz
900MHz
100MHz
100MHz
0.02
(21dBm)
0.1
(7dBm)
0.4
(+5dBm)
Figure 38. Representative Unit, Error in dB vs. Input Level,
V
S
= 2.7 V
It is also apparent in Figure 38 that the error plot tends to
shift to the right with increasing frequency. Because the input
impedance decreases with frequency, the voltage actually applied
to the input will also tend to decrease (assuming a constant source
impedance over frequency). The dynamic range is almost con-
stant over frequency, but with a small decrease in conversion gain
at high frequency.
Input Coupling and Matching
The input impedance of the AD8361 decreases with increasing
frequency in both its resistive and capacitive components (Figure
13). The resistive component varies from 225
at 100 MHz
down to about 95
at 2.5 GHz.
A number of options exist for input matching. For operation at
multiple frequencies, a 75
shunt to ground, as shown in Figure
39a, will provide the best overall match. For use at a single fre-
quency, a resistive or a reactive match can be used. By plotting the
input impedance on a Smith Chart, the best value for a
resistive match can be calculated. The VSWR can be held below
1.5 at frequencies up to 1 GHz, even as the input impedance
varies from part to part. (Both input impedance and input
capacitance can vary by up to
20% around their nominal values.)
At very high frequencies (i.e., 1.8 GHz to 2.5 GHz), a shunt
resistor will not be sufficient to reduce the VSWR below 1.5.
Where VSWR is critical, remove shunt component and insert
an inductor in series with the coupling capacitor as shown in
Figure 39b.
Table II gives recommended shunt resistor values for various
frequencies and series inductor values for high frequencies. The
coupling capacitor, C
C
, essentially acts as an ac-short and plays
no intentional part in the matching.
AD8361
RFIN
RFIN
R
SH
C
C
a. Broadband Resistor Match
AD8361
C
C
RFIN
RFIN
L
M
b. Series Inductor Match
AD8361
C
C
RFIN
RFIN
L
M
C
M
c. Narrowband Reactive Match
AD8361
C
C
RFIN
RFIN
R
SERIES
d. Attenuating the Input Signal
Figure 39. Input Coupling/Matching Options
Table II. Recommended Component Values for Resistive or
Inductive Input Matching (Figures 39a and 39b)
Frequency
Matching Component
100 MHz
63.4
Shunt
800 MHz
75
Shunt
900 MHz
75
Shunt
1800 MHz
150
Shunt or 4.7 nH Series
1900 MHz
150
Shunt or 4.7 nH Series
2500 MHz
150
Shunt or 2.7 nH Series
AD8361
12
REV. A
Alternatively, a reactive match can be implemented using a shunt
inductor to ground and a series capacitor as shown in Figure
39c. A method for hand calculating the appropriate matching
components is shown on page 12 of the AD8306 data sheet.
Matching in this manner results in very small values for C
M
,
especially at high frequencies. As a result, a stray capacitance as
small as 1 pF can significantly degrade the quality of the match.
The main advantage of a reactive match is the increase in sensi-
tivity that results from the input voltage being "gained up" (by
the square root of the impedance ratio) by the matching network.
Table III shows recommended values for reactive matching.
Table III. Recommended Values for a Reactive Input Match
(Figure 39c)
Frequency
C
M
L
M
MHz
pF
nH
100
16
180
800
2
15
900
2
12
1800
1.5
4.7
1900
1.5
4.7
2500
1.5
3.3
Input Coupling Using a Series Resistor
Figure 39d shows a technique for coupling the input signal
into the AD8361, which may be applicable where the input signal
is much larger than the input range of the AD8361. A series
resistor combines with the input impedance of the AD8361 to
attenuate the input signal. Since this series resistor forms a
divider with the frequency-dependent input impedance, the
apparent gain changes greatly with frequency. However, this
method has the advantage of very little power being "tapped
off" in RF power transmission applications. If the resistor is large
compared to the transmission line's impedance then the VSWR of
the system is relatively unaffected.
FREQUENCY MHz
200
0
500
RESISTANCE
100
0
250
150
50
1000
1500
2000
2500
3000
3500
0.2
0.5
0.8
1.1
1.4
1.7
CAPACITANCE
pF
Figure 40. Input Impedance vs. Frequency, Supply 3 V,
SOT-23-6L
Selecting the Filter Capacitor
The AD8361's internal 27 pF filter capacitor is connected in
parallel with an internal resistance that varies with signal level
from 2 k
for small signals to 500 for large signals. The
resulting low-pass corner frequency between 3 MHz and 12 MHz
provides adequate filtering for all frequencies above 240 MHz
(i.e., ten times the frequency at the output of the squarer, which
is twice the input frequency). However, signals with high peak-
to-average ratios, such as CDMA or W-CDMA signals, and
with low frequency components, require additional filtering.
TDMA signals, such as GSM, PDC, or PHS have a peak-to-
average ratio that is close to that of a sinusoid, and the internal
filter is adequate.
The filter capacitance of the AD8361 can be augmented by
connecting a capacitor between Pin 6 (FLTR) and VPOS.
Table IV shows the effect of several capacitor values for various
communications standards with high peak-to-average ratios along
with the residual ripple at the output, in peak-to-peak and rms
volts. Note that large filter capacitors will increase the enable
and pulse response times, as discussed below.
Table IV. Effect of Waveform and C
FILT
on Residual AC
Output
Residual AC
Waveform
C
FILT
V dc
mV p-p
mV rms
IS95 Reverse Link
Open
0.5
550
100
1.0
1000
180
2.0
2000
360
0.01
F
0.5
40
6
1.0
160
20
2.0
430
60
0.1
F
0.5
20
3
1.0
40
6
2.0
110
18
IS95 8-Channel
0.01
F
0.5
290
40
Forward Link
1.0
975
150
2.0
2600
430
0.1
F
0.5
50
7
1.0
190
30
2.0
670
95
W-CDMA 15
0.01
F
0.5
225
35
Channel
1.0
940
135
2.0
2500
390
0.1
F
0.5
45
6
1.0
165
25
2.0
550
80
Operation at Low Frequencies
Although the AD8361 is specified for operation up to 2.5 GHz,
there is no lower limit on the operating frequency. It is only nec-
essary to increase the input coupling capacitor to reduce the
corner frequency of the input high-pass filter (use an input resis-
tance of 225
for frequencies below 100 MHz). It is also
necessary to increase the filter capacitor so that the signal at the
output of the squaring circuit is free of ripple. The corner fre-
quency will be set by the combination of the internal resistance of
2 k
and the external filter capacitance.
Power Consumption, Enable and Power-On
The quiescent current consumption of the AD8361 varies with
the size of the input signal from about 1 mA for no signal up to
7 mA at an input level of 0.66 V rms (9.4 dBm re 50
). If the
input is driven beyond this point, the supply current increases
steeply (see Figure 12). There is little variation in quiescent
current with power supply voltage.
AD8361
13
REV. A
The AD8361 can be disabled either by pulling the PWDN (Pin 4)
to VPOS or by simply turning off the power to the device. While
turning off the device obviously eliminates the current consump-
tion, disabling the device reduces the leakage current to less
than 1
A. Figures 23 and 24 show the response of the output of
the AD8361 to a pulse on the PWDN pin, with no capacitance and
with a filter capacitance of 0.01
F respectively; the turn-on time is
a function of the filter capacitor. Figure 27 shows a plot of the
output response to the supply being turned on (i.e., PWDN is
grounded and VPOS is pulsed) with a filter capacitor of 0.01
F
Again, the turn-on time is strongly influenced by the size of the
filter capacitor.
If the input of the AD8361 is driven while the device is disabled
(PWDN = VPOS), the leakage current of less than 1
A will
increase as a function of input level. When the device is dis-
abled, the output impedance increases to around 16 k
.
Volts to dBm Conversion
In many of the plots, the horizontal axis is scaled in both rms
volts and dBm. In all cases, dBm are calculated relative to an
impedance of 50
. To convert between dBm and volts in a
50
. system, the following equations can be used. Figure 40
shows this conversion in graphical form.
Power dBm
V rms
W
V rms
V rms
W
dBm
dBm
(
)
log
(
)
.
log (
(
) )
.
log
log
/
=
=
=
=
(
)
10
50
0 001
10
20
0 001
50
10
10
20
2
2
1
1
V rms
dBm
+20
+10
0
10
20
30
40
1
0.1
0.01
0.001
Figure 41. Conversion from dBm to rms Volts
Output Drive Capability and Buffering
The AD8361 is capable of sourcing an output current of approxi-
mately 3 mA. If additional current is required, a simple buffering
circuit can be used as shown in Figure 42c. Similar circuits
can be used to increase or decrease the nominal conversion gain of
7.5 V/V rms (Figure 42a and 42b). In Figure 42b, the AD8031
buffers a resistive divider to give a slope of 3.75 V/V rms. In Figure
42a, the op amp's gain of two increases the slope to 15 V/V rms.
Using other resistor values, the slope can be changed to an
arbitrary value. The AD8031 rail-to-rail op amp, used in these
examples can swing from 50 mV to 4.95 V on a single 5 V supply
and operate at supply voltages down to 2.7 V. If high output
current is required (>10 mA), the AD8051, which also has rail-
to-rail capability, can be used, down to a supply voltage of 3 V. It
can deliver up to 45 mA of output current.
100pF
0.01 F
AD8361
VOUT
VPOS
COMM PWDN
5k
5k
0.01 F
5V
15V/V rms
AD8031
a. Slope of 15 V/V rms
AD8361
VOUT
VPOS
COMM PWDN
0.01 F
5V
3.75V/V rms
AD8031
10k
5k
5k
100pF
0.01 F
b. Slope of 3.75 V/V rms
100pF
AD8361
VOUT
VPOS
COMM PWDN
0.01 F
0.01 F
5V
7.5V/V rms
AD8031
c. Slope of 7.5 V/V rms
Figure 42. Output Buffering Options
OUTPUT REFERENCE TEMPERATURE DRIFT
COMPENSATION
The error due to low temperature drift of the AD8361 can be
reduced if the temperature is known. Many systems incorporate
a temperature sensor; the output of the sensor is typically digi-
tized, facilitating a software correction. Using this information,
only a two-point calibration at ambient is required.
The output voltage of the AD8361 at ambient (25
C) can be
expressed by the equation:
V
GAIN
V
V
OUT
IN
OS
=
(
)
+
where GAIN is the conversion gain in V/V rms and V
OS
is the
extrapolated output voltage for an input level of 0 V. GAIN and
V
OS
(also referred to as Intercept and Output Reference) can be
calculated at ambient using a simple two-point calibration;
that is, by measuring the output voltages for two specific input
levels. Calibration at roughly 35 mV rms (16 dBm) and
250 mV rms (+1 dBm) is recommended for maximum linear
dynamic range. However, alternative levels and ranges can be
AD8361
14
REV. A
chosen to suit the application. GAIN and V
OS
are then calculated
using the equations:
GAIN
V
V
V
V
OUT
OUT
IN
IN
=
-
(
)
-
(
)
2
1
2
1
V
V
GAIN
V
OS
OUT
IN
=
-
(
)
1
1
Both GAIN and V
OS
drift over temperature. However, the drift
of V
OS
has a bigger influence on the error relative to the output.
This can be seen by inserting data from Figures 14 and 17 (con-
version gain and intercept drift) into the equation for V
OUT
. These
plots are consistent with Figures 10 and 11 which show that the
error due to temperature drift decreases with increasing input
level. This results from the offset error having a diminishing
influence with increasing level on the overall measurement error.
From Figure 14, the average Intercept drift is 0.43 mV/
C from
40
C to +25C and 0.17 mV/C from +25C to +85C. For a
less rigorous compensation scheme, the average drift over the
complete temperature range can be calculated:
DRIFT
V
C
V
V
C
C
VOS
/
.
.
(
)
=
- -
(
)
+ - -
(
)
0 010
0 028
85
40
= 0.000304 V/
C
With the drift of V
OS
included, the equation for V
OUT
becomes:
Table V. Evaluation Board Configuration Options
Component
Function
Default Condition
TP1, TP2
Ground and Supply Vector Pins.
Not Applicable
SW1
Device Enable. When in Position A, the PWDN pin is connected to +V
S
and
SW1 = B
the AD8361 is in power-down mode. In Position B, the PWDN pin is grounded,
putting the device in operating mode.
SW2/SW3
Operating Mode. Selects either Ground Referenced Mode, Internal Reference
SW2 = A, SW3 = B
Mode or Supply Reference Mode. See Table I for more details.
(Ground Reference Mode)
C1, R2
Input Coupling. The 75
resistor in position R2 combines with the AD8361's
R2 = 75
(Size 0402)
internal input impedance to give a broadband input impedance of around 50
.
C1 = 100 pF (Size 0402)
For more precise matching at a particular frequency, R2 can be replaced by a
different value (see Input Matching and Figure 39).
Capacitor C1 ac-couples the input signal and creates a high-pass input filter
whose corner frequency is equal to approximately 8 MHz. C1 can be increased
for operation at lower frequencies. If resistive attenuation is desired at the input,
series resistor R1, which is nominally 0
, can be replaced by an appropriate value.
C2, C3, R6
Power Supply Decoupling. The nominal supply decoupling of 0.01
F and
C2 = 0.01
F (Size 0402)
100 pF. A series inductor or small resistor can be placed in R6 for additional
C3 = 100 pF (Size 0402)
decoupling.
R6 = 0
(Size 0402)
C5
Filter Capacitor. The internal 50 pF averaging capacitor can be augmented
C5 = 1 nF (Size 0603)
by placing a capacitance in C5.
C4, R5
Output Loading. Resistors and capacitors can be placed in C4 and R5 to
C4 = R5 = Open
load test V rms.
(Size 0603)
V
GAIN
V
V
DRIFT
TEMP
C
OUT
IN
OS
VOS
=
(
)
+
+
-
(
)
25
The equation can be rewritten to yield a temperature compen-
sated value for V
IN
.
V
V
V
DRIFT
TEMP
C
GAIN
IN
OUT
OS
VOS
=
-
-
-
(
)
(
)
25
EVALUATION BOARD
Figures 43 and 46 show the schematic of the AD8361 evalua-
tion board. Note that uninstalled components are drawn in as
dashed. The layout and silkscreen of the component side are
shown in Figures 44, 45, 47, and 48. The board is powered by a
single supply in the range, 2.7 V to 5.5 V. The power supply
is decoupled by 100 pF and 0.01
F capacitors. Additional
decoupling, in the form of a series resistor or inductor in R6,
can also be added. Table V details the various configuration
options of the evaluation board.
AD8361
15
REV. A
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
C1
100pF
R2
75
C5
1
2
3
4
5
6
7
8
C2
0.01 F
RFIN
Vrms
C3
100pF
VPOS
V
S
SW2
V
S
SW3
SW1
A
B
A
B
R5
(OPEN
)
R4
0
1nF
C4
(OPEN
)
R6
0
A
B
TP2
TP1
VPOS
VPOS
Figure 43. Evaluation Board Schematic micro_SOIC
Figure 44. Layout of Component Side micro_SOIC
Figure 45. Silkscreen of Component Side micro_SOIC
C5
1nF
C3
100pF
C2
0.01 F
J2
J3
J1
R2
75
TP2
R4
0
C4
OPEN
R5
OPEN
AD8361
VPOS
RFIN
PWDN
VRMS
FLTR
COMM
1
2
3
4
5
6
TP1
C1
100pF
SW1
1
2
3
R7
50
VPOS
Figure 46. Evaluation Board Schematic, SOT-23-6L
Figure 47. Layout of the Component Side, SOT-23-6L
Figure 48. Silkscreen of the Component Side, SOT-23-6L
16
C3716a26/00 (rev. A) 01088
PRINTED IN U.S.A.
AD8361
REV. A
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
C1
0.1 F
R1
75
1
2
3
4
5
6
7
8
RFIN
C3
C4
0.1 F
C2
100pF
IREF
PWDN
VPOS
SREF
VRMS
Figure 49. Characterization Board
AD8361
CHARACTERIZATION
BOARD
RFIN
PRUP
+V
S
SREF
IREF
VRMS
DC OUTPUT
RF SIGNAL
SMIQ038B
RF SOURCE
IEEE BUS
PC CONTROLLER
DC MATRIX / DC SUPPLIES / DMM
DC SOURCES
3dB
ATTENUATOR
Figure 50. Characterization Setup
8-Lead micro_SOIC Package
(RM-8)
0.009 (0.23)
0.005 (0.13)
0.028 (0.70)
0.016 (0.40)
6
0
0.037 (0.95)
0.030 (0.75)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
0.193
(4.90)
BSC
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.016 (0.40)
0.010 (0.25)
0.043
(1.10)
MAX
6-Lead SOT-23-6L Package
(RT-6)
0.122 (3.10)
0.106 (2.70)
PIN 1
0.118 (3.00)
0.098 (2.50)
0.075 (1.90)
BSC
0.037 (0.95) BSC
1
3
4
5
6
2
0.071 (1.80)
0.059 (1.50)
0.009 (0.23)
0.003 (0.08)
0.022 (0.55)
0.014 (0.35)
10
0
0.020 (0.50)
0.010 (0.25)
0.006 (0.15)
0.000 (0.00)
0.051 (1.30)
0.035 (0.90)
SEATING
PLANE
0.057 (1.45)
0.035 (0.90)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Problems caused by impedance mismatch may arise using the
evaluation board to examine the AD8361 performance. One
way to reduce these problems is to put a coaxial 3 dB attenuator
on the RFIN SMA connector. Mismatches at the source, cable,
and cable interconnection, as well as those occurring on the
evaluation board can cause these problems.
A simple (and common) example of such problem is triple travel
due to mismatch at both the source and the evaluation board.
Here the signal from the source reaches the evaluation board
and mismatch causes a reflection. When that reflection reaches
the source mismatch, it causes a new reflection, which travels
back to the evaluation board adding to the original signal inci-
dent at the board. The resultant voltage will vary with both
cable length and frequency dependent upon the relative phase of
the initial and reflected signals. Placing the 3 dB pad at the
input of the board improves the match at the board and thus
reduces the sensitivity to mismatches at the source. When such
precautions are taken, measurements will be less sensitive to
cable length and other fixturing issues. In an actual application
when the distance between AD8361 and source is short and well
defined, this 3 dB attenuator is not needed.
CHARACTERIZATION SETUPS
Equipment
The primary characterization setup is shown in Figure 50. The
signal source used was a Rohde & Schwarz SMIQ03B, version
3.90HX. The modulated waveforms used for IS95 reverse link,
IS95 nine active channels forward (Forward Link 18 setting),
W-CDMA 4- and 15-channel were generated using the default
settings coding and filtering. Signal levels were calibrated into a
50
impedance.
Analysis
The conversion gain and output reference are derived using the
coefficients of a linear regression performed on data collected in
its central operating range (35 mV rms to 250 mV rms). This
range was chosen to avoid areas of operation where offset distorts
the linear response. Error is stated in two forms Error from Linear
Response to CW waveform and Output Delta from 25
C performance.
The Error from Linear Response to CW waveform is the difference
in output from the ideal output defined by the conversion gain
and output reference. This is a measure of both the linearity of
the device response to both CW and modulated waveforms. The
error in dB uses the conversion gain multiplied times the input
as its reference. Error from Linear Response to CW waveform is not a
measure of absolute accuracy, since it is calculated using the
gain and output reference of each device. But it does show the
linearity and effect of modulation on the device response.
Error from 25
C performance uses the performance of a given
device and waveform type as the reference; it is predomi-
nantly a measure of output variation with temperature.
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