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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD9814

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

Complete 14-Bit

CCD/CIS Signal Processor

FUNCTIONAL BLOCK DIAGRAM

9-BIT

DAC

PGA

CDS

PGA

9-BIT

DAC

CDS

9-BIT

DAC

PGA

CDS

3:1

MUX

14-BIT

ADC

14:8

MUX

BANDGAP

REFERENCE

CONFIGURATION

REGISTER

MUX

REGISTER

BLUE

GREEN

RED

BLUE

GREEN

RED

GAIN
REGISTERS

OFFSET
REGISTERS

DIGITAL

CONTROL

INTERFACE

INPUT

CLAMP

BIAS

AD9814

DRVDD

DRVSS

AVDD

AVSS

CAPT

CAPB

AVDD

AVSS

CML

OEB

DOUT

SCLK

SLOAD

SDATA

ADCCLK

CDSCLK2

CDSCLK1

OFFSET

VINB

VING

VINR

FEATURES
14-Bit 10 MSPS A/D Converter
No Missing Codes Guaranteed
3-Channel Operation Up to 10 MSPS
1-Channel Operation Up to 7 MSPS
Correlated Double Sampling
1-6x Programmable Gain

300 mV Programmable Offset

Input Clamp Circuitry
Internal Voltage Reference
Multiplexed Byte-Wide Output (8+6 Format)
3-Wire Serial Digital Interface
+3/+5 V Digital I/O Compatibility
28-Lead SOIC Package
Low Power CMOS: 330 mW (Typ)
Power-Down Mode: <1 mW

APPLICATIONS
Flatbed Document Scanners
Film Scanners
Digital Color Copiers
Multifunction Peripherals

PRODUCT DESCRIPTION

The AD9814 is a complete analog signal processor for CCD
imaging applications. It features a 3-channel architecture de-
signed to sample and condition the outputs of trilinear color
CCD arrays. Each channel consists of an input clamp, Corre-
lated Double Sampler (CDS), offset DAC and Programmable
Gain Amplifier (PGA), multiplexed to a high performance 14-
bit A/D converter.

The CDS amplifiers may be disabled for use with sensors such
as Contact Image Sensors (CIS) and CMOS active pixel sen-
sors, which do not require CDS.

The 14-bit digital output is multiplexed into an 8-bit output
word that is accessed using two read cycles. The internal regis-
ters are programmed through a 3-wire serial interface, and pro-
vide adjustment of the gain, offset, and operating mode.

The AD9814 operates from a single +5 V power supply, typi-
cally consumes 330 mW of power, and is packaged in a 28-lead
SOIC.

REV. 0

AD9814SPECIFICATIONS

ANALOG SPECIFICATIONS

J-Grade

K-Grade

Parameter

Min

Typ

Max

Min

Typ

Max

Units

CONVERSION RATE

3-Channel Mode with CDS

MSPS

1-Channel Mode with CDS

MSPS

ACCURACY (Entire Signal Path)

ADC Resolution

Bits

Integral Nonlinearity

(INL)

+2.5/6.0

11.0

LSB

INL @ 10 MHz

+4.0/7.0

LSB

Differential Nonlinearity (DNL)

+0.6/0.5

1.0

LSB

DNL @ 10 MHz

+0.8/0.6

LSB

No Missing Codes Guaranteed

Bits

Offset Error

104

Gain Error

2.2

5.3

% FSR

ANALOG INPUTS

Input Signal Range

4.0

V p-p

Allowable Reset Transient

1.0

Input Limits

AVSS 0.3

AVDD + 0.3

AVSS 0.3

AVDD + 0.3

Input Capacitance

Input Bias Current

AMPLIFIERS

PGA Gain at Minimum

V/V

PGA Gain at Maximum

5.8

V/V

PGA Resolution

Steps

PGA Monotonicity

Guaranteed

Programmable Offset at Minimum

300

Programmable Offset at Maximum

+300

Programmable Offset Resolution

512

Steps

Programmable Offset Monotonicity

Guaranteed

NOISE AND CROSSTALK

Input Referred Noise @ PGA Min

130

V rms

Total Output Noise @ PGA Min

0.55

LSB rms

Input Referred Noise @ PGA Max

V rms

Total Output Noise @ PGA Max

2.0

LSB rms

Channel-Channel Crosstalk

LSB

POWER SUPPLY REJECTION

AVDD = +5 V

0.25 V

0.07

0.3

% FSR

Differential VREF (@ +25

CAPT-CAPB (4 V Input Range)

2.0

1.9

2.0

2.1

CAPT-CAPB (2 V Input Range)

1.0

0.94

1.0

1.06

TEMPERATURE RANGE

Operating

+70

Storage

+150

POWER SUPPLIES

AVDD

+4.75

+5.0

+5.25

+4.75

+5.0

+5.25

DRVDD

+3.0

+5.0

+5.25

+3.0

+5.0

+5.25

Total Operating Current

AVDD

DRVDD

1.8

Power-Down Mode Current

150

Power Dissipation

330

450

Power Dissipation @ 10 MHz

355

Power Dissipation (1-Channel Mode)

220

265

MIN

to T

MAX

, AVDD = +5 V, DRVDD = +5 V, 3-Channel CDS Mode, f

ADCCLK

= 6 MHz, f

CDSCLK1

= f

CDSCLK2

2 MHz, PGA Gain = 1, Input Range = 4 V, unless otherwise noted.)

REV. 0

AD9814

DIGITAL SPECIFICATIONS

Parameter

Symbol

Min

Typ

Max

Units

LOGIC INPUTS

High Level Input Voltage

2.6

Low Level Input Voltage

0.8

High Level Input Current

Low Level Input Current

Input Capacitance

LOGIC OUTPUTS

High Level Output Voltage

4.5

Low Level Output Voltage

0.1

High Level Output Current

Low Level Output Current

Specifications subject to change without notice.

TIMING SPECIFICATIONS

Parameter

Symbol

Min

Typ

Max

Units

CLOCK PARAMETERS

3-Channel Pixel Rate

PRA

300

500

1-Channel Pixel Rate

PRB

140

ADCCLK Pulsewidth

ADCLK

CDSCLK1 Pulsewidth

CDSCLK2 Pulsewidth

CDSCLK1 Falling to CDSCLK2 Rising

C1C2

ADCCLK Falling to CDSCLK2 Rising

ADC2

CDSCLK2 Rising to ADCCLK Rising

C2ADR

CDSCLK2 Falling to ADCCLK Falling

C2ADF

CDSCLK2 Falling to CDSCLK1 Rising

C2C1

ADCCLK Falling to CDSCLK1 Rising

ADC1

Aperture Delay for CDS Clocks

SERIAL INTERFACE

Maximum SCLK Frequency

SCLK

MHz

SLOAD to SCLK Set-Up Time

SCLK to SLOAD Hold Time

SDATA to SCLK Rising Set-Up Time

SCLK Rising to SDATA Hold Time

SCLK Falling to SDATA Valid

RDV

DATA OUTPUT

Output Delay

3-State to Data Valid

Output Enable High to 3-State

Latency (Pipeline Delay)

3 (Fixed)

Cycles

Specifications subject to change without notice.

MIN

to T

MAX

, AVDD = +5 V, DRVDD = +5 V, CDS Mode, f

ADCCLK

= 6 MHz, f

CDSCLK1

= f

CDSCLK2

= 2 MHz,

= 10 pF, unless otherwise noted.)

MIN

to T

MAX

, AVDD = +5 V, DRVDD = +5 V)

NOTES

The Integral Nonlinearity in measured using the "fixed endpoint" method, NOT using a "best-fit" calculation. See Definitions of Specifications.

The Gain Error specification is dominated by the tolerance of the internal differential voltage reference.

Linear input signal range is from 0 V to 4 V when the CCD's reference level is clamped to 4 V by the AD9814's input clamp. A larger reset transient can be tolerated

by using the 3 V clamp level instead of the nominal 4 V clamp level. Linear input signal range will be from 0 V to 3 V when using the 3 V clamp level.

1V TYP

RESET TRANSIENT

4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE)

4V p-p MAX INPUT SIGNAL RANGE

GND

The input limits are defined as the maximum tolerable voltage levels into the AD9814. These levels are not intended to be in the linear input range of the device.

Signals beyond the input limits will turn on the overvoltage protection diodes.

The PGA Gain is approximately "linear in dB" and follows the equation:

Gain

[

. [

]

5 8

4 8

63 G

where G is the register value. See Figure 13.

Specifications subject to change without notice.

REV. 0

AD9814

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9814 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

With
Respect

Parameter

Min

Max

Units

VIN, CAPT, CAPB

AVSS

0.3

AVDD + 0.3

Digital Inputs

AVSS

0.3

AVDD + 0.3

AVDD

AVSS

0.5

+6.5

DRVDD

DRVSS

0.5

+6.5

AVSS

DRVSS

0.3

+0.3

Digital Outputs

DRVSS

0.3

DRVDD + 0.3

Junction Temperature

+150

Storage Temperature

+150

Lead Temperature

(10 sec)

+300

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.

ORDERING GUIDE

Temperature

Package

Model

Range

Description

AD9814JR

C to +70

28-Lead 300 Mil SOIC

AD9814KR

C to +70

28-Lead 300 Mil SOIC

THERMAL CHARACTERISTICS

Thermal Resistance
28-Lead 300 Mil SOIC

= 71.4

C/W

= 23

C/W

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

AD9814

CDSCLK1

AVDD

CDSCLK2

AVSS

ADCCLK

VINR

OEB

OFFSET

DRVDD

VING

DRVSS

CML

(MSB) D7

VINB

CAPT

CAPB

AVSS

AVDD

SLOAD

SCLK

(LSB) D0

SDATA

PIN FUNCTION DESCRIPTIONS

Pin
N

Name

Type

Description

CDSCLK1

CDS Reference Level Sampling
Clock

CDSCLK2

CDS Data Level Sampling Clock

ADCCLK

A/D Converter Sampling Clock

OEB

Output Enable, Active Low

DRVDD

Digital Output Driver Supply

DRVSS

Digital Output Driver Ground

Data Output MSB. ADC DB13
High Byte, ADC DB5 Low Byte

Data Output. ADC DB12 High
Byte, ADC DB4 Low Byte

Data Output. ADC DB11 High
Byte, ADC DB3 Low Byte

Data Output. ADC DB10 High
Byte, ADC DB2 Low Byte

Data Output. ADC DB9 High
Byte, ADC DB1 Low Byte

Data Output. ADC DB8 High
Byte, ADC DB0 Low Byte

Data Output. ADC DB7 High
Byte, Don't Care Low Byte

Data Output LSB. ADC DB6
High Byte, Don't Care Low Byte

SDATA

DI/DO

Serial Interface Data Input/Output

SCLK

Serial Interface Clock Input

SLOAD

Serial Interface Load Pulse

AVDD

+5 V Analog Supply

AVSS

Analog Ground

CAPB

ADC Bottom Reference Voltage
Decoupling

CAPT

ADC Top Reference Voltage
Decoupling

VINB

Analog Input, Blue Channel

CML

Internal Bias Level Decoupling

VING

Analog Input, Green Channel

OFFSET

Clamp Bias Level Decoupling

VINR

Analog Input, Red Channel

AVSS

Analog Ground

AVDD

+5 V Analog Supply

TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO =
Digital Output, P = Power.

REV. 0

AD9814

DEFINITIONS OF SPECIFICATIONS

INTEGRAL NONLINEARITY (INL)

Integral nonlinearity error refers to the deviation of each indi-
vidual code from a line drawn from "zero scale" through "posi-
tive full scale." The point used as "zero scale" occurs 1/2 LSB
before the first code transition. "Positive full scale" is defined as
a level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.

DIFFERENTIAL NONLINEARITY (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. No missing codes guaranteed to
14-bit resolution indicates that all 16384 codes, respectively,
must be present over all operating ranges.

OFFSET ERROR

The first ADC code transition should occur at a level 1/2 LSB
above the nominal zero scale voltage. The offset error is the
deviation of the actual first code transition level from the ideal
level.

GAIN ERROR

The last code transition should occur for an analog value
1 1/2 LSB below the nominal full-scale voltage. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between the first and last
code transitions.

INPUT REFERRED NOISE

The rms output noise is measured using histogram techniques.
The ADC output codes' standard deviation is calculated in
LSB, and converted to an equivalent voltage, using the relation-
ship 1 LSB = 4 V/16384 = 244 mV. The noise is then referred
to the input of the AD9814 by dividing by the PGA gain.

CHANNEL-TO-CHANNEL CROSSTALK

In an ideal three channel system, the signal in one channel will
not influence the signal level of another channel. The channel-
to-channel crosstalk specification is a measure of the change that
occurs in one channel as the other two channels are varied. In
the AD9814, one channel is grounded and the other two chan-
nels are exercised with full-scale input signals. The change in the
output codes from the first channel is measured and compared
with the result when all three channels are grounded. The differ-
ence is the channel-to-channel crosstalk, stated in LSB.

APERTURE DELAY

The aperture delay is the time delay that occurs from when a
sampling edge is applied to the AD9814 until the actual sample
of the input signal is held. Both CDSCLK1 and CDSCLK2
sample the input signal during the transition from high to low,
so the aperture delay is measured from each clock's falling edge
to the instant the actual internal sample is taken.

POWER SUPPLY REJECTION

Power Supply Rejection specifies the maximum full-scale change
that occurs from the initial value when the supplies are varied
over the specified limits.

REV. 0

AD9814

PIXEL N (R, G, B)

PIXEL (N+1)

C2ADF

ADC2

C2ADR

ADCLK

ANALOG

INPUTS

CDSCLK2

ADCCLK

OUTPUT

DATA

D<7:0>

R (N2)

G (N2)

B (N2)

R (N1)

G (N1)

B (N1)

R (N)

G (N)

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

ADC1

C2C1

PRA

C1C2

CDSCLK1

PIXEL

(N+2)

Figure 1. 3-Channel CDS Mode Timing

PIXEL N

ANALOG

INPUTS

C2ADR

CDSCLK2

ADCCLK

OUTPUT

DATA

D<7:0>

C2ADF

ADCLK

PIXEL (N4)

PIXEL (N3)

PIXEL (N2)

C1C2

CDSCLK1

ADC1

C2C1

HIGH BYTE

LOW BYTE

HIGH BYTE

LOW BYTE

HIGH BYTE

PIXEL (N+1)

PRB

PIXEL (N+2)

Figure 2. 1-Channel CDS Mode Timing

REV. 0

AD9814

PIXEL N (R, G, B)

PIXEL (N+1)

PRA

C2ADF

ADC2

C2ADR

ADCLK

ANALOG

INPUTS

CDSCLK2

ADCCLK

OUTPUT

DATA

D<7:0>

R (N2)

G (N2)

B (N2)

R (N1)

G (N1)

B (N1)

R (N)

G (N)

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

Figure 3. 3-Channel SHA Mode Timing

PRB

C2ADR

ANALOG

INPUTS

CDSCLK2

ADCCLK

OUTPUT

DATA

D<7:0>

PIXEL N

C2ADF

ADCLK

HIGH BYTE

LOW BYTE

HIGH BYTE

LOW BYTE

PIXEL (N4)

PIXEL (N3)

PIXEL (N2)

Figure 4. 1-Channel SHA Mode Timing

REV. 0

AD9814

FUNCTIONAL DESCRIPTION

The AD9814 can be operated in four different modes: 3-Channel
CDS Mode, 3-Channel SHA Mode, 1-Channel CDS Mode,
and 1-Channel SHA Mode. Each mode is selected by program-
ming the Configuration Register through the serial interface.
For more detail on CDS or SHA mode operation, see the
Circuit Operation section.

3-Channel CDS Mode

In 3-Channel CDS Mode, the AD9814 simultaneously samples
the red, green and blue input voltages from the CCD outputs.
The sampling points for each Correlated Double Sampler (CDS)
are controlled by CDSCLK1 and CDSCLK2 (see Figures 8 and
9). CDSCLK1's falling edge samples the reference level of the
CCD waveform. CDSCLK2's falling edge samples the data
level of the CCD waveform. Each CDS amplifier outputs the
difference between the CCD's reference and data levels. Next,
the output voltage of each CDS amplifier is level-shifted by an
Offset DAC. The voltages are then scaled by the three Program-
mable Gain Amplifiers before being multiplexed through the
14-bit ADC. The ADC sequentially samples the PGA outputs
on the falling edges of ADCCLK.

The offset and gain values for the red, green and blue channels
are programmed using the serial interface. The order in which
the channels are switched through the multiplexer is selected by
programming the MUX register.

Timing for this mode is shown in Figure 1. It is recommended
that the falling edge of CDSCLK2 occur coincident with or
before the rising edge of ADCCLK, although this is not re-
quired to satisfy the minimum timing constraints. The rising
edge of CDSCLK2 should not occur before the previous falling
edge of ADCCLK, as shown by t

ADC2

. The output data latency

is three clock cycles.

3-Channel SHA Mode

In 3-Channel SHA Mode, the AD9814 simultaneously samples
the red, green and blue input voltages. The sampling point is
controlled by CDSCLK2. CDSCLK2's falling edge samples the
input waveforms on each channel. The output voltages from the
three SHAs are modified by the offset DACs and then scaled by
the three PGAs. The outputs of the PGAs are then multiplexed
through the 14-bit ADC. The ADC sequentially samples the
PGA outputs on the falling edges of ADCCLK.

The input signal is sampled with respect to the voltage applied
to the OFFSET pin (see Figure 10). With the OFFSET pin

grounded, a zero volt input corresponds to the ADC's zero-scale
output. The OFFSET pin may also be used as a coarse offset
adjust pin. A voltage applied to this pin will be subtracted from
the voltages applied to the red, green and blue inputs in the first
amplifier stage of the AD9814. The input clamp is disabled in this
mode. For more information, see the Circuit Operation section.

Timing for this mode is shown in Figure 2. CDSCLK1 should
be grounded in this mode. Although not required, it is recom-
mended that the falling edge of CDSCLK2 occur coincident
with or before the rising edge of ADCCLK. The rising edge of
CDSCLK2 should not occur before the previous falling edge of
ADCCLK, as shown by t

ADC2

. The output data latency is three

ADCCLK cycles.

1-Channel CDS Mode

This mode operates in the same way as the 3-Channel CDS
mode. The difference is that the multiplexer remains fixed in
this mode, so only the channel specified in the MUX register is
processed.

Timing for this mode is shown in Figure 3. Although not re-
quired, it is recommended that the falling edge of CDSCLK2
occur coincident with or before the rising edge of ADCCLK.

1-Channel SHA Mode

This mode operates in the same way as the 3-Channel SHA
mode, except that the multiplexer remains stationary. Only the
channel specified in the MUX register is processed.

The input signal is sampled with respect to the voltage applied
to the OFFSET pin. With the OFFSET pin grounded, a zero
volt input corresponds to the ADC's zero scale output. The
OFFSET pin may also be used as a coarse offset adjust pin. A
voltage applied to this pin will be subtracted from the voltages
applied to the red, green and blue inputs in the first amplifier
stage of the AD9814. The input clamp is disabled in this mode.
For more information, see the Circuit Operation section.

Timing for this mode is shown in Figure 4. CDSCLK1 should
be grounded in this mode of operation. Although not required,
it is recommended that the falling edge of CDSCLK2 occur
coincident with or before the rising edge of ADCCLK.

REV. 0

AD9814

INTERNAL REGISTER DESCRIPTIONS

Table I. Internal Register Map

Register

Address

Data Bits

Name

Configuration

Input Rng

VREF

3Ch/1Ch

CDS On

Clamp

Pwr Dn

MUX

RGB/BGR

Red

Green

Blue

Red PGA

MSB

LSB

Green PGA

MSB

LSB

Blue PGA

MSB

LSB

Red Offset

MSB

LSB

Green Offset

MSB

LSB

Blue Offset

MSB

LSB

Configuration Register

The Configuration Register controls the AD9814's operating mode and bias levels. Bits D8, D1 and D0 should always be set low. Bit
D7 sets the full-scale voltage range of the AD9814's A/D converter to either 4 V (high) or 2 V (low). Bit D6 controls the internal
voltage reference. If the AD9814's internal voltage reference is used, this bit is set high. Setting Bit D6 low will disable the internal
voltage reference, allowing an external voltage reference to be used. Bit D5 will configure the AD9814 for either the 3-Channel (high)
or 1-Channel (low) mode of operation. Setting Bit D4 high will enable the CDS mode of operation, and setting this bit low will en-
able the SHA mode of operation. Bit D3 sets the dc bias level of the AD9814's input clamp. This bit should always be set high for
the 4 V clamp bias, unless a CCD with a reset feedthrough transient exceeding 2 V is used. If the 3 V clamp bias level is used, the
peak-to-peak input signal range to the AD9814 is reduced to 3 V maximum. Bit D2 controls the power-down mode. Setting Bit D2
high will place the AD9814 into a very low power "sleep" mode. All register contents are retained while the AD9814 is in the pow-
ered-down state.

Table II. Configuration Register Settings

Set

Input Range

Internal VREF

# of Channels

CDS Operation

Input Clamp Bias

Power-Down

Set

1 = 4 V*

1 = Enabled*

1 = 3-Ch Mode*

1 = CDS Mode*

1 = 4 V*

1 = On

0 = 2 V

0 = Disabled

0 = 1-Ch Mode

0 = SHA Mode

0 = 3 V

0 = Off (Normal)* 0

*Power-on default value.

MUX Register

The MUX Register controls the sampling channel order in the AD9814. Bits D8, D3, D2, D1, and D0 should always be set low. Bit
D7 is used when operating in 3-Channel Mode. Setting Bit D7 high will sequence the MUX to sample the red channel first, then the
green channel and then the blue channel. When in this mode, the CDSCLK2 pulse always resets the MUX to sample the red channel
first (see Timing Figure 1). When Bit D7 is set low, the channel order is reversed to blue first, green second and red third. The
CDSCLK2 pulse will always reset the MUX to sample the blue channel first. Bits D6, D5, and D4 are used when operating in
1-Channel Mode. Bit D6 is set high to sample the red channel. Bit D5 is set high to sample the green channel. Bit D4 is set high to
sample the blue channel. The MUX will remain stationary during 1-Channel Mode.

Table III. MUX Register Settings

Set

3-Channel Select

1-Channel Select

Set

1 = R-G-B*

1 = RED*

1 = GREEN

1 = BLUE

0 = B-G-R

0 = Off

0 = Off*

*Power-on default value.

REV. 0

AD9814

PGA Gain Registers

There are three PGA registers for individually programming the gain in the red, green and blue channels. Bits D8, D7 and D6 in
each register must be set low, and bits D5 through D0 control the gain range in 64 increments. See Figure 13 for a graph of the PGA
Gain versus PGA register code. The coding for the PGA registers is straight binary, with an all "zeros" word corresponding to the
minimum gain setting (1x) and an all "ones" word corresponding to the maximum gain setting (5.8x).

Table IV. PGA Gain Register Settings

Gain (V/V)

Gain (dB)

Set to 0

MSB

LSB

1.0

0.0

1.013

0.12

5.4

14.6

5.8

15.25

*Power-on default value.

Offset Registers

There are three PGA registers for individually programming the offset in the red, green and blue channels. Bits D8 through D0 con-
trol the offset range from 300 mV to +300 mV in 512 increments. The coding for the offset registers is sign magnitude, with D8 as
the sign bit. Table V shows the offset range as a function of the Bits D8 through D0.

Table V. Offset Register Settings

Offset (mV)

MSB

LSB

+1.2

+300

1.2

300

*Power-on default value.

REV. 0

AD9814

CIRCUIT OPERATION

Analog Inputs--CDS Mode

Figure 8 shows the analog input configuration for the CDS
mode of operation. Figure 9 shows the internal timing for the
sampling switches. The CCD reference level is sampled when
CDSCLK1 transitions from high to low, opening S1. The CCD
data level is sampled when CDSCLK2 transitions from high to
low, opening S2. S3 is then closed, generating a differential
output voltage representing the difference between the two sampled
levels.

The input clamp is controlled by CDSCLK1. When CDSCLK1
is high, S4 closes and the internal bias voltage is connected to
the analog input. The bias voltage charges the external 0.1

input capacitor, level-shifting the CCD signal into the AD9814's
input common-mode range. The time constant of the input
clamp is determined by the internal 5 k

resistance and the

external 0.1

F input capacitance.

AD9814

4pF

CML

AVDD

1.7k

VINR

OFFSET

0.1 F

CCD SIGNAL

0.1 F

1 F

2.2k

6.9k

INPUT CLAMP LEVEL
IS SELECTED IN THE
CONFIGURATION
REGISTER

Figure 8. CDS-Mode Input Configuration (All Three Chan-
nels Are Identical)

CDSCLK1

CDSCLK2

(INTERNAL)

S1, S4 CLOSED

S2 CLOSED

S3 CLOSED

S3 OPEN

S2 OPEN

S1, S4 OPEN

Figure 9. CDS-Mode Internal Switch Timing

External Input Coupling Capacitors

The recommended value for the input coupling capacitors is
0.1

F. While it is possible to use a smaller capacitor, this larger

value is chosen for several reasons:

1. Signal Attenuation. The input coupling capacitor creates a

capacitive divider with a CMOS integrated circuit's input
capacitance, attenuating the CCD signal level. C

should be

large relative to the IC's 10 pF input capacitance in order to
minimize this effect.

2. Linearity. Some of the input capacitance of a CMOS IC is

junction capacitance, which varies nonlinearly with applied
voltage. If the input coupling capacitor is too small, then the
attenuation of the CCD signal will vary nonlinearly with signal
level. This will degrade the system linearity performance.

3. Sampling Errors. The internal 4 pF sample capacitors have

a "memory" of the previously sampled pixel. There is a
charge redistribution error between C

and the internal

sample capacitors

for larger pixel-to-pixel voltage swings. As

the value of C

is reduced, the resulting error in the sampled

voltage will increase. With a C

value of 0.1

F, the charge

redistribution error will be less than 1 LSB for a full-scale
pixel-to-pixel voltage swing.

Analog Inputs--SHA Mode

Figure 10 shows the analog input configuration for the SHA
mode of operation. Figure 11 shows the internal timing for the
sampling switches. The input signal is sampled when CDSCLK2
transitions from high to low, opening S1. The voltage on the
OFFSET pin is also sampled on the falling edge of CDSCLK2,
when S2 opens. S3 is then closed, generating a differential out-
put voltage representing the difference between the sampled
input voltage and the OFFSET voltage. The input clamp is
disabled during SHA mode operation.

AD9814

4pF

CML

VINR

INPUT SIGNAL

4pF

CML

OFFSET

RED

VING

GREEN

VINB

BLUE

OPTIONAL DC OFFSET

(OR CONNECT TO GND)

Figure 10. SHA-Mode Input Configuration (All Three
Channels Are Identical)

CDSCLK2

(INTERNAL)

S1, S2 CLOSED

S3 CLOSED

S3 OPEN

S1, S2 OPEN

Figure 11. SHA-Mode Internal Switch Timing

REV. 0

AD9814

Figure 12 shows how the OFFSET pin may be used in a CIS
application for coarse offset adjustment. Many CIS signals have
dc offsets ranging from several hundred millivolts to more than
1 V. By connecting the appropriate dc voltage to the OFFSET
pin, the CIS signal will be restored to "zero." After the large dc
offset is removed, the signal can be scaled using the PGA to
maximize the ADC's dynamic range.

AD9814

OFFSET

RED-OFFSET

GREEN-OFFSET

BLUE-OFFSET

VINR

VING

VINB

RED

GREEN

BLUE

0.1 F

AVDD

VREF FROM

CIS MODULE

DC OFFSET

SHA

Figure 12. SHA-Mode Used with External DC Offset

Programmable Gain Amplifiers

The AD9814 uses one Programmable Gain Amplifier (PGA) for
each channel. Each PGA has a gain range from 1x (0 dB) to
5.8x (15.5 dB), adjustable in 64 steps. Figure 6 shows the PGA
gain as a function of the PGA register code. Although the gain
curve is approximately "linear in dB", the gain in V/V varies
nonlinearly with register code, following the equation:

Gain

5 8

4 8

where G is the decimal value of the gain register contents, and
varies from 0 to 63.

PGA REGISTER VALUE Decimal

GAIN dB ( )

12 16 20 24 28 32 36 40 44 48 52 56 60 63

6.0

5.0

4.0

3.0

2.0

1.0

GAIN V/V ( )

Figure 13. PGA Gain Transfer Function

2000

4000

6000

8000

10000 12000 14000

16383

1.0

0.8

0.6

0.4

0.2

0.0

0.2

0.4

0.6

0.8

1.0

DNL GRAPH

MAX DNL +0.48
MIN DNL 0.39

5.0

4.0

3.0

2.0

1.0

0.0

1.0

2.0

3.0

4.0

5.0

2000

4000

6000

8000

10000 12000 14000

16383

INL GRAPH

MAX INL +1.22
MIN INL 4.06

LSB

Figure 14. Typical Linearity Performance

REV. 0

AD9814

CDSCLK1

AVDD

CDSCLK2

ADCCLK

OEB

DRVDD

DRVSS

D7 (MSB)

D0 (LSB)

AVSS

VINR

OFFSET

VING

CML

VINB

CAPT

CAPB

AVSS

AVDD

SLOAD

SCLK

SDATA

CLOCK INPUTS

DATA OUTPUTS

0.1 F

SERIAL INTERFACE

0.1 F

+5V/3V

+5V

0.1 F

RED INPUT

GREEN INPUT

BLUE INPUT

0.1 F

1.0 F

10 F

0.1 F

+5V

0.1 F

Figure 15. Recommended Circuit Configuration, 3-Channel CDS Mode

AD9814

CDSCLK1

AVDD

CDSCLK2

ADCCLK

OEB

DRVDD

DRVSS

D7 (MSB)

D0 (LSB)

AVSS

VINR

OFFSET

VING

CML

VINB

CAPT

CAPB

AVSS

AVDD

SLOAD

SCLK

SDATA

CLOCK INPUTS

DATA OUTPUTS

0.1 F

SERIAL INTERFACE

0.1 F

+5V/3V

+5V

0.1 F

RED INPUT

GREEN INPUT

BLUE INPUT

0.1 F

10 F

0.1 F

+5V

0.1 F

Figure 16. Recommended Circuit Configuration, 3-Channel SHA Mode
(Analog Inputs Sampled with Respect to Ground)

APPLICATIONS INFORMATION
Circuit and Layout Recommendations

The recommended circuit configuration for 3-Channel CDS
mode operation is shown in Figure 15. The recommended input
coupling capacitor value is 0.1

F (see Circuit Operation section

for more details). A single ground plane is recommended for the
AD9814. A separate power supply may be used for DRVDD,
the digital driver supply, but this supply pin should still be
decoupled to the same ground plane as the rest of the AD9814.
The loading of the digital outputs should be minimized, either
by using short traces to the digital ASIC, or by using external
digital buffers. To minimize the effect of digital transients during
major output code transitions, the falling edge of CDSCLK2

should occur coincident with or before the rising edge of
ADCCLK (see Figures 1 through 4 for timing). All 0.1

decoupling capacitors should be located as close as possible to
the AD9814 pins. When operating in single channel mode, the
unused analog inputs should be grounded.

Figure 16 shows the recommended circuit configuration for 3-
Channel SHA mode. All of the above considerations also apply
for this configuration, except that the analog input signals are
directly connected to the AD9814 without the use of coupling
capacitors. The analog input signals must already be dc-biased
between 0 V and 4 V (see the Circuit Operation section for
more details).

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