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Energy Metering IC with On-Chip Fault and
Missing Neutral Detection
ADE7761A
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
FEATURES
High accuracy, active energy measurement IC supports
IEC 62053-21
Less than 0.1% error over a dynamic range of 500 to 1
Supplies active power on the frequency outputs, F1 and F2
High frequency output CF is intended for calibration and
supplies instantaneous active power
Continuous monitoring of the phase and neutral current
allows fault detection in 2-wire distribution systems
Current channels input level best suited for shunt and
current transformer sensors
Uses the larger of the two currents (phase or neutral) to
bill--even during a fault condition
Continuous monitoring of the voltage and current inputs
allows missing neutral detection
Uses one current input (phase or neutral) to bill when
missing neutral is detected
Two logic outputs (FAULT and REVP) can be used to indicate
a potential miswiring, fault, or missing neutral condition
Direct drive for electromechanical counters and 2-phase
stepper motors (F1 and F2)
Proprietary ADCs and DSP provide high accuracy over large
variations in environmental conditions and time
Reference 2.5 V 8% (drift 30 ppm/C typical) with external
overdrive capability
Single 5 V supply, low power
GENERAL DESCRIPTION
The ADE7761A is a high accuracy, fault-tolerant, electrical
energy measurement IC intended for use with 2-wire distribution
systems. The part specifications surpass the accuracy requirements
as quoted in the IEC 62053-21 standard. The only analog circuitry
used on the ADE7761A is in the ADCs and reference circuit.
All other signal processing (such as multiplication and filtering)
is carried out in the digital domain. This approach provides
superior stability and accuracy over extremes in environmental
conditions and over time. The ADE7761A incorporates a fault
detection scheme similar to the ADE7751 by continuously
monitoring both phase and neutral currents. A fault is indicated
when the currents differ by more than 6.25%.
The ADE7761A incorporates a missing neutral detection
scheme by continuously monitoring the input voltage. When a
missing neutral condition is detected--no voltage input--the
ADE7761A continues billing based on the active current signal
(see the Missing Neutral Mode section). The missing neutral
condition is indicated when the FAULT pin goes high. The
ADE7761A supplies average active power information on the
low frequency outputs, F1 and F2. The CF logic output gives
instantaneous active power information.
The ADE7761A includes a power-supply monitoring circuit on
the V
DD
supply pin. Internal phase matching circuitry ensures
that the voltage and current channels are matched. An internal
no-load threshold ensures that the ADE7761A does not exhibit
any creep when there is no load.
FUNCTIONAL BLOCK DIAGRAM
MISCAL
ADC
6
5
V
2P
V
2N
ADC
ADC
4
3
7
V
1B
ADC
2
V
1A
AGND
FAULT
V
DD
V
1N
2.5V
REFERENCE
INTERNAL
OSCILLATOR
MISSING NEUTRAL
GAIN ADJUST
MISSING NEUTRAL
DETECTION
9
14
17
10
11
12
B>A
A<>B
A>B
ZERO CROSSING
DETECTION
ADE7761A
SIGNAL PROCESSING
BLOCK
15
1
8
POWER
SUPPLY MONITOR
DIGITAL-TO-FREQUENCY CONVERTER
16
18
19
20
F1
F2
CF
REVP
S0
S1
SCF
DGND
RCLKIN
REF
IN/OUT
HPF
LPF
3k
0504
0-
0
-
00
1
PGA
13
Figure 1.
ADE7761A
Rev. 0 | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
Performance
Issues That May Affect Billing Accuracy........... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Test Circuit ...................................................................................... 10
Operation......................................................................................... 11
Power Supply Monitor ............................................................... 11
Analog Inputs ............................................................................. 11
Internal Oscillator ...................................................................... 12
Analog-to-Digital Conversion.................................................. 13
Active Power Calculation .......................................................... 14
Digital-to-Frequency Conversion ............................................ 16
Transfer Function....................................................................... 16
Fault Detection ........................................................................... 17
Missing Neutral Mode ............................................................... 18
Applications..................................................................................... 21
Interfacing to a Microcontroller for Energy Measurement .. 21
Selecting a Frequency for an Energy Meter Application ...... 21
Negative Power Information..................................................... 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
7/06--Revision 0: Initial Version
ADE7761A
Rev. 0 | Page 3 of 24
SPECIFICATIONS
V
DD
= 5 V 5%, AGND = DGND = 0 V, on-chip reference, on-chip oscillator, T
MIN
to T
MAX
= -40C to +85C.
Table 1.
Parameter Value
Unit
Test
Conditions/Comments
ACCURACY
1
Measurement Error
2
0.1
% of reading, typ
Over a dynamic range of 500 to 1
Phase Error Between Channels
PF = 0.8 Capacitive
0.05
Degrees, max
Phase lead 37
PF = 0.5 Inductive
0.05
Degrees, max
Phase lag 60
AC Power Supply Rejection
2
Output Frequency Variation
0.01
%, typ
V
1A
= V
1B
= V
2P
= 100 mV rms
DC Power Supply Rejection
2
Output Frequency Variation
0.01
%, typ
V
1A
= V
1B
= V
2P
= 100 mV rms
FAULT DETECTION
2, 3
See
the
Fault Detection section
Fault Detection Threshold
Inactive Input <> Active Input
6.25
%, typ
V
1A
or V
1B
active
Input Swap Threshold
Inactive Input <> Active Input
6.25
% of larger, typ
V
1A
or V
1B
active
Accuracy Fault Mode Operation
V
1A
Active, V
1B
= AGND
0.1
% of reading, typ
Over a dynamic range of 500 to 1
V
1B
Active, V
1A
= AGND
0.1
% of reading, typ
Over a dynamic range of 500 to 1
Fault Detection Delay
3
Seconds, typ
Swap Delay
3
Seconds, typ
MISSING NEUTRAL MODE
2, 4
See
the
Missing Neutral Detection section
Missing Neutral Detection Threshold
V
2P
- V
2N
59.4
mV peak, min
Accuracy Missing Neutral Mode
V
1A
Active, V
1B
= V
2P
= AGND
0.1
% of reading, typ
Over a dynamic range of 500 to 1
V
1B
Active, V
1A
= V
2P
= AGND
0.1
% of reading, typ
Over a dynamic range of 500 to 1
Missing Neutral Detection Delay
3
Seconds, typ
ANALOG INPUTS
V
1A
- V
1N
, V
1B
- V
1N
, V
2P
- V
2N
Maximum Signal Levels
660
mV peak, max
Differential input
660
mV peak, max
Differential input MISCAL - V
2N
Input Impedance (DC)
400
k, min
Bandwidth (-3 dB)
7
kHz, typ
ADC Offset Error
2
15
mV, typ
Uncalibrated error, see the Terminology section for details
Gain Error
4
%, typ
External 2.5 V reference
Gain Error Match
2
3
%, typ
External 2.5 V reference
REFERENCE INPUT
REF
IN/OUT
Input Voltage Range
2.7
V, max
2.5 V + 8%
2.3
V, min
2.5 V - 8%
Input Impedance
3
k, min
Input Capacitance
10
pF, max
ON-CHIP REFERENCE
Reference Error
200
mV, max
Temperature Coefficient
30
ppm/C, typ
Current Source
20
A, min
ON-CHIP OSCILLATOR
Oscillator Frequency
450
kHz
Oscillator Frequency Tolerance
12
% of reading, typ
Temperature Coefficient
30
ppm/C, typ
ADE7761A
Rev. 0 | Page 4 of 24
Parameter Value
Unit
Test
Conditions/Comments
LOGIC INPUTS
5
PGA, SCF, S1, and S0
Input High Voltage, V
INH
2.4 V,
min
V
DD
= 5 V 5%
Input Low Voltage, V
INL
0.8 V,
max
V
DD
= 5 V 5%
Input Current, I
IN
3
A, max
Typical 10 nA, V
IN
= 0 V to V
DD
Input Capacitance, C
IN
10 pF,
max
LOGIC OUTPUTS
5
CF, REVP, and FAULT
Output High Voltage, V
OH
4 V,
min
V
DD
= 5 V 5%
Output Low Voltage, V
OH
1 V,
max
V
DD
= 5 V 5%
F1 and F2
Output High Voltage, V
OH
4 V,
min
V
DD
= 5 V 5%, I
SOURCE
= 10 mA
Output Low Voltage, V
OH
1 V,
max
V
DD
= 5 V 5%, I
SINK
= 10 mA
POWER SUPPLY
For specified performance
V
DD
4.75
V, min
5 V - 5%
5.25
V, max
5 V + 5%
V
DD
3 mA,
max
1
See plots in the Typical Performance Characteristics section.
2
See the Terminology section for explanation of specifications.
3
See the Fault Detection section for explanation of fault detection functionality.
4
See the Missing Neutral Detection section for explanation of missing neutral detection functionality.
5
Sample tested during initial release and after any redesign or process change that might affect this parameter.
TIMING CHARACTERISTICS
V
DD
= 5 V 5%, AGND = DGND = 0 V, on-chip reference, on-chip oscillator, T
MIN
to T
MAX
= -40C to +85C. Sample tested during
initial release and after any redesign or process change that might affect this parameter. See Figure 2.
Table 2.
Parameter
Value
Unit
Test Conditions/Comments
t
1
1
120
ms
F1 and F2 Pulse Width (Logic High).
t
2
See Table 7
s
Output Pulse Period. See the Transfer Function section.
t
3
1/2 t
2
s
Time Between F1 Falling Edge and F2 Falling Edge.
t
4
1
90
ms
CF Pulse Width (Logic High).
t
5
See Table 8
s
CF Pulse Period. See the Transfer Function section.
t
6
CLKIN/4
s
Minimum Time Between F1 and F2 Pulse.
1
The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Transfer Function section.
t
1
t
6
t
3
t
4
t
2
t
5
F1
F2
CF
0
504
0-
0
02
Figure 2. Timing Diagram for Frequency Outputs
ADE7761A
Rev. 0 | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
T
A
= 25C, unless otherwise noted.
Table 3.
Parameter Rating
V
DD
to AGND
-0.3 V to +7 V
Analog Input Voltage to AGND
V
1A
, V
1B
, V
1N
, V
2N
, V
2P
, MISCAL
-6 V to +6 V
Reference Input Voltage to AGND
-0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to DGND
-0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to DGND
-0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial
-40C to +85C
Storage Temperature Range
-65C to +150C
Junction Temperature
150C
20-Lead SSOP, Power Dissipation
450 mW
JA
Thermal Impedance
112C/W
Lead Temperature, Soldering
Vapor Phase (60 sec)
215C
Infrared (15 sec)
220C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PERFORMANCE ISSUES THAT MAY AFFECT
BILLING ACCURACY
The ADE7761A provides pulse outputs--CF, F1, and F2--
intended to be used for the billing of active energy. Pulses
are generated at these outputs in two different situations.
Case 1
: When the analog input V
2P
V
2N
complies with the
conditions described in Figure 34, CF, F1, and F2 frequencies
are proportional to active power and can be used to bill
active energy.
Case 2
: When the analog input V
2P
V
2N
does not comply with
the conditions described in Figure 34, the ADE7761A does not
measure active energy but a quantity proportional to kAh. This
quantity is used to generate pulses on the same CF, F1, and F2.
This situation is indicated when the FAULT pin is high.
Analog Devices, Inc. cautions users of the ADE7761A about the
following:
Billing active energy in Case 1 is consistent with the
understanding of the quantity represented by pulses on CF,
F1, and F2 outputs (watt-hour).
Billing active energy while the ADE7761A is in Case 2 must
be decided knowing that the entity measured by the
ADE7761A in this case is ampere-hour and not watt-hour.
Users should be aware of this limitation and decide if the
ADE7761A is appropriate for their application.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADE7761A
Rev. 0 | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REF
IN/OUT
S0
SCF
S1
V
DD
F1
V
1A
F2
V
1B
CF
V
1N
DGND
V
2N
REVP
V
2P
FAULT
MISCAL
RCLKIN
AGND
PGA
1
2
3
4
20
19
18
17
5
6
7
16
15
14
8
13
9
12
10
11
ADE7761A
TOP VIEW
(Not to Scale)
05
04
0-
00
3
Figure 3. Pin Configuration (SSOP)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 V
DD
Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7761A. The supply voltage
should be maintained at 5 V 5% for specified operation. This pin should be decoupled with a 10 F capacitor
in parallel with a ceramic 100 nF capacitor.
2, 3
V
1A
, V
1B
Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs with maximum
differential input signal levels of 660 mV with respect to V
1N
for specified operation. The maximum signal level
at these pins is 1 V with respect to AGND. Both inputs have internal ESD protection circuitry, and an overvoltage
of 6 V can also be sustained on these inputs without risk of permanent damage.
4 V
1N
Negative Input for Differential Voltage Inputs, V
1A
and V
1B
. The maximum signal level at this pin is 1 V with
respect to AGND. The input has internal ESD protection circuitry, and an overvoltage of 6 V can also be sustained
on this input without risk of permanent damage. The input should be directly connected to the burden resistor
and held at a fixed potential, that is, AGND. See the Analog Inputs section.
5 V
2N
Negative Input for Differential Voltage Inputs, V
2P
and MISCAL. The maximum signal level at this pin is 1 V with
respect to AGND. The input has internal ESD protection circuitry, and an overvoltage of 6 V can also be sustained
on this input without risk of permanent damage. The input should be held at a fixed potential, that is, AGND. See
the Analog Inputs section.
6 V
2P
Analog Input for Channel 2 (Voltage Channel). This input is a fully differential voltage input with maximum
differential input signal levels of 660 mV with respect to V
2N
for specified operation. The maximum signal level at
this pin is 1 V with respect to AGND. This input has internal ESD protection circuitry, and an overvoltage of 6 V
can also be sustained on this input without risk of permanent damage.
7 MISCAL
Analog Input for Missing Neutral Calibration. This pin can be used to calibrate the CF-F1-F2 frequencies in the
missing neutral condition. This input is a fully differential voltage input with maximum differential input signal
levels of 660 mV with respect to V
2N
for specified operation. The maximum signal level at this pin is 1 V with
respect to AGND. This input has internal ESD protection circuitry, and an overvoltage of 6 V can also be
sustained on this input without risk of permanent damage.
8 AGND This pin provides the ground reference for the analog circuitry in the ADE7761A, that is, ADCs and reference. This
pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground reference for all
analog circuitry, such as antialiasing filters, and current and voltage transducers. For good noise suppression, the
analog ground plane should be connected only to the digital ground plane at the DGND pin.
9 REF
IN/OUT
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
2.5 V 8% and a typical temperature coefficient of 30 ppm/C. An external reference source can also be
connected at this pin. In either case, this pin should be decoupled to AGND with a 1 F ceramic capacitor and
100 nF ceramic capacitor.
10 SCF
Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF.
Table 7 shows how the calibration frequencies are selected.
11, 12
S1, S0
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion.
This offers the designer greater flexibility when designing the energy meter. See the Selecting a Frequency for an
Energy Meter Application section.
13
PGA
This logic input is used to select the gain for the analog inputs, V
1A
and V
1B
. The possible gains are 1 and 16.
14 RCLKIN To enable the internal oscillator as a clock source on the chip, a precise low temperature drift resistor at
nominal value of 6.2 k must be connected from this pin to DGND.
ADE7761A
Rev. 0 | Page 7 of 24
Pin No.
Mnemonic
Description
15 FAULT This logic output goes active high when a fault or missing neutral condition occurs. A fault is defined as a
condition under which the signals on V
1A
and V
1B
differ by more than 6.25%. A missing neutral condition is
defined when the chip is powered up with no voltage at the input. The logic output is reset to zero when a fault
or missing neutral condition is no longer detected. See the Fault Detection section and the Missing Neutral Mode
section.
16 REVP This logic output goes logic high when negative power is detected, that is, when the phase angle between the
voltage and current signals is greater than 90. This output is not latched and is reset when positive power is once
again detected. The output goes high or low at the same time as a pulse is issued on CF.
17 DGND This pin provides the ground reference for the digital circuitry in the ADE7761A, that is, multiplier, filters, and
digital-to-frequency converters. This pin should be tied to the digital ground plane of the PCB. The digital ground
plane is the ground reference for all digital circuitry, such as counters (mechanical and digital), MCUs, and
indicator LEDs. For good noise suppression, the analog ground plane should be connected only to the digital
ground plane at the DGND pin.
18 CF
Calibration Frequency Logic Output. The CF logic output, active high, gives instantaneous active power
information. This output is used for operational and calibration purposes. See the Digital-to-Frequency Conversion
section.
19, 20
F2, F1
Low Frequency Logic Outputs. F1 and F2 supply average active power information. The logic outputs can be
used to directly drive electromechanical counters and 2-phase stepper motors.
ADE7761A
Rev. 0 | Page 8 of 24
TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the
ADE7761A is defined by
-
=
%
100
Energy
True
Energy
True
ADE7761A
by
registered
Energy
Error
Percentage
Phase Error Between Channels
The high-pass filter (HPF) in the current channel has a phase
lead response. To offset this phase response and equalize the
phase response among channels, a phase correction network is
also placed in the current channel. The phase correction network
ensures a phase match between the current channels and
voltage channels to within 0.1 over a range of 45 Hz to
65 Hz and 0.2 over a range of 40 Hz to 1 kHz.
Power Supply Rejection (PSR)
PSR quantifies the ADE7761A measurement error as a
percentage of reading when the power supplies are varied. For
the ac PSR measurement, a reading at nominal supplies (5 V) is
taken. A second reading is obtained with the same input signal
levels when an ac (175 mV rms/100 Hz) signal is introduced
onto the supplies. Any error introduced by this ac signal is
expressed as a percentage of reading (see the Measurement
Error definition).
For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. A second reading is obtained with the same input
signal levels when the power supplies are varied 5%. Any error
introduced is again expressed as a percentage of reading.
ADC Offset Error
The dc offset associated with the analog inputs to the ADCs.
With the analog inputs connected to AGND, the ADCs still see
a dc analog input signal. The magnitude of the offset depends on
the input gain and range selection (see the Typical Performance
Characteristics section). However, when HPFs are switched on,
the offset is removed from the current channels and the power
calculation is not affected by this offset.
Gain Error
The gain error in the ADE7761A ADCs is defined as the
difference between the measured output frequency (minus the
offset) and the ideal output frequency. It is measured with a
gain of 1 in Channel V
1A
. The difference is expressed as a
percentage of the ideal frequency, which is obtained from the
transfer function (see the Transfer Function section).
Gain Error Match
The gain error match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1 or 16. It is
expressed as a percentage of the output ADC code obtained
under a gain of 1.
ADE7761A
Rev. 0 | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
050
40
-
00
4
CURRENT (% of Full Scale)
100.0
0.1
1.0
10.0
% E
R
RO
R
1.0
1.0
0.8
0.6
0.4
0.2
0.2
0.4
0
0.6
0.8
PF = 1
ON-CHIP REFERENCE
40C
+25C
+85C
Figure 4. Active Power Error as a Percentage of Reading
with Gain = 1 and Internal Reference
050
40
-
00
5
CURRENT (% of Full Scale)
100
0.1
1.0
10
% E
R
RO
R
1.0
1.5
1.0
0.5
0
0.5
PF = DIFFERENT VALUES
ON-CHIP REFERENCE
40C; PF = 0.5
+25C; PF = 1
+25C; PF = 0.5
+85C; PF = 0.5
Figure 5. Active Power Error as a Percentage of Reading
over Power Factor with Gain = 1 and Internal Reference
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.10
1
10
100
CURRENT (% Full Scale)
%
E
RRO
R
05
04
0-
0
34
+25C
+85C
40C
0.6
0.8
1.0
PF = 1. GAIN = 16
ON-CHIP REFERENCE
Figure 6. Active Power Error as a Percentage of Reading
with Gain = 16 and Internal Reference
0.2
0
0.2
0.4
0.10
1
10
100
CURRENT (% Full Scale)
%
E
RRO
R
0.6
GAIN = 16
ON-CHIP REFERENCE
050
40
-
0
35
PF = 0.5
PF = +1
PF = +0.5
1.0
0.8
0.8
0.6
0.4
1.0
Figure 7. Active Power Error as a Percentage of Reading
over Power Factor with Gain = 16 and Internal Reference
050
40
-
00
6
CURRENT (% of Full Scale)
100.0
0.1
1.0
10.0
% E
R
RO
R
1.0
1.0
0.8
0.6
0.4
0.2
0.2
0.4
0
0.6
0.8
PF = 1
ON-CHIP REFERENCE
5.25V
5.00V
4.75V
Figure 8. Active Power Error as a Percentage of Reading
over Power Supply with Gain = 1 and Internal Reference
050
40
-
00
7
CURRENT (% of Full Scale)
100.0
0.1
1.0
10.0
% E
R
RO
R
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
ON-CHIP REFERENCE
+85C
+25C
40C
Figure 9. Ampere Hour Error as a Percentage of Reading
in Missing Neutral Mode with Gain = 1 and Internal Reference
ADE7761A
Rev. 0 | Page 10 of 24
TEST CIRCUIT
V
DD
REF
IN/OUT
100nF
10F
V
DD
AGND DGND
PGA
CF
FAULT
RCLKIN
S1
SCF
PS2501-1
ADE7761A
TO FREQ.
COUNTER
V
1A
V
1B
V
1N
100nF
10F
V
2N
I
33nF
1k
S0
6.2k
10k
40A TO 80mA
RB = 18
1
18
15
14
12
11
10
9
17
13
8
5
4
3
2
+
2k
2k
1
2
V
2P
MISCAL
33nF
1k
1M
220V
6
7
100k
560k
33nF
33nF
1k
RB
33nF
1k
RB
33nF
1k
+
3
4
05
04
0
-
00
8
Figure 10. Test Circuit for Performance Curves
ADE7761A
Rev. 0 | Page 11 of 24
OPERATION
POWER SUPPLY MONITOR
The ADE7761A continuously monitors the power supply (V
DD
)
with its on-chip, power supply monitor. If the supply is less than
4 V 5%, the ADE7761A goes into an inactive state, that is, no
energy is accumulated and the CF, F1, and F2 outputs are
disabled. This is useful to ensure correct device operation at
power-up and during power-down. The power supply monitor
has built-in hysteresis and filtering, which provides a high
degree of immunity to false triggering due to noisy supplies.
The power supply and decoupling for the part should be such
that the ripple at V
DD
does not exceed 5 V 5% as specified for
normal operation.
ADE7761A
REVP - FAULT - CF -
F1 - F2 OUTPUTS
INACTIVE
ACTIVE
TIME
INACTIVE
V
DD
5V
4V
0V
05
04
0-
00
9
Figure 11. On-Chip, Power Supply Monitoring
ANALOG INPUTS
Channel V1 (Current Channel)
The voltage outputs from the current transducers are connected
to the ADE7761A at Channel V1. It has two voltage inputs, V
1A
and V
1B
. These inputs are fully differential with respect to V
1N
.
However, at any one time, only one is selected to perform the
power calculation (see the Fault Detection section).
The maximum peak differential signal on V
1A
- V
1N
and V
1B
- V
1N
is 660 mV. However, Channel 1 has a programmable gain
amplifier (PGA) with user-selectable gains of 1 or 16 (see
Table 5). This gain facilitates easy transducer interfacing.
Table 5. Channel 1 Dynamic Range
PGA
Gain
Maximum Differential Signal (mV)
0 1
660
1 16
41
Figure 12 shows the maximum signal levels on V
1A
, V
1B
, and
V
1N
. The maximum differential voltage is 660 mV divided by
the gain selection. The differential voltage signal on the inputs
must be referenced to a common mode (usually AGND).
V
CM
DIFFERENTIAL INPUT B
660mV MAX PEAK
V
1B
V
1N
V
1A
V1
V1
V
CM
COMMON MODE
100mV MAX
DIFFERENTIAL INPUT A
660mV MAX PEAK
AGND
V
1A
, V
1B
05
04
0-
0
10
+660mV
GAIN
660mV
GAIN
+ V
CM
+ V
CM
Figure 12. Maximum Signal Levels, Channel 1
Channel V2 (Voltage Channel)
The output of the line voltage transducer is connected to the
ADE7761A at this analog input. Channel V2 is a single-ended,
voltage input. The maximum peak differential signal on Channel 2
is 660 mV with respect to V
2N
. Figure 13 shows the maximum
signal levels that can be connected to Channel 2.
05
04
0-
0
1
1
V
CM
+660mV + V
CM
660mV + V
CM
COMMON MODE
100mV MAX
V
2N
V
2P
V
CM
V2
DIFFERENTIAL INPUT
660mV MAX PEAK
V2
Figure 13. Maximum Signal Levels, Channel 2
The differential voltage V
2P
- V
2N
must be referenced to a
common mode (usually AGND). The analog inputs of the
ADE7761A can be driven with common-mode voltages of up
to 100 mV with respect to AGND. However, the best results
are achieved using a common mode equal to AGND.
MISCAL Input
The input for the power calibration in missing neutral mode
is connected to the ADE7761A at this analog input. MISCAL is
a single-ended, voltage input. It is recommended to use a dc
signal derived from the voltage reference to drive this pin. The
maximum peak differential signal on MISCAL is 660 mV with
respect to V
2N
. Figure 14 shows the maximum signal levels that
can be connected to the MISCAL pin.
0
50
40-
012
V
CM
+660mV + V
CM
COMMON MODE
100mV MAX
V
2N
MISCAL
V
CM
MISCAL
DIFFERENTIAL INPUT
660mV MAX PEAK
MISCAL
AGND
Figure 14. Maximum Signal Levels, MISCAL
ADE7761A
Rev. 0 | Page 12 of 24
The differential voltage MISCAL - V
2N
must be referenced
to a common mode (usually AGND). The analog inputs of the
ADE7761A can be driven with common-mode voltages of up
to 100 mV with respect to AGND. However, best results are
achieved using a common mode equal to AGND.
Typical Connection Diagrams
Figure 15 shows a typical connection diagram for Channel V1.
The analog inputs are used to monitor both the phase and
neutral currents. Because of the large potential difference
between the phase and neutral, two current transformers (CTs)
must be used to provide the isolation. Note that both CTs are
referenced to analog ground (AGND); therefore, the common-
mode voltage is 0 V. The CT turns ratio and burden resistor
(RB) are selected to give a peak differential voltage of
660 mV/gain.
AGND
V
1B
V
1N
V
1A
R
F
R
F
C
F
C
F
CT
CT
RB
RB
IN
IP
P
HAS
E
NE
UT
RA
L
05
04
0-
0
1
3
660mV
GAIN
660mV
GAIN
Figure 15. Typical Connection for Channel 1
Figure 16 shows two typical connections for Channel V2.
The first option uses a potential transformer (PT) to provide
complete isolation from the main voltage. In the second option,
the ADE7761A is biased around the neutral wire, and a resistor
divider is used to provide a voltage signal that is proportional to
the line voltage. Adjusting the ratio of RA and RB + VR is a
convenient way to carry out a gain calibration on the meter.
05
04
0-
0
14
1
RB + VR = RF.
VR
1
RB
1
RA
1
V
2P
NE
UT
RA
L
P
HAS
E
R
F
V
2N
C
T
V
2P
NE
UT
RA
L
P
HAS
E
R
F
R
F
V
2N
C
F
C
F
C
F
660mV
AGND
Figure 16. Typical Connection for Channel 2
Figure 17 shows a typical connection for the MISCAL input.
The voltage reference input (REF
IN/OUT
) is used as a dc reference
to set the MISCAL voltage.
Adjusting the level of MISCAL to calibrate the meter in missing
neutral mode can be done by changing the ratio of RC and RD
+ VR1. When the internal reference is used, the values of RC,
RD, and VR1 must be chosen to limit the current sourced by
the internal reference sourcing current to below the specified
20 A. Therefore, because V
REF
internal = 2.5 V, RC + RD +
VR1 > 600 k.
05
04
0-
0
15
VR1
RD
RC
MISCAL
R
F
V
2N
C
F
C
F
REF
IN/OUT
Figure 17. Typical Connection for MISCAL
INTERNAL OSCILLATOR
The nominal internal oscillator frequency is 450 kHz when
used with the recommended R
OSC
resistor value of 6.2 k
between RCLKIN and DGND (see Figure 18).
The internal oscillator frequency is inversely proportional to the
value of this resistor. Although the internal oscillator operates
when used with an R
OSC
resistor value between 5 k and 12 k,
it is recommended to choose a value within the range of the
nominal value.
The output frequencies on CF, F1, and F2 are directly propor-
tional to the internal oscillator frequency; therefore, the resistor
R
OSC
must have a low tolerance and low temperature drift. A low
tolerance resistor limits the variation of the internal oscillator
frequency. A small variation of the clock frequency and
consequently of the output frequencies from meter to meter
contributes to a smaller calibration range of the meter.
A low temperature drift resistor directly limits the variation of
the internal clock frequency over temperature. The stability of
the meter to external variation is then better ensured by design.
2.5V
REFERENCE
INTERNAL
OSCILLATOR
9
ADE7761A
DGND
RCLKIN
REF
IN/OUT
3k
0
50
40-
016
R
OSC
14
17
Figure 18. Internal Oscillator Connection
ADE7761A
Rev. 0 | Page 13 of 24
ANALOG-TO-DIGITAL CONVERSION
The analog-to-digital conversion in the ADE7761A is carried
out using second-order, - ADCs. Figure 19 shows a first-
order, - ADC (for simplicity). The converter is made up of
two parts: the - modulator and the digital low-pass filter.
04
40
7-
01
7
....10100101....
1-BIT DAC
LATCHED
COMPAR-
ATOR
INTEGRATOR
V
REF
MCLK
C
R
ANALOG
LOW-PASS FILTER
DIGITAL
LOW-PASS FILTER
1
24
Figure 19. First-Order, - ADC
A - modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7761A, the sampling clock is equal to CLKIN.
The 1-bit DAC in the feedback loop is driven by the serial data
stream. The DAC output is subtracted from the input signal. If
the loop gain is high enough, the average value of the DAC
output (and, therefore, the bit stream) approaches that of the
input signal level. For any given input value in a single sampling
interval, the data from the 1-bit ADC is virtually meaningless.
Only when a large number of samples are averaged is a meaningful
result obtained. This averaging is carried out in the second part
of the ADC, the digital low-pass filter. By averaging a large
number of bits from the modulator, the low-pass filter can
produce 24-bit data-words that are proportional to the input
signal level.
The - converter uses two techniques to achieve high
resolution from what is essentially a 1-bit conversion technique.
The first is oversampling, which means that the signal is sampled at
a rate (frequency) that is many times higher than the bandwidth
of interest. For example, the sampling rate in the ADE7761A is
CLKIN (450 kHz) and the band of interest is 40 Hz to 1 kHz.
Oversampling has the effect of spreading the quantization noise
(noise due to sampling) over a wider bandwidth. With the noise
spread more thinly over a wider bandwidth, the quantization
noise in the band of interest is lowered (see Figure 20).
However, oversampling alone is not an efficient enough method
to improve the signal-to-noise ratio (SNR) in the band of interest.
For example, an oversampling ratio of 4 is required just to
increase the SNR by only 6 dB (1 bit). To keep the oversampling
ratio at a reasonable level, it is possible to shape the quantization
noise so that the majority of the noise lies at the higher frequencies.
This is what happens in the - modulator; the noise is shaped
by the integrator, which has a high-pass type response for the
quantization noise. The result is that most of the noise is at the
higher frequencies, where it can be removed by the digital low-
pass filter. This noise shaping is also shown in Figure 20.
SHAPED NOISE
HIGH RESOLUTION
OUTPUT FROM
DIGITAL LFP
NOISE
SIGNAL
NOISE
SIGNAL
0
1
225
450
FREQUENCY (kHz)
0
1
225
450
FREQUENCY (kHz)
DIGITAL FILTER
ANTIALIAS FILTER (RC)
SAMPLING FREQUENCY
05
04
0-
0
18
Figure 20. Noise Reduction due to Oversampling and
Noise Shaping in the Analog Modulator
Antialias Filter
Figure 20 also shows an analog low-pass filter (RC) on input to
the modulator. This filter is present to prevent aliasing. Aliasing
is an artifact of all sampled systems, which means that frequency
components in the input signal to the ADC that are higher than
half the sampling rate of the ADC appear in the sampled signal
frequency below half the sampling rate. Figure 21 illustrates
the effect.
In Figure 21, frequency components (arrows shown in black)
above half the sampling frequency (also known as the Nyquist
frequency), that is, 225 kHz, are imaged or folded back down
below 225 kHz (arrows shown in gray). This happens with all
ADCs no matter what the architecture. In the example shown,
only frequencies near the sampling frequency (450 kHz) move
into the band of interest for metering (40 Hz to 1 kHz). This
fact allows the use of a very simple low-pass filter to attenuate
these frequencies (near 250 kHz) and thereby prevent distortion
in the band of interest. A simple RC filter (single pole) with a
corner frequency of 10 kHz produces an attenuation of
approximately 33 dB at 450 kHz (see Figure 21). This is
sufficient to eliminate the effects of aliasing.
0
50
40-
019
0
1
225
450
FREQUENCY (kHz)
IMAGE
FREQUENCIES
SAMPLING
FREQUENCY
ANTIALIASING EFFECTS
Figure 21. ADC and Signal Processing in Current Channel or Voltage Channel
ADE7761A
Rev. 0 | Page 14 of 24
ACTIVE POWER CALCULATION
The ADCs digitize the voltage signals from the current and
voltage transducers. A high-pass filter in the current channel
removes any dc component from the current signal. This
eliminates any inaccuracies in the active power calculation
due to offsets in the voltage or current signals (see the HPF and
Offset Effects section).
The active power calculation is derived from the instantaneous
power signal. The instantaneous power signal is generated by a
direct multiplication of the current and voltage signals. To
extract the active power component (dc component), the
instantaneous power signal is low-pass filtered. Figure 22
illustrates the instantaneous active power signal and shows how
the active power information can be extracted by low-pass
filtering the instantaneous power signal. This scheme correctly
calculates active power for nonsinusoidal current and voltage
waveforms at all power factors. All signal processing is carried
out in the digital domain for superior stability over temperature
and time.
05
04
0-
02
0
F2
CF
F1
DIGITAL-TO-
FREQUENCY
DIGITAL-TO-
FREQUENCY
HPF
MULTIPLIER
LPF
ADC
ADC
CH1
CH2
INSTANTANEOUS
POWER SIGNAL p(t)
INSTANTANEOUS
ACTIVE POWER SIGNAL
V I
V I
2
TIME
p(t) = i(t).v(t)
WHERE:
v(t) = V cos(t)
i(t) = I cos(t)
p(t) = V I {1 + cos (2t)}
2
PGA
Figure 22. Signal Processing Block Diagram
The low frequency output of the ADE7761A is generated by
accumulating this active power information. This low frequency
inherently means a long accumulation time between output
pulses. The output frequency is, therefore, proportional to the
average active power. This average active power information
can, in turn, be accumulated (for example, by a counter) to
generate active energy information. Because of its high output
frequency and, therefore, shorter integration time, the CF
output is proportional to the instantaneous active power. This is
useful for system calibration purposes that take place under
steady load conditions.
Power Factor Considerations
The method used to extract the active power information from
the instantaneous power signal (by low-pass filtering) is still valid
even when the voltage and current signals are not in phase.
Figure 23 displays the unity power factor condition and a
displacement power factor (DPF = 0.5), that is, current signal
lagging the voltage by 60.
INSTANTANEOUS
POWER SIGNAL
INSTANTANEOUS
ACTIVE POWER SIGNAL
INSTANTANEOUS
POWER SIGNAL
INSTANTANEOUS
ACTIVE POWER SIGNAL
60
CURRENT
CURRENT
VOLTAGE
0V
0V
VOLTAGE
05
04
0-
0
21
V I
2
V I
2
cos(60)
Figure 23. Active Power Calculation over PF
If one assumes that the voltage and current waveforms are
sinusoidal, the active power component of the instantaneous
power signal (dc term) is given by
(V I/2) cos(60)
This is the correct active power calculation.
Nonsinusoidal Voltage and Current
The active power calculation method also holds true for
nonsinusoidal current and voltage waveforms. All voltage
and current waveforms in practical applications have some
harmonic content. Using the Fourier transform, instantaneous
voltage and current waveforms can be expressed in terms of
their harmonic content
)
sin(
2
)
(
0
h
h
h
O
t
h
V
V
t
v
+
+
=
(1)
where:
v(t) is the instantaneous voltage.
V
O
is the average value.
V
h
is the rms value of voltage harmonic h.
h
is the phase angle of the voltage harmonic.
ADE7761A
Rev. 0 | Page 15 of 24
)
sin(
2
)
(
0
h
h
h
O
t
h
I
I
t
i
+
+
=
(2)
where:
i(t) is the instantaneous current.
I
O
is the dc component.
I
h
is the rms value of current harmonic h.
h
is the phase angle of the current harmonic.
Using Equation 1 and Equation 2, the active power P can be
expressed in terms of its fundamental active power (P
1
) and
harmonic active power (P
H
).
P = P
1
+ P
H
where:
P
1
= V
1
I
1
cos(
1
)
1
=
1
-
1
(3)
and
)
cos(
2
=
=
h
h
h
h
H
I
V
P
h
h
h
-
=
(4)
As can be seen in Equation 4, a harmonic active power component
is generated for every harmonic provided that the harmonic is
present in both the voltage and current waveforms. The power
factor calculation was previously shown to be accurate in the
case of a pure sinusoid; therefore, the harmonic active power
must also correctly account for the power factor because it is
made up of a series of pure sinusoids.
Note that the input bandwidth of the analog inputs is 7 kHz
with an internal oscillator frequency of 450 kHz.
HPF and Offset Effects
Equation 5 shows the effect of offsets on the active power
calculation. Figure 24 shows the effect of offsets on the active
power calculation in the frequency domain.
)
cos(
)
cos(
2
))
cos(
(
))
cos(
(
)
(
)
(
t
I
V
t
I
V
I
V
I
V
t
I
I
t
V
V
t
I
t
V
0
1
1
0
1
1
1
0
1
0
1
0
+
+
+
=
+
+
=
(5)
As can be seen in Equation 5 and Figure 24, an offset on Channel 1
and Channel 2 contributes a dc component after multiplication.
Because this dc component is extracted by the LPF and used to
generate the active power information, the offsets contribute a
constant error to the active power calculation. This problem is
easily avoided in the ADE7761A with the HPF in Channel 1. By
removing the offset from at least one channel, no error component
can be generated at dc by the multiplication. Error terms at cos(t)
are removed by the LPF and the digital-to-frequency conversion
(see the Digital-to-Frequency Conversion section).
The HPF in Channel 1 has an associated phase response that is
compensated for on-chip. Figure 25 and Figure 26 show the
phase error between channels with the compensation network
activated. The ADE7761A is phase compensated up to 1 kHz as
shown, which ensures a correct active harmonic power calculation
even at low power factors.
05
04
0-
02
2
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR ACTIVE
POWER CALCULATION
2
FREQUENCY (RAD/S)
0
V
1
I
0
V
0
I
1
V
1
I
1
2
Figure 24. Effect of Channel Offsets on the Active Power Calculation
FREQUENCY (Hz)
0
100
P
H
A
S
E
(
D
eg
rees)
0.05
0.10
0
0.05
0.10
0.15
0.20
0.25
0.30
200
300
400
500
600
700
800
900 1000
05
04
0-
02
3
Figure 25. Phase Error Between Channels (0 Hz to 1 kHz)
FREQUENCY (Hz)
40
P
HAS
E
(
D
eg
ree
s
)
0.05
0.10
0.05
0
0.10
0.15
0.20
0.25
0.30
45
50
55
60
65
70
05
04
0-
0
24
Figure 26. Phase Error Between Channels (40 Hz to 70 Hz)
ADE7761A
Rev. 0 | Page 16 of 24
DIGITAL-TO-FREQUENCY CONVERSION
As previously described, the digital output of the low-pass filter
after multiplication contains the active power information.
However, because this LPF is not an ideal brick wall filter
implementation, the output signal also contains attenuated
components at the line frequency and its harmonics, that is,
cos(ht), where h = 1, 2, 3, ..., and so on. The magnitude
response of the filter is given by
2
)
Hz
5
.
4
/
(
1
1
)
(
f
f
H
=
=
(6)
For a line frequency of 50 Hz, this gives an attenuation of the 2
(100 Hz) component of approximately -26.9 dB. The dominating
harmonic is at twice the line frequency, cos(2t), due to the
instantaneous power signal.
F1
F2
CF
DIGITAL-TO-
FREQUENCY
DIGITAL-TO-
FREQUENCY
MULTIPLIER
LPF
V
I
0
2
FREQUENCY (Rad/s)
LPF TO EXTRACT
ACTIVE POWER
(DC TERM)
TIME
TIME
0
504
0-
0
25
F
RE
Q
U
E
NC
Y
F
RE
Q
UE
NC
Y
F1
FOUT
INSTANTANEOUS ACTIVE POWER SIGNAL (FREQUENCY DOMAIN)
Figure 27. Active Power to Frequency Conversion
Figure 27 shows the instantaneous active power signal output of
the LPF, which still contains a significant amount of instantaneous
power information, cos(2t). This signal is then passed to the
digital-to-frequency converter, where it is integrated (accumulated)
over time to produce an output frequency. This accumulation of
the signal suppresses or averages out any non-dc components in
the instantaneous active power signal. The average value of a
sinusoidal signal is zero. Therefore, the frequency generated by
the ADE7761A is proportional to the average active power.
Figure 27 also shows the digital-to-frequency conversion for
steady load conditions: constant voltage and current. As can be
seen in Figure 27, the frequency output CF varies over time,
even under steady load conditions. This frequency variation is
primarily due to the cos(2t) component in the instantaneous
active power signal.
The output frequency on CF can be up to 2048 times higher
than the frequency on F1 and F2. This higher output frequency
is generated by accumulating the instantaneous active power
signal over a much shorter time while converting it to a frequency.
This shorter accumulation period means less averaging of the
cos(2t) component. As a consequence, some of this instantaneous
power signal passes through the digital-to-frequency conversion.
This is not a problem in the application.
Where CF is used for calibration purposes, the frequency
should be averaged by the frequency counter, which removes
any ripple. If CF is being used to measure energy, such as in a
microprocessor-based application, the CF output should also be
averaged to calculate power. Because the outputs, F1 and F2,
operate at a much lower frequency, a lot more averaging of the
instantaneous active power signal is carried out. The result is a
greatly attenuated sinusoidal content and a virtually ripple-free
frequency output.
TRANSFER FUNCTION
Frequency Outputs F1 and F2
The ADE7761A calculates the product of two voltage signals
(on Channel 1 and Channel 2) and then low-pass filters this
product to extract active power information. This active power
information is then converted to a frequency. The frequency
information is output on F1 and F2 in the form of active high
pulses. The pulse rate at these outputs is relatively low, for
example, 0.34 Hz maximum for ac signals with S0 = S1 = 0
(see Table 8). This means that the frequency at these outputs is
generated from active power information accumulated over a
relatively long period. The result is an output frequency that is
proportional to the average active power. The averaging of the
active power signal is implicit to the digital-to-frequency
conversion. The output frequency or pulse rate is related to
the input voltage signals by
2
2
1
70
.
5
REF
4
1
rms
rms
V
F
V2
V1
Gain
Frequency
F
F
-
=
-
(7)
where:
F
1
- F
2
Frequency is the output frequency on F
1
and F
2
(Hz).
V1
rms
is the differential rms voltage signal on Channel 1 (V).
V2
rms
is the differential rms voltage signal on Channel 2 (V).
Gain is 1 or 16, depending on the PGA gain selection made
using the logic input PGA.
V
REF
is the reference voltage (2.5 V 8%) (V).
F
14
is one of four possible frequencies selected by using the
logic inputs S0 and S1 (see Table 6).
ADE7761A
Rev. 0 | Page 17 of 24
Table 6. F
14
Frequency Selection
S1 S0 F
14
(Hz)
1
F
1-4
= OSC/2
n 2
0 0 1.72
OSC/2
18
0 1 3.44
OSC/2
17
1 0 6.86
OSC/2
16
1 1 13.7
OSC/2
15
1
Values are generated using the nominal frequency of 450 kHz.
2
F
14
are a binary fraction of the master clock and, therefore, vary with the
internal oscillator frequency (OSC).
Frequency Output CF
The pulse output calibration frequency (CF) is intended for use
during calibration. The output pulse rate on CF can be up to
2048 times the pulse rate on F1 and F2. The lower the F
14
frequency selected, the higher the CF scaling. Table 7 shows
how the two frequencies are related, depending on the states of
the logic inputs S0, S1, and SCF. Because of its relatively high
pulse rate, the frequency at this logic output is proportional to
the instantaneous active power. As with F1 and F2, the
frequency is derived from the output of the low-pass filter after
multiplication. However, because the output frequency is high,
this active power information is accumulated over a much
shorter time. Therefore, less averaging is carried out in the
digital-to-frequency conversion. With much less averaging of
the active power signal, the CF output is much more responsive
to power fluctuations (see Figure 22).
Table 7. Relationship Between CF and F1, F2 Frequency
Outputs
SCF S1 S0 F
14
(Hz)
CF Frequency Output
1
0
0
1.72
128 F1, F2
0
0
0
1.72
64 F1, F2
1
0
1
3.44
64 F1, F2
0
0
1
3.44
32 F1, F2
1
1
0
6.86
32 F1, F2
0
1
0
6.86
16 F1, F2
1
1
1
13.7
16 F1, F2
0
1
1
13.7
2048 F1, F2
Example
In this example, if ac voltages of 660 mV peak are applied to
V1 and V2, then the expected output frequency on CF, F1, and
F2 is calculated as
Gain = 1, PGA = 0
F
14
= 1.7 Hz, SCF = S1 = S0 = 0
V1
rms
= rms of 660 mV peak ac = 0.66/2 V
V2
rms
= rms of 660 mV peak ac = 0.66/2 V
V
REF
= 2.5 V (nominal reference value)
Note that if the on-chip reference is used, actual output
frequencies can vary from device to device due to a reference
tolerance of 8%.
Hz
34
.
0
5
.
2
2
2
Hz
72
.
1
66
.
0
66
.
0
70
.
5
2
2
1
=
=
- Frequency
F
F
CF Frequency = F
1
- F
2
64 = 22.0 Hz
As can be seen from these two example calculations, the
maximum output frequency for ac inputs is always half of that
for dc input signals. Table 8 shows a complete listing of all
maximum output frequencies for ac signals.
Table 8. Maximum Output Frequencies on CF, F1, and F2 for
AC Inputs
SCF S1 S0
F1, F2 Maximum
Frequency (Hz)
CF Maximum
Frequency (Hz)
CF-to-
F1 Ratio
1 0 0 0.34
43.52
128
0 0 0 0.34
21.76
64
1 0 1 0.68
43.52
64
0 0 1 0.68
21.76
32
1 1 0 1.36
43.52
32
0 1 0 1.36
21.76
16
1 1 1 2.72
43.52
16
0 1 1 2.72
5570
2048
FAULT DETECTION
The ADE7761A incorporates a novel fault detection scheme
that warns of fault conditions and allows the ADE7761A to
continue accurate billing during a fault event. The ADE7761A
does this by continuously monitoring both the phase and
neutral (return) currents. A fault is indicated when these
currents differ by more than 6.25%. However, even during a
fault, the output pulse rate on F1 and F2 is generated using the
larger of the two currents. Because the ADE7761A looks for a
difference between the voltage signals on V
1A
and V
1B
, it is
important that both current transducers be closely matched.
On power-up, the output pulse rate of the ADE7761A is
proportional to the product of the voltage signals on V
1A
and
Channel 2. If the difference between V
1A
and V
1B
on power-up is
greater than 6.25%, the fault indicator (FAULT) becomes active
after about 1 sec. In addition, if V
1B
is greater than V
1A
, the
ADE7761A selects V
1B
as the input. The fault detection is
automatically disabled when the voltage signal on Channel 1 is
less than 0.3% of the full-scale input range. This eliminates false
detection of a fault due to noise at light loads.
ADE7761A
Rev. 0 | Page 18 of 24
Fault with Active Input Greater than Inactive Input
If V
1A
is the active current input (that is, being used for billing),
and the voltage signal on V
1B
(inactive input) falls below 93.75%
of V
1A
, the fault indicator becomes active. Both analog inputs
are filtered and averaged to prevent false triggering of this logic
output. As a consequence of the filtering, there is a time delay of
approximately 3 sec on the logic output FAULT after the fault
event. The FAULT logic output is independent of any activity on
outputs F1 or F2. Figure 28 shows one condition under which
FAULT becomes active. Because V
1A
is the active input and it is
still greater than V
1B
, billing is maintained on V
1A
, that is, no
swap to the V
1B
input occurs. V
1A
remains the active input.
V
1B
V
1N
V
1A
AGND
FILTER
AND
COMPARE
TO
MULTIPLIER
FAULT
A
B
V
1A
V
1B
V
1B
< 93.75% OF V
1A
>0
<0
ACTIVE POINT INACTIVE INPUT
6.25% OF ACTIVE INPUT
05
04
0-
0
26
0V
FAULT
V
1A
V
1B
Figure 28. Fault Conditions for Active Input Greater than Inactive Input
Fault with Inactive Input Greater than Active Input
Figure 29 illustrates another fault condition. If the difference
between V
1B
, the inactive input, and V
1A
, the active input (that
is, being used for billing), becomes greater than 6.25% of V
1B
,
the FAULT indicator becomes active and a swap over to the V
1B
input occurs. The analog input V
1B
becomes the active input.
Again, a time constant of about 3 sec is associated with this
swap. V
1A
does not swap back to the active channel until V
1A
is
greater than V
1B
and the difference between V
1A
and V
1B
--in
this order--becomes greater than 6.25% of V
1A
. However, the
FAULT indicator becomes inactive as soon as V
1A
is within
6.25% of V
1B
. This threshold eliminates potential chatter
between V
1A
and V
1B
.
V
1B
V
1N
V
1A
AGND
FILTER
AND
COMPARE
TO
MULTIPLIER
FAULT
A
B
V
1A
V
1B
V
1A
< 93.75% OF V
1B
>0
<0
ACTIVE POINT INACTIVE INPUT
6.25% OF INACTIVE INPUT
05
04
0-
0
27
0V
FAULT + SWAP
V
1A
V
1B
Figure 29. Fault Conditions for Inactive Input Greater than Active Input
Calibration Concerns
Typically, when a meter is being calibrated, the voltage and
current circuits are separated, as shown in Figure 30. This
means that current passes through only the phase or neutral
circuit. Figure 30 shows current being passed through the phase
circuit. This is the preferred option because the ADE7761A
starts billing on the input V
1A
on power-up. The phase circuit
CT is connected to V
1A
in Figure 30. Because there is no current
in the neutral circuit, the FAULT indicator comes on under
these conditions. However, this does not affect the accuracy of
the calibration and can be used as a means to test the functionality
of the fault detection.
AGND
V
1B
V
1N
V
1A
R
F
R
F
C
F
C
F
CT
CT
RB
RB
0V
V
1A
IB
IB
P
HAS
E
NE
UT
RA
L
1
RB + VR = RF.
VR
1
RB
1
RA
1
V
2P
R
F
V
2N
C
T
C
F
V
TEST
CURRENT
240V rms
05
04
0-
0
28
Figure 30. Conditions for Calibration of Channel B
If the neutral circuit is chosen for the current circuit in the
arrangement shown in Figure 30, this may have implications for
the calibration accuracy. The ADE7761A powers up with the
V
1A
input active as normal. However, because there is no
current in the phase circuit, the signal on V
1A
is zero. This
causes a fault to be flagged and the active input to be swapped
to V
1B
(neutral). The meter can be calibrated in this mode, but
the phase and neutral CTs may differ slightly. Because under
no-fault conditions all billing is carried out using the phase CT,
the meter should be calibrated using the phase circuit. Of
course, both phase and neutral circuits can be calibrated.
MISSING NEUTRAL MODE
The ADE7761A integrates a novel fault detection that warns
and allows the ADE7761A to continue to bill in case a meter is
connected to only one wire (see Figure 31). For correct
operation of the ADE7761A in this mode, the V
DD
pin of the
ADE7761A must be maintained within the specified range (5 V
5%). The missing neutral detection algorithm is designed to
work over a line frequency of 45 Hz to 55 Hz.
ADE7761A
Rev. 0 | Page 19 of 24
V
1B
V
1N
V
1A
R
F
R
F
C
F
C
F
CT
CT
RB
RB
0V
V
1A
1
RB + VR = RF.
VR
1
RB
1
RA
1
V
2P
R
F
V
2N
C
T
C
F
05
04
0-
0
29
LOAD
244V rms
POWER
GENERATOR
IB
Figure 31. Missing Neutral System Diagram
The ADE7761A detects a missing neutral condition by
continuously monitoring the voltage channel input (V
2P
- V
2N
).
The FAULT pin is held high when a missing neutral condition is
detected. In this mode, the ADE7761A continues to bill the
energy based on the signal level on the current channel (see
Figure 32). The billing rate or frequency outputs can be adjusted
by changing the dc level on the MISCAL pin.
V
1A
V
1N
V
1B
MISSING NEUTRAL
GAIN ADJUSMTENT
DIGITAL-TO-
FREQUENCY
CONVERTERS
CF F1 F2
050
40
-
03
0
ZERO
CROSSING
DETECTION
A > B
B > A
B <> A
ADC
ADC
ADC
MISCAL
LPF
HPF
Figure 32. Energy Calculation in Missing Neutral Mode
Important Note for Billing of Active Energy
The ADE7761A provides pulse outputs--CF, F1, and F2--
intended to be used for the billing of active energy. Pulses
are generated at these outputs in two different situations.
Case 1
: When the analog input V
2P
V
2N
complies with the
conditions described in Figure 34, CF, F1, and F2 frequencies
are proportional to active power and can be used to bill active
energy.
Case 2
: When the analog input V
2P
V
2N
does not comply with
the conditions described in Figure 34, the ADE7761A does not
measure active energy but a quantity proportional to kAh. This
quantity is used to generate pulses on the same CF, F1, and F2.
This situation is indicated when the FAULT pin is high.
Analog Devices, Inc. cautions users of the ADE7761A about the
following:
Billing active energy in Case 1 is consistent with the
understanding of the quantity represented by pulses on CF,
F1, and F2 outputs (watt-hour).
Billing active energy while the ADE7761A is in Case 2 must
be decided knowing that the entity measured by the
ADE7761A in this case is ampere-hour and not watt-hour.
Users should be aware of this limitation and decide if the
ADE7761A is appropriate for their application.
Missing Neutral Detection
The ADE7761A continuously monitors the voltage input and
detects a missing neutral condition when the voltage input peak
value is smaller than 9% of the analog full scale or when no zero
crossings are detected on this input (see Figure 33).
0V
FS
FS
0V
FS
05
04
0-
03
1
9% OF FS
0V
FILTER AND
THRESHOLD
V2
V
2P
V
2N
AGND
ADC
MISSING
NEUTRAL
|V2|
PEAK
< 9% OF FULL SCALE
V
2P
V
2N
V
2P
V
2N
V
2P
V
2N
NO ZERO CROSSING ON V2
OR
Figure 33. Missing Neutral Detection
The ADE7761A leaves the missing neutral mode for normal
operation when both conditions are no longer valid, that is, a
voltage peak value of greater than 9% of full scale and zero
crossing on the voltage channel is detected (see Figure 34).
05
04
0-
03
2
FILTER AND
THRESHOLD
V2
V
2P
V
2N
AGND
ADC
MISSING
NEUTRAL
|V2|
PEAK
> 9% OF FULL SCALE
AND
ZERO CROSSING ON V2
FS
+9% OF FS
9% OF FS
V
2P
V
2N
Figure 34. Return to Normal Mode after Missing Neutral Detection
ADE7761A
Rev. 0 | Page 20 of 24
Missing Neutral Gain Calibration
Example
When the ADE7761A is in missing neutral mode, the energy is
bill based on the active current input signal level. The frequency
outputs in this mode can be calibrated with the MISCAL analog
input pin. In this mode, applying a dc voltage of 330 mV on
MISCAL is equivalent to applying, in normal mode, a pure sine
wave on the voltage input with a peak value of 330 mV. The
MISCAL input can vary from 0 V to 660 mV (see the Analog
Inputs section). When set to 0 V, the frequency outputs are
close to zero. When set to 660 mV dc, the frequency outputs are
twice that when MISCAL is at 330 mV dc. In other words,
Equation 7 can be used in missing neutral mode by replacing
V2
rms
by MISCAL
rms
/2.
In normal mode, ac voltages of 330 mV peak are applied to V1
and V2, and then the expected output frequency on F
1
and F
2
is
calculated as:
Gain =1 ; PGA =0
F
14
= 1.7 Hz, SCF = S1 = S0 = 0
V1 = rms of 330 mV peak ac = 0.33/2 V
V2 = rms of 330 mV peak ac = 0.33/2 V
V
REF
= 2.5 V (nominal reference value)
Hz
084
.
0
5
.
2
2
2
Hz
7
.
1
33
.
0
33
.
0
70
.
5
,
2
2
1
=
=
Frequency
F
F
2
4
1
2
1
2
/
1
70
.
5
,
REF
rms
rms
V
F
MISCAL
V
Gain
Frequency
F
F
-
=
(8)
CF Frequency = F
1
- F
2
Frequency 64 = 5.4 Hz
In missing neutral mode, the ac voltage of 330 mV peak is
applied to V1, no signal is connected on V2, and a 330 mV dc
input is applied to MISCAL. With the ADE7761A in the same
configuration as the previous example, the expected output
frequencies on CF, F
1
, and F
2
are
where:
F
1
, F
2
Frequency is the output frequency on F
1
and F
2
(Hz).
V1
rms
is the differential rms voltage signal on Channel 1 (V).
MISCAL
rms
is the differential rms voltage signal on the MISCAL
pin (V).
Hz
084
.
0
5
.
2
2
Hz
7
.
1
2
/
33
.
0
33
.
0
70
.
5
,
2
=
=
Frequency
F
F
2
1
Gain is 1 or 16, depending on the PGA gain selection made
using logic input PGA.
CF Frequency = F
1
, F
2
Frequency 64 = 5.4 Hz
V
REF
is the reference voltage (2.5 V 8%) (V).
F
1-4
is one of four possible frequencies selected by using the
logic inputs S0 and S1 (see Table 6).
ADE7761A
Rev. 0 | Page 21 of 24
APPLICATIONS
INTERFACING TO A MICROCONTROLLER FOR
ENERGY MEASUREMENT
The easiest way to interface the ADE7761A to a microcontroller
is to use the CF high frequency output with the output frequency
scaling set to 2048 F1, F2. This is done by setting SCF = 0
and S0 = S1 = 1 (see Table 8). With full-scale ac signals on the
analog inputs, the output frequency on CF is approximately
5.5 kHz. Figure 35 illustrates one scheme that could be used to
digitize the output frequency and carry out the necessary
averaging mentioned in the Frequency Output CF section.
TIME
10%
AVERAGE
FREQUENCY
CF
FREQUENCY
RIPPLE
MCU
UP/DOWN
COUNTER
LOGIC
CF
REVP
1
ADE7761A
FAULT
2
05
04
0-
03
3
1
REVP MUST BE USED IF THE METER IS BIDIRECTIONAL OR
DIRECTION OF ENERGY FLOW IS NEEDED.
2
FAULT MUST BE USED TO RECORD ENERGY IN FAULT CONDITION.
Figure 35. Interfacing the ADE7761A to an MCU
As shown in Figure 35 the frequency output CF is connected to
an MCU counter or port, which counts the number of pulses in
a given integration time, determined by an MCU internal timer.
The average power, proportional to the average frequency, is
Timer
Counter
Power
Active
Average
Frequency
Average
=
=
The energy consumed during an integration period is
Counter
Time
Time
Counter
Time
Power
Average
Energy
=
=
=
For the purpose of calibration, this integration time could be
10 sec to 20 sec to accumulate enough pulses to ensure correct
averaging of the frequency. In normal operation, the integration
time could be reduced to 1 sec or 2 sec depending on, for
example, the required update rate of a display. With shorter
integration times on the MCU, the amount of energy in each
update may still have a small amount of ripple, even under
steady load conditions. However, over a minute or more, the
measured energy has no ripple.
SELECTING A FREQUENCY FOR AN ENERGY
METER APPLICATION
As shown in Table 6, the user can select one of four frequencies.
This frequency selection determines the maximum frequency
on F1 and F2. These outputs are intended to be used to drive
the energy register (electromechanical or other). Because only
four different output frequencies can be selected, the available
frequency selection was optimized for a meter constant of
100 impulses/kWh with a maximum current of between 10 A
and 120 A. Table 9 shows the output frequency for several
maximum currents (I
MAX
) with a line voltage of 240 V. In all
cases, the meter constant is 100 impulses/kWh.
Table 9. F1 and F2 Frequency at 100 Impulses/kWh
I
MAX
(A)
F1 and F2 (Hz)
12.5
0.083
25
0.166
40
0.266
60
0.4
80
0.533
120
0.8
The F
14
frequencies allow complete coverage of this range of
output frequencies on F1 and F2. When designing an energy
meter, the nominal design voltage on Channel 2 (voltage)
should be set to half-scale to allow for calibration of the meter
constant. The current channel should also be no more than half-
scale when the meter sees maximum load, which accommodates
overcurrent signals and signals with high crest factors. Table 10
shows the output frequency on F1 and F2 when both analog
inputs are half-scale. The frequencies listed in Table 10 align
well with those listed in Table 9 for maximum load.
Table 10. F1 and F2 Frequency with Half-Scale AC Inputs
S0 S1 F
14
(Hz)
Frequency on F1 and F2, Ch 1 and Ch 2,
Half-Scale AC Inputs (Hz)
0 0 1.72
0.085
0 1 3.44
0.17
1 0 6.86
0.34
1 1 13.5
0.68
When selecting a suitable F
14
frequency for a meter design, the
frequency output at I
MAX
(maximum load) with a meter constant
of 100 impulses/kWh should be compared with Column 4 of
Table 10. The frequency that is closest in Table 10 determines
the best choice of frequency (F
1-4
). For example, if a meter with
a maximum current of 40 A is being designed, the output
frequency on F1 and F2 with a meter constant of 100 impulses
per kWh is 0.266 Hz at 40 A and 240 V (see Table 9).
ADE7761A
Rev. 0 | Page 22 of 24
Looking at Table 10, the closest frequency to 0.266 Hz
in Column 4 is 0.17 Hz. Therefore, F2 (3.4 Hz; see Table 6) is
selected for this design.
Frequency Outputs
Figure 2 is a timing diagram for the various frequency outputs.
The high frequency CF output is intended for communication
and calibration purposes. CF produces a 90 ms wide, active
high pulse (t
4
) at a frequency that is proportional to active
power. The CF output frequencies are given in Table 8. As with
F1 and F2, if the period of CF (t
5
) falls below 180 ms, the CF
pulse width is set to half the period. For example, if the CF
frequency is 20 Hz, the CF pulse width is 25 ms.
No-Load Threshold
The ADE7761A includes a no-load threshold and start-up
current feature that eliminates creep effects in the meter. The
ADE7761A is designed to issue a minimum output frequency.
Any load generating a frequency lower than this minimum
frequency does not cause a pulse to be issued on F1, F2, or CF.
The minimum output frequency is given as 0.0045% of the full-
scale output frequency. (See Table 8 for maximum output
frequencies for ac signals).
For example, an energy meter with a meter constant of
100 impulses per kWh on F1, F2 using SCF = 1, S1 = 0, and
S0 = 1, the maximum output frequency at F1 or F2 is 0.68 Hz
and 43.52 Hz on CF. The minimum output frequency at F1
or F2 is 0.0045% of 0.68 Hz or 3.06 10
5
Hz. This is 1.96
10
3
Hz at CF (64 F1 Hz).
In this example, the no-load threshold is equivalent to 1.1 W of
load or a startup current of 4.6 mA at 240 V. Compare this value
to the IEC 32053-21 specification, which states that the meter
must start up with a load equal to or less than 0.4% of I
B
. For a
5 A (I
B
B
B
) meter, 0.4% of I
B
is equivalent to 20 mA.
B
Note that the no-load threshold is not enabled when using the
high CF frequency mode: SCF = 0, S1 = S0 = 1.
NEGATIVE POWER INFORMATION
The ADE7761A detects when the current and voltage channels
have a phase shift greater than 90. This mechanism can detect
a wrong connection of the meter or the generation of negative
power. The REVP pin output goes active high when negative
power is detected and active low when positive power is
detected. The REVP pin output changes state as a pulse is
issued on CF.
ADE7761A
Rev. 0 | Page 23 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-150-AE
06
01
06
-
A
20
11
10
1
7.50
7.20
6.90
8.20
7.80
7.40
5.60
5.30
5.00
SEATING
PLANE
0.05 MIN
0.65 BSC
2.00 MAX
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
8
4
0
Figure 36. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADE7761AARS
40C to +85C
20-Lead Shrink Small Outline Package (SSOP)
RS-20
ADE7761AARS-RL
40C to +85C
20-Lead Shrink Small Outline Package (SSOP)
RS-20
ADE7761AARSZ
1
40C to +85C
20-Lead Shrink Small Outline Package (SSOP)
RS-20
ADE7761AARSZ-RL
1
40C to +85C
20-Lead Shrink Small Outline Package (SSOP)
RS-20
ADE7761AARS-REF
Reference
Board
1
Z = Pb-free part.
ADE7761A
Rev. 0 | Page 24 of 24
NOTES
2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05040-0-7/06(0)
Document Outline
-
- GENERAL DESCRIPTION
-
-
-
-
-
- PERFORMANCE ISSUES THAT MAY AFFECT BILLING ACCURACY
-
-
-
-
-
-
-
-
-
-
-
- Power Factor Considerations
-
-
-
-
-
-
-
-
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