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Quad Voltage Monitor and Sequencer

Preliminary Technical Data

ADM1185

Rev. PrK June 2006

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

Powered from 2.7V to 5.5V on the VCC pin

Monitors Four Supplies via 0.8% Accurate Comparators

Four inputs can be programmed for voltage levels with

resistor dividers

Three Open-Drain Enable Outputs

Open-Drain Power Good Output

10-pin MSOP Package

APPLICATIONS

Monitor and Alarm Functions

Power Supply Sequencing

Telecommunication and Datacommunication Equipment

PC/Servers

GENERAL DESCRIPTION

The ADM1185 is an integrated four channel voltage monitoring
device. A 2.7V to 5.5V power supply is required on the VCC pin
to power the device.

Four precision comparators monitor four voltage rails. All
comparators have a 0.6V reference with a worst-case accuracy
of 0.8%. Resistor networks external to the VIN1-VIN4 pins set
the trip points.

There are four open-drain outputs on the device. A digital core
interprets the comparator outputs and asserts the outputs as
appropriate.

FUNCTIONAL BLOCK DIAGRAM

OUT1

PWRGD

VCC

VIN2

REF=0.6V

VIN3

REF=0.6V

VIN4

REF=0.6V

GND

OUT2

OUT3

LOGIC

POWER AND
REFERENCE
GENERATOR

REF=0.6V

VIN1

ADM1185

Figure 1.

APPLICATIONS DIAGRAM

OUT1

OUT2

OUT3

2.5V OUT

1.8V OUT

PWRGD

VIN4

VIN2

VIN3

POWER

GOOD

Regulator1

3.3V IN

OUT

2.5V OUT

OUT

1.8V OUT

OUT

GND

1.2V OUT

Regulator2

Regulator3

VCC

VIN1

ADM1185

Figure 2.

Preliminary Technical Data

ADM1185

Rev. PrK | Page 3 of 12

ADM1185--SPECIFICATIONS

VCC

= 2.7V to 5.5V, T

= -40°C to +85°C

Table 1.

Parameter Min

Typ

Max

Units

Conditions

VCC Pin

Operating Voltage Range, V

VCC

2.7

5.5

Supply Current, I

VCC

100

µA

VIN1-VIN4 Pins

Input Current, I

VINLEAK

-100

100

VINx

= 0.7V

Input Rising Threshold, V

THR

0.5952

0.6000

0.6048

Input Rising Hysteresis, V

HYST

(=V

THR

-V

THF

)

OUT1-OUT3, PWRGD Pins

Output low voltage, V

OUTL

0.4

VCC

= 2.7 V, I

SINK

= 2mA

0.4

VCC

= 1 V, I

SINK

=100µA

Leakage Current, I

ALERT

-1 1

µA

VCC

that guarantees outputs valid

All outputs will be guaranteed to be either
low or giving a valid output level from V

VCC

= 1V.

VIN1 to OUT1 Delay

100

190

280

VIN1

Rising

VIN4 to PWRGD Delay

100

190

280

VIN4

Rising, condition only valid at certain

operational states, refer to state diagram

High-to-Low Propagation Delay

µs

VCC

=3.3V, see TPC1

Low-to-High Propagation Delay

µs

VCC

=3.3V, see TPC1

ADM1185

Preliminary Technical Data

Rev. PrK | Page 4 of 12

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

-0.3 V to +6 V

VIN1-VIN4 Pin

-0.3 V to +6 V

OUT1-OUT3, PWRGD Pins

-0.3 V to +6 V

Power Dissipation

TBD

Storage Temperature

-65°C to +125°C

Operating Temperature Range

-40°C to +85°C

Lead Temperature Range

(Soldering 10 sec)

300°C

Junction Temperature

150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only. Functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions may affect device reliability.
Ambient temperature = 25°C, unless otherwise noted.

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Preliminary Technical Data

ADM1185

Rev. PrK | Page 5 of 12

PIN CONFIGURATIONS

ADM1185

TOP VIEW

(NOT TO SCALE)

Vcc

OUT2

OUT3

PWRGD

VIN4

VIN2

VIN1

VIN3

OUT1

GND

Figure 3. Pin Configurations

PIN FUNCTIONAL DESCRIPTIONS

Table 3.

Pin No.

Name

Description

GND

Chip Ground Pin.

2 VIN1

Non-inverting input of comparator 1. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.

3 VIN2

Non-inverting input of comparator 2. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.

4 VIN3

Non-inverting input of comparator 3. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.

5 VIN4

Non-inverting input of comparator 4. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.

6 PWRGD Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when

the voltage on VIN4 is greater than 0.6V. A time delay of 190ms (typical) is included before assertion of this
pin. After power-up (after PWRGD asserts) this output will be driven low if any of the voltages on the VIN1-
VIN4 pins falls below 0.6V.

7 OUT3

Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when
the voltage on VIN3 is greater than 0.6V. After power-up (after PWRGD asserts) this output will be driven low
if the voltage on VIN1 falls below 0.6V.

8 OUT2

Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when
the voltage on VIN2 is greater than 0.6V. After power-up (after PWRGD asserts) this output will be driven low
if the voltage on VIN1 falls below 0.6V.

9 OUT1

Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when
the voltage on VIN1 is greater than 0.6V. A time delay of 190ms (typical) is included before assertion of this
pin. After power-up (after PWRGD asserts) this output will be driven low if the voltage on VIN1 falls below
0.6V.

VCC

Positive supply input pin. The operating supply voltage range is 2.7 V to 5.5 V.

Preliminary Technical Data

ADM1185

Rev. PrK | Page 7 of 12

Functional Description

The operation of the ADM1185 is explained in this section in
the context of the device in a voltage monitoring and
sequencing application (figure 4, above). In this application, the
ADM1185 will monitor four separate voltage rails, turn on
three regulators in a predefined sequence and generate a power
good signal to turn on a controller when all power supplies are
up and stable.

POWER ON SEQUENCING AND MONITORING

The main supply (in this case 3.3V) powers up the device via
the VCC pin as the voltage rises. A supply voltage of 2.7V to
5.5V is needed to power the device.

The VIN1 pin is monitoring the main 3.3V supply. An external
resistor divider will scale this voltage down for monitoring at
the VIN1 pin. The resistor ratio is chosen so that the VIN1
voltage is 0.6V when the main voltage rises to the preferred
level at start-up (some voltage below the nominal 3.3V level). In
this case, R1 is 4.6K and R2 is 1.2K so that a voltage level of
2.9V will correspond to 0.6V on the non-inverting input of the
first comparator.

TO LOGIC

CORE

ADM1185

3.3V

0.6V

2.9V supply
gives 0.6V
at VIN1 pin

2.9V

1.2K

4.6K

VIN1

Figure 4.Setting the undervoltage threshold with an external resistor divider

OUT1 is an open drain active high output. In this application,
OUT1 is connected to the enable pin of a regulator. Before the
voltage on VIN1 has reached 0.6V this output is switched to
ground, disabling regulator 1. (Note that all outputs are driven
to ground as long as there is 1V on the VCC pin of the
ADM1185). When the main system voltage reaches 2.9V VIN1
will detect 0.6V and this will cause OUT1 to assert after a
190ms delay. When this occurs the open drain output will
switch high and the external pull-up resistor will pull the
voltage on the regulator 1 enable pin above its turn-on
threshold, turning on the output of regulator 1.

The assertion of OUT1 will turn on Regulator1. The 2.5V
output of this regulator will begin to rise. This will be detected
by input VIN2 (with a similar resistor divider scheme as shows
in figure 5). When VIN2 sees the 2.5V rail rise above its UV
point it will assert output OUT2, turning on Regulator2. A
capacitor can be placed on the VIN2 pin to slow the rise of the
voltage on this pin- this effectively sets a time delay between the
2.5V rail powering up and the next Regulator being enabled.

The same scheme is implemented with the other input and
output pins. Every rail that is turned on via an output pin
OUT(n) is monitored via input pin VIN(n+1).

The final comparator inside the VIN4 pin detects the final
supply turning on, which is 1.2V in this case. All of the output
pins (OUT1-OUT3) are logically ANDed together to generate a
system power good signal (PWRGD). There is an internal
190ms delay associated with the assertion of the PWRGD
output.

Table 4 below is a truth table that steps through the power on
sequence of the outputs. Any associated internal time delays are
also shown.

VOLTAGE MONITORING AFTER POWER ON

Once PWRGD is asserted the logical core latches into a
different mode of operation. During the initial power up phase
each output is directly dependant on an input (i.e. VIN3
asserting causes OUT3 to assert). When power up is complete
this function is redundant.

Once in the PWRGD state the following behavior can be
observed:

If the main 3.3V supply that is monitored via VIN1
faults in the power good state then the PWRGD
output is deasserted to warn the downstream
controller and all of the outputs OUT1-OUT3 are
immediately turned off, disabling all locally generated
supplies.

If a supply monitored by VIN2-VIN4 fails the
PWRGD output is deasserted to warn the controller
but the other outputs are not deasserted.

Table 5 and table 6 are truth tables that highlight the behavior of
the ADM1185 under various fault situations during normal
operation (i.e. in the mode of operation after PWRGD has
asserted).

ADM1185

Preliminary Technical Data

Rev. PrK | Page 8 of 12

OUT1

OUT2

OUT3

2.5V OUT

1.8V OUT

PWRGD

VIN4

VIN2

VIN3

POWER

GOOD

Regulator1

3.3V IN

OUT

2.5V OUT

OUT

1.8V OUT

OUT

GND

1.2V OUT

Regulator2

Regulator3

VCC

VIN1

ADM1185

Figure 5. Applications Diagram showing ADM1185 in a voltage monitoring and sequencing application

State1

IN1=FAULT

IN1=OK

(Delay=100ms min)

IN1=FAULT

Start

State2

State3

State4

State5

OUT1

IN2=OK

IN3=OK

IN4=OK

(Delay=100ms min)

OUT1,2

OUT1,2,3

PWRGD

IN2.IN3.IN3=FAULT

Figure 6. Flow Diagram highlighting the different modes of operation o the logical core

State

State Name

OUT1 OUT2 OUT3 OUT4

Next Event

Next State

Reset* 0 0 0 0

IN1

High

for

190ms

Out1

Out1 On

IN1 and IN2 High for 30us

Out1,2 On

IN1 and IN3 High for 30us

Out1,2,3 On

All High for 190ms

PowerGood

IN2 or IN3 or IN4 Low for

30us

Out1,2,3 On

PowerGood

1 1 1 1

IN1 Low for 30 us

Start

Table 4. Truth table

ADM1185

Preliminary Technical Data

Rev. PrK | Page 10 of 12

CASCADING MULTIPLE DEVICES

Multiple ADM1185 devices can be cascaded in situations where
a large number of supplies must be monitored and/or
sequenced. There are numerous configurations for
interconnecting devices. The most suitable configuration will
depend on the application. Figures 8, 9 and 10 show some
methods for cascading multiple ADM1185 devices.

OUT1

OUT2

OUT3

PWRGD

VIN3

VIN1

VIN2

3.3V

GND

VCC

Reg1

EN1

Reg2

EN2

Reg3

EN3

3.3V

OUT1

OUT2

PWRGD

GND

VCC

Reg4

EN4

Reg5

EN5

3.3V

VIN1

POWER GOOD

ADM1185-A

ADM1185-B

Note: Supplies
scaled down with
resistor dividers

VIN4

VIN3

VIN2

VIN4

OUT3

Reg6

EN6

Figure 8. Cascading multiple ADM1185 devices, option 1

Preliminary Technical Data

ADM1185

Rev. PrK | Page 11 of 12

OUT1

OUT2

OUT3

PWRGD

VIN3

VIN1

VIN2

3.3V

GND

VCC

Reg1

EN1

Reg2

EN2

Reg3

EN3

3.3V

OUT1

OUT2

PWRGD

GND

VCC

Reg4

EN4

Reg5

EN5

3.3V

VIN1

POWER GOOD

ADM1185-A

ADM1185-B

Note: Supplies
scaled down with
resistor dividers

VIN4

VIN3

VIN2

VIN4

OUT3

Reg6

EN6

3.3V

Figure 9. Cascading multiple ADM1185 devices, option 2

OUT1

OUT2

OUT3

PWRGD

VIN3

VIN1

VIN2

3.3V

GND

VCC

Reg1

EN1

Reg2

EN2

Reg3

EN3

3.3V

OUT1

OUT2

PWRGD

GND

VCC

3.3V

VIN1

POWER GOOD

ADM1185-A

ADM1185-B

Note: Supplies
scaled down with
resistor dividers

VIN4

VIN3

VIN2

VIN4

OUT3

3.3V

Reg5

Reg4

EN5

EN4

Figure 10. Cascading multiple ADM1185 devices, option 3

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