REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

ADP3153

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1998

5-Bit Programmable Dual

Power Supply Controller

for Pentium

II Processor

FEATURES
5-Bit Digitally Programmable 1.8 V to 3.5 V Output

Voltage

Dual N-Channel Synchronous Driver
Total Output Accuracy 1% (0 C to +70 C)
High Efficiency
Current-Mode Operation
Short Circuit Protection
Power Good Output
Overvoltage Protection Crowbar
On-Board Linear Regulator Controller
VRM 8.2 Compatible
Narrow Body TSSOP 20-Lead Package

APPLICATIONS
Desktop PC Power Supply for:

Pentium II Processor
Deschutes Processor
Pentium Pro Processor
Pentium Processor
AMDK6 Processor

VRM Modules

GENERAL DESCRIPTION

The ADP3153 is a highly efficient synchronous switching regu-
lator controller and a linear regulator controller. The switching
regulator controller is optimized for Pentium II and Deschutes
Processor applications where 5 V is stepped down to a digitally
controlled output voltage between 1.8 V and 3.5 V. Using a 5-bit
DAC to read a voltage identification (VID) code directly from
the processor, the ADP3153 uses a current mode constant off-
time architecture to generate its precise output voltage.

The ADP3153 drives two N-channel MOSFETS in a synchro-
nous rectified buck converter, at a maximum switching fre-
quency of 250 kHz. Using the recommended loop compensation
and guidelines, the ADP3153 provides a dc/dc converter that
meets Intel's stringent transient specifications with a minimum
number of output capacitors and smallest footprint. Addition-
ally, the current mode architecture also provides guaranteed
short circuit protection and adjustable current limiting.

The ADP3153's linear regulator controller drives an external
N-channel device. The output voltage is set by the ratio of the
external feedback resistors. The controller has been designed for
excellent load transient response.

+12V

1 F

22 F

150pF

5-BIT CODE

IRL3103

+5V

10BQ015

2.5 H

IRL3103

1.8V3.5V
14A

SENSE

1nF

COMP

DRIVE1

SENSE+

SENSE

DRIVE2

PGND

VID0VID4

AGND

CMP

ADP3153

35k

20k

VLDO

+5V

1000 F

+3.3V

IRL2703

Figure 1. Typical Application

Pentium is a registered trademark of Intel Corporation.
All other trademarks are the property of their respective holders.

REV. 0

ADP3153SPECIFICATIONS

(0 C

+70 C, V

= 12 V, V

= 5 V, unless otherwise noted)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

OUTPUT ACCURACY

1.8 V Output Voltage

With Respect to Nominal

1.0

2.8 V Output Voltage

Output Voltage (Figure 1)

1.0

3.5 V Output Voltage

1.0

OUTPUT VOLTAGE LINE

LOAD

= 10 A (Figure 2)

REGULATION

= 4.75 V to 5.25 V

0.05

OUTPUT VOLTAGE LOAD

(Figure 2)

REGULATION

200 mA < I

LOAD

< 14 A

0.1

INPUT DC SUPPLY CURRENT

Normal Mode

= 0.8 V

4.1

5.5

Shutdown

= +25

C, VSD = 2.0 V

140

250

CURRENT SENSE THRESHOLD

VOLTAGE

Forced to V

OUT

125

145

165

VID PINS THRESHOLD

, V

Low

0.6

High

2.0

VID PINS INPUT CURRENT

VID

= 0 V

110

220

VID0VID4 PULL-UP RESISTANCE

VID

PIN DISCHARGE CURRENT

= +25

OUT

in Regulation

OUT

= 0 V

OFFTIME

OFF

= 150 pF

1.8

2.45

3.2

DRIVER OUTPUT TRANSITION

, t

= 7000 pF (Pins 16, 17)

TIMES

= +25

120

200

POSITIVE POWER GOOD TRIP POINT

PWRGD

% Above Output Voltage

NEGATIVE POWER GOOD TRIP POINT

PWRGD

% Below Output Voltage

POWER GOOD RESPONSE TIME

PWRGD

500

CROWBAR TRIP POINT

CROWBAR

% Above Output Voltage

ERROR AMPLIFIER OUTPUT

IMPEDANCE

ERR

145

ERROR AMPLIFIER

TRANSCONDUCTANCE

ERR

2.2

mmho

ERROR AMPLIFIER MINIMUM

OUTPUT VOLTAGE

CMPMIN

Forced to V

OUT

+ 3%

0.8

ERROR AMPLIFIER MAXIMUM

OUTPUT VOLTAGE

CMPMAX

Forced to V

OUT

2.4

ERROR AMPLIFIER BANDWIDTH 3 dB

ERR

CMP = Open

500

kHz

LINEAR REGULATOR FEEDBACK

CURRENT

0.35

LINEAR REGULATOR OUTPUT

Figure 2

VOLTAGE

PROG

= 35K, R3 = 20K, I

= 1 A

3.24

3.30

3.38

SHUTDOWN (SD) PIN

Low Threshold

Part Active

0.6

High Threshold

Part in Shutdown

2.0

Input Current

NOTES

Dynamic supply current is higher due to the gate charge being delivered to the external MOSFETS.

The LDO is tested in a V

OUT

= 3.3 V configuration with the circuit shown in Figure 2. By selecting a different R

PROG

value, any output voltage above 1.20 V can

be set.

All limits at temperature extremes are guaranteed via correlation using standard quality control methods.
Specifications are subject to change without notice.

ADP3153

REV. 0

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3153 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

PIN FUNCTION DESCRIPTIONS

Pin

Mnemonic

Function

14, 20

VID1VID4,

Voltage Identification DAC Input Pins. These pins are internally pulled up to V

REG

providing a

VID0

logic high if left open. The DAC output range is 600 mV to 1.167 V. Leaving all five DAC
inputs open results in placing the ADP3153 into shutdown.

AGND

Analog Ground Pin. This pin must be routed separately to the () terminal of C

OUT

Shutdown Pin. A logic high will place the ADP3153 in shutdown and disable both outputs. This
pin is internally pulled down.

This pin is the feedback connection for the linear controller. Connect this pin to the resistor
divider network to set the output voltage of the linear regulator.

8, 18

No Connect.

VLDO

Gate Drive for the Linear Regulator N-channel MOSFET.

SENSE

Connects to the internal resistor divider which along with the VID code, sets the output voltage.
Pin 10 is also the () input for the current comparator.

SENSE+

The (+) input for the current comparator. A threshold between Pins 10 and 11 set by the error
amplifier in conjunction with R

SENSE

, sets the current trip point.

External Capacitor C

from Pin 12 to ground sets the off time of the device.

CMP

Error Amplifier Compensation Point. The current comparator threshold increases with the Pin
13 voltage.

PWRGD

Power Good Pin. An open drain signal to indicate that the output voltage is within a

5% regu-

lation band.

Input Voltage Pin.

DRIVE2

Gate Drive for the Synchronous Rectifier N-channel MOSFET. The voltage at Pin 16 swings
from ground to V

DRIVE1

Gate Drive for the buck switch N-channel MOSFET. The voltage at Pin 17 swings from ground
to V

PGND

Driver Power Ground. Connects to the source of the bottom N-channel MOSFET onto the ()
terminal of C

PIN CONFIGURATION

20-Lead Thin Shrink Small Outline (TSSOP)

(RU-20)

TOP VIEW

(Not to Scale)

ADP3153

NC = NO CONNECT

SENSE

VLDO

VID2

VID3

VID4

AGND

SENSE+

CMP

PGND

DRIVE 1

PWRGD

DRIVE 2

VID1

VID0

ABSOLUTE MAXIMUM RATINGS*

Input Supply Voltage (Pin 15) . . . . . . . . . . . . 0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . 0.3 V to +16 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Temperature Range . . . . . . . . . . . . . 0

C to +70

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

C/W

Storage Temperature Range . . . . . . . . . . . . 65

C to +150

Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged.

ORDERING GUIDE

Temperature

Package

Model

Range

Description

Option

ADP3153ARU

C to +70

Thin Shrink Small RU-20
Outline (TSSOP)

ADP3153

REV. 0

SYSTEM

R1
150k

R2
39k

150pF

22 F

1 F

IRL3103

10BQ015

1 F

2700 F 3

(10V)

1.7 H

2.5 H

SENSE

6.7m

2700 F

(10V)

1.8V3.5V
0-14A

RTN

220

100k

+5V

+5V RTN

+12V RTN

2nF
C

COMP

ADP3153

NC = NO CONNECT

SENSE

VLDO

VID2

VID3

VID4

AGND

SENSE+

CMP

PGND

DRIVE1

PWRGD

DRIVE2

VID1

VID0

R3
20k

1000 F

+3.3V

IRL2703

1nF

PROG

35k

RTN

220

+12V

Figure 2. Typical VRM8.2 Compliant Core DC/DC Converter Circuit

NONOVERLAP

DRIVE

CROWBAR

DRIVE1 DRIVE2 PGND

REF

+15%

AGND

PWRGD

SENSE+

DELAY

REF

+5%

REF

5%

SENSE

ADP3153

CMPI

DAC

CMP

1.20V

VID0

VID1

VID2

VID3

VID4

REF

CMPT

SENSE

REFERENCE

OFF-TIME

CONTROL

VLDO

OFF

Figure 3. Functional Block Diagram

OUTPUT CURRENT Amps

EFFICIENCY %

100

1.4

2.8

14.0

4.2

5.6

7.0

9.8 11.2 12.6

8.4

OUT

= +2.0V

OUT

= +2.8V

OUT

= +3.5V

SEE FIGURE 2

Figure 4. Efficiency vs. Output Current

OUT

= +3.5V, I

OUT

= 10A

500ns/DIV

PRIMARY

N-DRIVE

DRIVER OUTPUT

SECONDARY

N-DRIVE

DRIVER OUTPUT

DRIVE 1 AND 2 = 5V/DIV

SEE FIGURE 2

Figure 7. Gate Switching Waveforms

OUTPUT CURRENT
1A TO 14A

OUTPUT VOLTAGE
20mV/DIV

10 s/DIV

Figure 10. Transient Response,
1A14 A of Figure 2 Circuit

Typical Performance CharacteristicsADP3153

REV. 0

TIMING CAPACITOR pF

100

800

200

300

400

500

600

700

FREQUENCY kHz

450

400

200

150

100

350

250

300

Figure 5. Frequency vs. Timing
Capacitor

100ns/DIV

SEE FIGURE 2

= +12V

= +5V

OUT

= +3.5V

OUT

= 10A

Figure 8. Driver Transition Waveforms

10ms/DIV

REGULATOR

OUTPUT VOLTAGE

1V/DIV

VOLTAGE

5V/DIV

Figure 11. Power-On Start-Up
Waveforms

OPERATING FREQUENCY kHz

397

134

GATE CHARGE CURRENT mA

Qn + Qn = 100nC

Figure 6. Gate Charge vs. Supply
Current

10 s/DIV

OUTPUT CURRENT
14A TO 1A

OUTPUT VOLTAGE
20mV/DIV

Figure 9. Transient Response,
14 A1A of Figure 2 Circuit

OUTPUT ACCURACY %

NUMBER OF PARTS

0.55

0.5

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

= +25 C

SEE FIGURE 13

Figure 12. Output Accuracy Distribution

ADP3153

REV. 0

DRIVE1

SENSE+

SENSE

DRIVE2

PGND

VID0
VID4

AGND

CMP

12V

5-BIT

CODE

1 F

4700pF

0.1 F

OUT

1.2V

100k

0.1 F

ADP3153

OP27

Figure 13. Closed-Loop Test Circuit for Accuracy

APPLICATION INFORMATION

The ADP3153 uses a current-mode, constant-off-time control
technique to switch a pair of external N-channel MOSFETs in
a synchronous rectified buck converter application. Due to the
constant-off-time operation, no slope compensation is needed.
A unique feature of the constant-off-time control technique is
that the converter's frequency becomes a function of the ratio of
input voltage to output voltage. The off time is determined by
the value of the external capacitor connected to the C

pin.

The on time varies in such a way that a regulated output volt-
age is maintained.

The output voltage is sensed by an internal voltage divider that
is connected to the SENSE pin. A voltage-error amplifier g

compares the values of the divided output voltage with a refer-
ence voltage. The reference voltage is set by an on-board 5-bit
DAC, which reads the code present at the voltage identification
(VID) pins and converts it to a precise value between 600 mV
and 1.167 V. Refer to Table I for the output voltage vs. VID pin
code information.

During continuous-inductor-current mode of operation, the
voltage-error amplifier g

and the current comparator CMPI

are the main control elements. During the on time of the high
side MOSFET, the current comparator CMPI monitors the
voltage between the SENSE+ and SENSE pins. When the
voltage level between the two pins reaches the threshold level
V

, the high side drive output is switched to zero, which turns

off the high side MOSFET. The timing capacitor C

is now

discharged at a rate determined by the off time controller. In
order to maintain a ripple current in the inductor, which is
independent of the output voltage, the discharge current is
made proportional to the value of the output voltage (mea-
sured at the SENSE pin). While the timing capacitor is dis-
charging, the low side drive output goes high, turning on the
low side MOSFET. When the voltage level on the timing ca-
pacitor has discharged to the threshold voltage level V

comparator CMPT resets the SR flip-flop. The output of the
flip-flop forces the low side drive output to go low and the high
side drive output to go high. As a result, the low side switch is
turned off and the high side switch is turned on. The sequence is
then repeated. As the load current increases, the output voltage
starts to decrease. This causes an increase in the output of the
voltage-error amplifier, which, in turn, leads to an increase in
the current comparator threshold V

T1,

thus tracking the load

current.

Table I. Output Voltage vs. VID Code

VID4

VID3

VID2

VID1

VID0

VOUT

1.80

1.85

1.90

1.95

2.00

2.05

Shutdown

2.10

2.20

2.30

2.40

2.50

2.60

2.70

2.80

2.90

3.00

3.10

3.20

3.30

3.40

3.50

To prevent cross conduction of the external MOSFETs, feed-
back is incorporated to sense the state of the driver output pins.
Before the low side drive output can go high, the high side drive
output must be low. Likewise, the high side drive output is
unable to go high while the low side drive output is high.

Power Good

The ADP3153 has an internal monitor which monitors the
output voltage and drives the PWRGD pin of the device. This
pin is an open drain output whose high level (when connected
to a pull-up resistor) indicates that the output voltage has been
within a

5% regulation band of the targeted value for more

than 500

s. The PWRGD pin will go low if the output is out-

side the regulation band for more than 500

Output Crowbar

An added feature of using an N-channel MOSFET as the syn-
chronous switch is the ability to crowbar the output with the
same MOSFET. If the output voltage is 15% greater than the
desired regulated value, the ADP3153 will turn on the lower
MOSFET, which will current-limit the source power supply or
blow its fuse, pull down the output voltage, and thus save the
expensive microprocessor from destruction. The crowbar func-
tion releases at approximately 50% of the nominal output volt-
age. For example, if the output is programmed to 2.0 V, but is
pulled up to 2.3 V or above, the crowbar will turn on the lower
MOSFET. If in this case the output is pulled down to less than

ADP3153

REV. 0

1.0 V, the crowbar will release, allowing the output voltage to
recover to 2.0 V.

Shutdown

The ADP3153 has a shutdown pin which is pulled logic low by
an internal resistor. In this condition the device functions nor-
mally. This pin should be pulled high externally to disable the
output drives.

Calculation of Component Values

The design parameters for a typical 300 MHz Pentium

II appli-

cation (Figure 2) are as follows:

Input voltage: V

= 5 V

Auxiliary input: V

= 12 V

Output voltage: V

= 2.8 V

Maximum output current:

OMAX

= 14.2 Adc

Minimum output current:

OMIN

= 0.8 Adc

Static tolerance of the supply voltage for the processor core:

OST+

= 100 mV

OST

= 60 mV

Transient tolerance (for less than 2

s) of the supply voltage for

the processor core when the load changes between the minimum
and maximum values with a di/dt of 30 A/

OTR+

= 130 mV

OTR

= 130 mV

Input current di/dt when the load changes between the mini-
mum and maximum values: less than 0.1 A/

The above requirements correspond to Intel's published power
supply requirements based on VRM 8.2 guidelines.

Selection for Operating Frequency

The ADP3153 uses a constant-off-time architecture with t

OFF

determined by an external timing capacitor C

. Each time the

high side N-channel MOSFET switch turns on, the voltage
across C

is reset to approximately 3.3 V. During the off time,

is discharged by a constant current of 65

A to 2.3 V, that is

by 1 V. The value of the off time is calculated from the pre-
ferred continuous-mode operating frequency. Assuming a nomi-
nal operating frequency of f

NOM

= 200 kHz at an output voltage

of V

= 2.8 V, the corresponding off time is:

OFF

NOM

2.2

The timing capacitor can be calculated from the equation:

OFF

143 pF

The converter operates at the nominal operating frequency only
at the above specified V

and at light load. At higher V

, and

heavy load, the operating frequency decreases due to the para-
sitic voltage drops across the power devices. The actual mini-
mum frequency at V

= 2.8 V is calculated to be 160 kHz (see

Equation 1 below), where:

is the input dc current (assuming an efficiency
of 90%, I

= 9 A)

is the resistance of the input filter (estimated
value: 7 m

)

DS(ON)HSF

is the resistance of the high side MOSFET
(estimated value: 10 m

)

DS(ON)LSF

is the resistance of the low side MOSFET
(estimated value: 10 m

)

SENSE

is the resistance of the sense resistor
(estimated value: 7 m

)

is the resistance of the inductor (estimated
value: 6 m

)

Selection--Determining the ESR

The selection of the output capacitor is driven by the required
ESR and capacitance C

. The ESR must be small enough that

both the resistive voltage deviation due to a step change in the
load current and the output ripple voltage stay below the values
defined in the specification of the supplied microprocessor. The
capacitance, C

, must be large enough that the output is held

up while the inductor current ramps up or down to the value
corresponding to the new load current.

The total static tolerance of the Pentium II processor is 160 mV.
Taking into account the

1% setpoint accuracy of the ADP3153,

and assuming a 0.5% (or 14 mV) peak-to-peak ripple, the al-
lowed static voltage deviation of the output voltage when the
load changes between the minimum and maximum values is
0.08 V. Assuming a step change of

I = I

OMAX

OMIN

= 13.4 A,

and allocating all of the total allowed static deviation to the
contribution of the ESR sets the following limit:

E MAX

(

)

ESR

MAX 1

0.08

13. 4

5.9 m

The output filter capacitor must have an ESR of less than
5.9 m

. One can use, for example, six FA type capacitors from

Panasonic, with 2700

F capacitance, 10 V voltage rating, and

34 m

ESR. The six capacitors have a total typical ESR of

~ 5 m

when connected in parallel.

Inductor Selection

The minimum inductor value can be calculated from ESR, off
time, dc output voltage and allowed peak-to-peak ripple voltage.

MIN1

OFF

E( MAX )

RIPPLE , p

2.8

2.2

µ ×

5.9 m

14 m

2.6

The minimum inductance gives a peak-to-peak ripple current of
2.15 A, or 15% of the maximum dc output current I

OMAX

MIN

OFF

OMAX

DS(ON )HSF

SENSE

) V

OMAX

DS(ON )HSF

SENSE

DS(ON )LSF

)

160 kHz

(1)

ADP3153

REV. 0

The inductor peak current in normal operation is:

LPEAK

= I

OMAX

+ I

RPP

/2 = 15.3 A

The inductor valley current is:

LVALLEY

= I

LPEAK

RPP

= 13 A

The inductor for this application should have an inductance
of 2.6

H at full load current and should not saturate at the

worst-case overload or short circuit current at the maximum
specified ambient temperature. A suitable inductor is the
CTX12-13855 from Coiltronics, which is 4.4

H at 1 A and

about 2.5

H at 14.2 A.

Tips for Selecting Inductor Core

Ferrite designs have very low core loss, so the design should
focus on copper loss and on preventing saturation. Molypermalloy,
or MPP, is a low loss core material for toroids, and it yields the
smallest size inductor, but MPP cores are more expensive than
cores or the Kool M

® cores from Magnetics, Inc. The lowest

cost core is made of powdered iron, for example the #52 material
from Micrometals, Inc., but yields the largest size inductor.

Selection--Determining the Capacitance

The minimum capacitance of the output capacitor is determined
from the requirement that the output be held up while the in-
ductor current ramps up (or down) to the new value. The mini-
mum capacitance should produce an initial dv/dt which is equal
(but opposite in sign) to the dv/dt obtained by multiplying the
dt in the inductor and the ESR of the capacitor.

MIN

OMAX

OMIN

(di /dt )

14.2 0.8

5.9 m (2.2 / 4. 4

H )

4.5 mF

In the above equation the value of di/dt is calculated as the
smaller voltage across the inductor (i.e., V

rather than V

)

divided by the maximum inductance (4.4

H) of the CTX12-

13855 inductor from Coiltronics. The parallel-connected six
2700

F/10 V FA series capacitors from Panasonic have a total

capacitance of 16,200

F, so the minimum capacitance is met

with ample margin.

SENSE

The value of R

SENSE

is based on the required output current.

The current comparator of the ADP3153 has a threshold range
that extends from 0 mV to 125 mV (minimum). Note that the
full 125 mV range cannot be used for the maximum specified
nominal current, as headroom is needed for current ripple, tran-
sients and inductor core saturation.

The current comparator threshold sets the peak of the inductor
current yielding a maximum output current I

OMAX,

which equals

the peak value less half of the peak-to-peak ripple current. Solv-
ing for R

SENSE

and allowing a margin for tolerances inside the

ADP3153 and in the external component values yields:

SENSE

= (125 mV )/[1.2(I

OMAX

+ I

RPP

/2)] = 6.8 m

A practical solution is to use three 20 m

resistors in parallel,

with an effective resistance of about 6.7 m

Once R

SENSE

has been chosen, the peak short-circuit current

SC(PK)

can be predicted from the following equation:

SC(PK)

= (145 mV)/R

SENSE

= (145 mV)/(6.7 m

) = 21.5 A

The actual short-circuit current is less than the above calculated
I

SC(PK)

value because the off time rapidly increases when the

output voltage drops below 1 V. The relationship between the
off time and the output voltage is:

OFF

360 k

With a short across the output, the off time will be about
70

s. During that off time the inductor current gradually de-

cays. The amount of decay depends on the L/R time constant in
the output circuit. With an inductance of 2.5

H and total resis-

tance of 23 m

, the time constant will be 108

s, which yields a

valley current of 11.3 A and an average short-circuit current of
about 16.3 A. To safely carry the short-circuit current, the sense
resistor must have a power rating of at least 16.3 A

× 6

.8 m

1.8 W.

Current Transformer Option

An alternative to using low value and high power current sense
resistor is to reduce the sensed current by using a low cost cur-
rent transformer and a diode. The current can then be sensed
with a small-size, low cost SMT resistor. If we use a transformer
with one primary and 50 secondary turns, the worst-case resistor
dissipation is reduced to a fraction of a mW. Another advantage
of using this option is the separation of the current and voltage
sensing, which makes the voltage sensing more accurate.

Power MOSFET

Two external N-channel power MOSFETs must be selected for
use with the ADP3153, one for the main switch, and an identi-
cal one for the synchronous switch. The main selection param-
eters for the power MOSFETs are the threshold voltage V

GS(TH)

and the on resistance R

DS(ON)

The minimum input voltage dictates whether standard threshold
or logic-level threshold MOSFETs must be used. For V

> 8 V,

standard threshold MOSFETs (V

GS(TH)

< 4 V) may be used. If

is expected to drop below 8 V, logic-level threshold MOSFETs

GS(TH)

< 2.5 V) are strongly recommended. Only logic-level

MOSFETs with V

ratings higher than the absolute maximum

of V

should be used.

The maximum output current I

OMAX

determines the R

DS(ON)

requirement for the two power MOSFETs. When the ADP3153
is operating in continuous mode, the simplifying assumption can
be made that one of the two MOSFETs is always conducting
the average load current.

For V

= 5 V and V

= 2.8 V, the maximum duty ratio of the

high side FET is:

MAXHF

= (1 f

MIN

OFF

) =(1 160 kHz

2.2

s) = 65%

The maximum duty ratio of the low side (synchronous rectifier)
FET is:

MAXLF

= 1 D

MAXHF

= 35%

The maximum rms current of the high side FET is:

RMSLS

= [D

MAXHF

LVALLEY

+ I

LPEAK

+ I

LVALLEY

LPEAK

)/3]

0.5

= 11.5 Arms

ADP3153

REV. 0

The maximum rms current of the low side FET is:

RMSLS

= [D

MAXLF

LVALLEY

+ I

LPEAK

+ I

LVALLEY

LPEAK

)/3]

0.5

= 8.41 Arms

The R

DS(ON)

for each FET can be derived from the allowable

dissipation. If we allow 5% of the maximum output power for
FET dissipation, the total dissipation will be:

FETALL

= 0.05 V

OMAX

= 2 W

Allocating two-thirds of the total dissipation for the high side
FET and one-third for the low side FET, the required minimum
FET resistances will be:

DS(ON)HSF(MIN)

= 1.33/11.5

= 10 m

DS(ON)LSF(MIN)

= 0.67/8.41

= 9.5 m

Note that there is a tradeoff between converter efficiency and
cost. Larger FETs reduce the conduction losses and allow higher
efficiency but lead to increased cost. If efficiency is not a major
concern the Fairchild MOSFET NDP6030L or International
Rectifier IRL3103 is an economical choice for both the high side
and low side positions. Those devices have an R

DS(ON)

of 14 m

at V

= 10 V and at 25

C. The low side FET is turned on with

at least 10 V. The high side FET, however, is turned on with
only 12 V 5 V = 7 V. If we check the typical output character-
istics of the device in the data sheet, we find that for an output
current of 10 A, and at a V

of 7 V, the V

is 0.15 V, which

gives a R

DS(ON)

= V

= 15 m

. This value is only slightly

above the one specified at a V

of 10 V, so the resistance in-

crease due to the reduced gate drive can be neglected. We have
to modify, however, the specified R

DS(ON)

at the expected high-

est FET junction temperature of 140

C by a R

DS(ON)

multiplier,

using the graph in the data sheet. In our case:

DS(ON)MULT

= 1.7

Using this multiplier, the expected R

DS(ON)

at 140

C is 1.7

= 24 m

The high side FET dissipation is:

DFETHS

= I

RMSHS

DS(ON)

+ 0.5 V

LPEAK

MAX

= 3.72 W

where the second term represents the turn-off loss of the FET.
(In the second term, Q

is the gate charge to be removed from

the gate for turn-off and I

is the gate current. From the data

sheet, Q

is about 50 nC 70 nC and the gate drive current

provided by the ADP3153 is about 1 A.)

The low side FET dissipation is:

DFETLS

= I

RMSLS

DS(ON)

= 1.7 W

(Note that there are no switching losses in the low side FET.)

To remove the dissipation of the chosen FETs, proper heatsinks
should be used. The Thermalloy 6030 heatsink has a thermal
impedance of 13

C/W with convection cooling. With this heat-

sink, the junction-to-ambient thermal impedance of the chosen
high side FET

JAHS

will be 13 (heatsink-to-ambient) + 2 (junction-

to-case) + 0.5 (case-to-heatsink) = 15.5

C/W.

At full load and at 50

C ambient temperature, the junction

temperature of the high side FET is:

JHSMAX

= T

JAHS

DFETHS

= 105

A smaller heatsink may be used for the low side FET, e.g., the
Thermalloy type 7141 (

= 20.3

C/W). With this heatsink, the

JLSMAX

= T

JALS

DFETLS

= 106

All of the above calculated junction temperatures are safely
below the 175

C maximum specified junction temperature of

the selected FET.

The maximum operating junction temperature of the ADP3153
is calculated as follows:

JICMAX

= T

+ P

)

where

is the junction to ambient thermal impedance of the

ADP3153 and P

is the drive power. From the data sheet,

is equal to 110

C/W and I

= 2.7 mA. P

can be calculated as

follows:

= (C

RSS

+ C

ISS

MAX

= 307 mW

The result is:

JICMAX

= 86

Selection and Input Current di/dt Reduction

In continuous-inductor-current mode, the source current of the
high side MOSFET is a square wave with a duty ratio of V

. To keep the input ripple voltage at a low value, one or

more capacitors with low equivalent series resistance (ESR) and
adequate ripple-current rating must be connected across the
input terminals. The maximum rms current of the input bypass
capacitors is:

CINRMS

)]

0.5

OMAX

= 7 Arms

Let us select the FA-type capacitor with 2700

F capacitance

and 10 V voltage rating. The ESR of that capacitor is 34 m

and the allowed ripple current at 100 kHz is 1.94 A. At 105

we would need to connect at least four such capacitors in paral-
lel to handle the calculated ripple current. At 50

C ambient,

however, the ripple current can be increased, so three capacitors
in parallel are adequate.

The ripple voltage across the three paralleled capacitors is:

CINRPL

= I

OMAX

[ESR

/3 + D

MAXHF

/(3C

MIN

)] 140 mV p-p

To further reduce the effect of the ripple voltage on the system
supply voltage bus and to reduce the input-current di/dt to
below the recommended maximum of 0.1 A/

s, an additional

small inductor (L > 1.7

H @ 10 A) should be inserted between

the converter and the supply bus (see Figure 2).

Feedback Loop Compensation Design

To keep the peak-to-peak output voltage deviation as small as
possible, the low frequency output impedance (i.e., the output
resistance) of the converter should be made equal to the ESR of
the output capacitor. That can be achieved by having a single-pole
roll-off of the voltage gain of the g

error amplifier, where the pole

frequency coincides with the ESR zero of the output capacitor. A
gain with single-pole roll-off requires that the g

amplifier is termi-

nated by the parallel combination of a resistor and capacitor. The
required resistor value can be calculated from the equation:

SENSE

145 k

COMP

(

)

where g

= 2.2 ms and the quantities 36 and 145 k

are charac-

teristic of the ADP3153. The calculated compensating resis-
tance is:

R1 R2 = R

COMP

= 31 k

ADP3153

REV. 0

The compensating capacitance is determined from the equality
of the pole frequency of the error amplifier gain and the zero
frequency of the impedance of the output capacitor.

R C

COMP

OUT

COMP

16 2

2 6

In the application circuit we tested, we found that the compen-
sation scheme shown in Figure 2 gave the optimal response to
meet the Pentium II dc/dc static and transient specifications
with sufficient margins including the ADP3153's initial error
tolerance, the PCB layout trace resistances, and the external
component parasitics. If we increase the load resistance to the
COMP pin, the static regulation will improve. The load transient
response, however, will get worse. In Figure 2, if we decrease the
R1 = 150 k

resistor vs. the R2 = 39 k

resistor, the regulation

band will shift positive in relation to the 2.8 V. If we increase
the R1 resistor, the regulation band will shift negative. It may be
necessary to adjust these resistor values to obtain the best static
and dynamic regulation compliance depending on the output
capacitor ESR and the parasitic trace resistances of the PCB
layout. A detailed design procedure and published conference
papers on the optimal compensation are available on ADI's
website (http://www.analog.com).

ADP3153 Linear Regulator

The ADP3153 linear regulator provides a low cost, convenient,
and versatile solution for generating an additional power supply
rail that can be programmed between 1.2 V5 V. The maximum
output load current is determined by the size and thermal imped-
ance of an external N-channel power MOSFET that is placed in
series with the 5 V supply and controlled by the ADP3153. The
output voltage, V

in Figure 14, is sensed at the FB pin of the

ADP3153 and compared to an internal 1.2 V reference in a
negative feedback loop which keeps the output voltage in regula-
tion. Thus, if the load is being reduced or increased, the FET
drive will also be reduced or increased by the ADP3153 to pro-
vide a well regulated

1% accurate output voltage. This accu-

racy is maintained even if the load changes at the very high rate
typical of CPU-type loads. The output voltage is programmed
by adjusting the value of the external resistor R

PROG

shown in

Figure 14.

Features

· Typical Efficiency: 66% at 3.3 V Output Voltage

· Tight DC Regulation Due to 1% Reference and High Gain

· Output Voltage Stays Within Specified Limits at Load Cur-

rent Step with 30 A/

s Slope

· Fast Response to Input Voltage or Load Current Transients

The design in Figure 14 is for an output voltage, V

of 3.3 V

with a maximum load current of 0.5 A. Additionally, overcurrent
protection is provided by the addition of an external NPN tran-
sistor and an external resistor R

. The design specifications and

procedure is given below.

Linear Regulator Design Specifications

Maximum Ambient Temperature . . . . . . . . . . . T

AMB

= 50

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

= 5 V

Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V

= 3.3 V

Maximum Output Current . . . . . . . . . . . . . . . I

O2MAX

= 0.5 A

Maximum Output Load Transient Allowed . . V

TR2

= 0.036 V

Chosen FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRX3803
Junction-to-Ambient Thermal Impedance (FET)*

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

C/W

*Uses 1 inch square PCB cu-foil as heatsink

The output voltage may be programmed by the resistor R

PROG

as follows:

PROG

1 2

3 3

1 2

The current sense resistor may be calculated as follows:

O MAX

0 6

0 5

1 2

The power rating is:

O MAX

1 1

0 36

(

)

Use a 0.5

resistor.

The maximum FET junction temperature at shorted output is:

FETMAX

AMB

O MAX

× ×

1 1

50 40 5 0 5 1 1 160

which is within the maximum allowed by the FET's data sheet.

The maximum FET junction temperature at nominal output is:

FETMAX

AMB

O MAX

(

)

(

)

= °

50 40

5 3 3

0 5 84

The output filter capacitor maximum allowed ESR is:

ESR ~ V

TR2

OMAX

= 0.036/0.5 = 0.072

This requirement is met using a 1000

F/10 V LXV series ca-

pacitor from United Chemicon. For applications requiring
higher output current, a heatsink and/or a larger MOSFET
should be used to reduce the MOSFET's junction to ambient
thermal impedance.

1.1

470pF

2N2222

= +5V

IRX3803

1000 F/10V

= 3.3V

= 0.5A

VLDO

ADP3153

20k

PROG

35k

Figure 14. Linear Regulator with Overcurrent Protection

ADP3153

REV. 0

BOARD LAYOUT

A multilayer PCB is recommended with a minimum of two
copper layers. One layer on top should be used for traces inter-
connecting low power SMT components. The ground terminals
of those components should be connected with vias to the bot-
tom traces connecting directly to the ADP3153 ground pins.
One layer should be a power ground plane. If four layers are
possible, one additional layer should be an internal system
ground plane, and one additional layer can be used for other
system interconnections.

When laying out the printed circuit board, the following check-
list should be used to ensure proper operation of the ADP3153.

Board Layout Guidelines

1. The power loop should be routed on the PCB to encompass

small areas to minimize radiated switching noise energy to
the control circuit and thus to avoid circuit problems caused
by noise. This technique also helps to reduce radiated EMI.
The power loop includes the input capacitors, the two
MOSFETs, the sense resistor, the inductor and the output
capacitors. The ground terminals of the input capacitors,
the low side FET, the ADP3153 and the output capacitors
should be connected together with short and wide traces. It is
best to use an internal ground plane.

2. The PGND (power ground) pin of the ADP3153 must re-

turn to the grounded terminals of the input and output ca-
pacitors and to the source of the low side MOSFET with the
shortest and widest traces possible. The AGND (analog
ground) pin has to be connected to the ground terminals of
the timing capacitor and the compensating capacitor, again
with the shortest leads possible, and before it is connected to
the PGND pin.

3. The positive terminal of the input capacitors must be con-

nected to the drain of the high side MOSFET. The source
terminal of this FET is connected to the drain of the low side
FET, (whose source is connected to the ground plane direct)
with the widest and shortest traces possible. To kill parasitic
ringing at the input of the buck inductor due to parasitic
capacitances and inductances, a small (L > 3 mm) ferrite
bead is recommended to be placed in the drain lead of the
low side FET. Also, to minimize dissipation of the high side
FET, a low voltage 1 A Schottky diode can be connected
between the input of the buck inductor and the source of the
low side FET.

4. The positive terminal of the bypass capacitors of the +12 V

supply must be connected to the V

pin of the ADP3153

with the shortest leads possible. The negative terminals must
be connected to the PGND pin of the ADP3153.

5. The sense pins of the ADP3153 must be connected to the

sense resistor with as short traces as possible. Make sure that
the two sense traces are routed together with minimum sepa-
ration (<1 mm). The output side of the sense resistor should
be connected to the V

pin(s) of the CPU with as short and

wide PCB traces as possible to reduce the V

voltage drop.

(Each square unit of 1 ounce Cu-trace has a resistance of
~0.53 m

. At 14 A, each m

of PCB trace resistance be-

tween current sense resistor output and V

terminal(s) of

the CPU will reduce the regulated output voltage by 14 mV.
The filter capacitors to ground at the sense terminals of the
IC should be as close as possible (<8 mm) to the ADP3153.
The common ground of the optional filter capacitors should
be connected to the AGND pin of the ADP3153 with the
shortest traces possible (<10 mm).

6. The microprocessor load should be connected to the output

terminals of the converter with the widest and shortest traces
possible. Use overlapping traces in different layers to mini-
mize interconnection inductance.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADP3153

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADP3153