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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

ADP3410

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

Dual MOSFET Driver

with Bootstrapping

FEATURES
All-In-One Synchronous Buck Driver
One PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Programmable Transition Delay
Synchronous Override Control
Undervoltage Lockout
Programmable Overvoltage Shutdown
V

Good Signal Drives Auxiliary Circuits

Shutdown Quiescent Current < 10 A

APPLICATIONS
Mobile Computing CPU Core Power Converters
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations

GENERAL DESCRIPTION

The ADP3410 is a dual MOSFET driver optimized for driving
two N-channel FETs that are the two switches in the non-
isolated synchronous buck power converter topology. Each of
the drivers is capable of driving a 3000 pF load with a 20 ns
propagation delay and a 30 ns transition time. One of the drivers
can be bootstrapped, and is designed to handle the high-voltage
slew rate associated with "floating" high-side gate drivers. The
ADP3410 has several protection features: overlapping drive
prevention (ODP), undervoltage lockout (UVLO) with perform-
ance specified at very low VCC levels, and overvoltage protection
(OVP) that can be used to monitor either the input or output.
Additional features include: programmable transition delay, a
synchronous drive override control pin, a synchronous drive
status monitor and, in conjunction with exiting from the UVLO
mode, a V

Good (VCCGD) signal capable of driving a 10 mA

load. The quiescent current, when the device is disabled, is less
than 10

GND

PGND

DRVLSD

SRMON

OVPSET

DLY

VCC

VCCGD

BST

DRVH

DRVL

ADP3410

TO PWM

CONTROLLER

BATT

OUT

Figure 1. Typical Application Circuit

FUNCTIONAL BLOCK DIAGRAM

CONTROL

AND

OVERLAP

PROTECTION

CIRCUIT

ADP3410

4.4V

1.2V

VCC

VCCGD

GND

DLY

OVPSET

DRVLSD

PGND

BST

DRVH

DRVL

SRMON

REV. 0

ADP3410SPECIFICATIONS

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

SUPPLY

Supply Voltage Range

4.15

5.0

6.0

Quiescent Current

CCQ

Shutdown Mode

< 0.8 V

Operating Mode

> 2.0 V, No Switching

VCCGD OUTPUT

Output Voltage High

= 4.6 V, I

LOAD

= 10 mA

4.5

4.55

Output Voltage Low

< UVLO, I

LOAD

= 10

0.1

0.2

VCCGD Propagation Delay

2, 3

tpdh

VCCGD

SD Goes High

(See Figure 4)

tpdl

VCCGD

SD Goes Low

SYNCHRONOUS RECTIFIER

MONITOR
Output Voltage High

4.15

Output Voltage Low

= 4.6 V, C

LOAD

= 100 pF

Transition Time

SRMON

= 4.6 V, C

LOAD

= 100 pF

Propagation Delay

2, 3

tpdh

SRMON

DRVLSD Is High and

DRVL Goes High, or
DRVLSD Goes Low

tpdl

SRMON

DRVLSD Is High and

DRVL Goes Low

UNDERVOLTAGE LOCKOUT

UVLO Threshold

4.2

4.4

4.6

UVLO Hysteresis

0.05

UVLO Logic Active Threshold

1.5

UVLO

2, 3

Propagation Delay

tpdh

UVLO

Goes High

(See Figure 5)

tpdl

UVLO

Goes Low

OVERVOLTAGE PROTECTION

Trip Threshold

1.145 1.2

1.255

Hysteresis

0.8

Bias Current

0.2

1.0

OVP

2, 3, 4

Propagation Delay

tpdh

OVP

= 4.6 V, OVPSET Goes High

0.5

SYNCHRONOUS RECTIFIER ENABLE

DRVLSD
Input Voltage High

2.0

Input Voltage Low

0.8

Propagation Delay

2, 3

tpdl

DRVLSD

= 4.6 V,

(See Figure 3)

tpdh

DRVLSD

LOAD (DRVL)

= 3 nF

SD INPUT

Input Voltage High

2.0

Input Voltage Low

0.8

PWM INPUT (IN)

Input Voltage High

2.0

Input Voltage Low

0.8

THERMAL SHUTDOWN

Overtemperature Trip Point

165

OTP Hysteresis

HIGH-SIDE DRIVER

Output Resistance, Sourcing Current

BST

= 4.6 V

2.5

Output Resistance, Sinking Current

BST

= 4.6 V

2.5

DRVH Transition Times

DRVH

BST

= 4.6 V, C

LOAD

= 3 nF

(See Figure 6)

DRVH

DRVH Propagation Delay

2, 3

tpdh

DRVH

BST

= 4.6 V

Note 6

(See Figure 6)

tpdl

DRVH

= 0 C to 85 C, V

= 5 V, VBST = 4 V to 26 V,

SD > 2 V, unless otherwise

noted)

REV. 0

ADP3410

Parameter

Symbol

Conditions

Min

Typ Max

Unit

LOW-SIDE DRIVER

Output Resistance, Sourcing Current

= 4.6 V

2.5

Output Resistance, Sinking Current

= 4.6 V

2.5

DRVL Transition Times

DRVL,

= 4.6 V, C

LOAD

= 3 nF

(See Figure 6)

DRVL

DRVL Propagation Delay

2, 3

tpdh

DRVL

= 4.6 V

(See Figure 6)

tpdl

DRVL

NOTES

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

AC specifications are guaranteed by characterization, but not production tested.

For propagation delays, tpdh refers to the specified signal going high, tpdl refers to it going low.

Propagation delay measured until DRVL begins its transition.

Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 mA).

Maximum propagation delay = 40 ns max + (1 ns/pF

DLY

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

VCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
BST to PGND . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
SW to PGND . . . . . . . . . . . . . . . . . . . . . . . . 2.0 V to +25 V
OVPSET to PGND . . . . . . . . . . . . . . . . . . . . 0.3 V to +10 V
SD, IN, DRVLSD to GND . . . . . . . . . . . . . . 0.3 V to +7.3 V
GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0.3 V

Operating Ambient Temperature Range . . . . . . . 0

C to 85

Operating Junction Temperature Range . . . . . . 0

C to 125

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

C/W

Storage Temperature Range . . . . . . . . . . . . 65

C to +150

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3410 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

Model

Temperature

Package

Range

Description

Option

ADP3410KRU

C to 85

Thin Shrink Small RU-14
Outline Package
(TSSOP-14)

REV. 0

ADP3410

PIN FUNCTION DESCRIPTIONS

Pin

Mnemonic

Function

OVPSET

Overvoltage Shutdown Sense Input. Shutdown occurs when this pin is driven above the specified thresh-
old. It is a high-impedance comparator input, so an external resistor divider can be used to scale the
controlling voltage for OVP.

Shutdown. When high, this pin enables normal operation. When low, VCCGD, DRVH, and DRVL are
forced low and the supply current (ICC

) is minimized as specified.

GND

Signal Ground. The input signal and the capacitor at DLY should be closely referenced to this ground.

TTL-level input signal which has primary control of the drive outputs.

DRVLSD

Synchronous Rectifier Enable. When low, this signal forces DRVL low. The propagation delay time is on
the order of that for the main input signal, so it can be used for real time modulation control of DRVL.
When

DRVLSD is high, DRVL is enabled and controlled by IN.

DLY

Low-High-Transition Delay. A capacitor from this pin to ground programs the propagation delay
from turn-off of the lower FET to turn-on of the upper FET. The formula for the low-high-transition
delay is DLY = C

DLY

(1 ns/pF) + 20 ns. The rise time for turn-on of the upper FET is not included in

the formula.

VCCGD

Good. This pin indicates the status of the undervoltage lockout. When V

is high enough for the

device to exit UVLO mode, the VCCGD pin is pulled up to V

with the specified low impedance. This

signal is capable of acting as a switched power rail for external circuitry, since it can source 10 mA and
sink 10

VCC

Input Supply. This pin should be bypassed to PGND with ~1

F ceramic capacitor.

DRVL

Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) FET.

PGND

Power Ground. Should be closely connected to the source of the lower FET.

SRMON

Synchronous Rectifier Monitor. When

DRVLSD is high, SRMON follows DRVL. When DRVLSD is

low, SRMON is high. TTL-type output.

This pin is connected to the buck switching node, close to the upper FET's source. It is the floating return
for the upper FET drive signal. Also, it is used to monitor the switched voltage to prevent turn-on of the
lower FET until the voltage is below ~1 V. Thus, the high-low-transition delay is determined at this pin
according to operating conditions. This pin can be subjected to voltages as low as 2 V below PGND.

DRVH

Buck Drive. Output drive for the upper (buck) FET.

BST

Floating Bootstrap Supply for the upper FET. A capacitor connected between BST and SW pins holds
this bootstrapped voltage for the high-side FET as it is switched. The capacitor should be chosen between
0.1

F and 1

PIN CONFIGURATION

OVPSET

GND

DRVLSD

DLY

VCCGD

BST
DRVH
SW
SRMON
PGND
DRVL
VCC

1
2
3
4
5
6
7

14
13
12
11
10

9
8

ADP3410

REV. 0

DRVH

DRVL

= 5V

LOAD

= 3nF

= 0V

VOLTAGE

TIME ns

20ns/DIV

2V/DIV

Figure 7. DRVH Fall and DRVL Rise
Times

AMBIENT TEMPERATURE C

TIME ns

RISE TIME

FALL TIME

= 5V

LOAD

= 3nF

Figure 10. DRVL Rise and Fall Times
vs. Temperature

JUNCTION TEMPERATURE C

TIME ns

tpdl

DRVH

= 5V

LOAD

= 3nF

tpdl

DRVL

100

125

Figure 13. Propagation Delay vs.
Temperature

DRVL

DRVH

= 5V

LOAD

= 3nF

DLY

= 20pF

VOLTAGE

TIME ns

20ns/DIV

2V/DIV

Figure 8. DRVL Fall and DRVH Rise
Times

CAPACITANCE nF

TIME ns

= 5V

= 25 C

DRVH

DRVL

Figure 11. DRVH and DRVL Rise
Times vs. Load Capacitance

IN FREQUENCY kHz

SUPPLY CURRENT mA

1200

200

400

600

800

1000

= 5V

= 25 C

LOAD

= 3nF

Figure 14. Supply Current vs.
Frequency

JUNCTION TEMPERATURE C

TIME ns

RISE TIME

FALL TIME

= 5V

LOAD

= 3nF

Figure 9. DRVH Rise and Fall Times
vs. Temperature

CAPACITANCE nF

TIME ns

= 5V

= 25 C

DRVH

DRVL

Figure 12. DRVH and DRVL Fall Times
vs. Load Capacitance

JUNCTION TEMPERATURE C

11.0

10.5

9.0

125

SUPPLY CURRENT mA

100

10.0

9.5

= 5V

= 250kHz

LOAD

= 3nF

Figure 15. Supply Current vs.
Temperature

Typical Performance CharacteristicsADP3410

REV. 0

ADP3410

THEORY OF OPERATION

The ADP3410 is a dual MOSFET driver optimized for driving
two N-channel FETs in a synchronous buck converter topology.
A single PWM input signal is all that is required to properly
drive the high-side and the low-side FETs. Each driver is
capable of driving a 3 nF load with only a 20 ns transition time.

A more detailed description of the ADP3410 and its features
follows. Refer to the functional block diagram.

Low-Side Driver

The low-side driver is designed to drive low-R

DS(ON)

N-channel

MOSFETs. The maximum output resistance for the driver is
5

s for both sourcing and sinking gate current. The low-output

resistance allows the driver to have 20 ns rise and fall times into
a 3 nF load. The bias to the low-side driver is internally con-
nected to the VCC supply and PGND.

When the driver is enabled, the driver's output is 180

out of

phase with the PWM input. When the driver is shut down or the
entire ADP3410 is in shutdown or in under voltage lockout, the
low-side gate is held low.

High-Side Driver

The high-side driver is designed to drive a floating low R

DS(ON)

N-channel MOSFET. The maximum output resistance for the
driver is 5

s for both sourcing and sinking gate current. The

low output resistance allows the driver to have 20 ns rise and fall
times into a 3 nF load. The bias voltage for the high-side driver
is developed by an external bootstrap supply circuit, which is
connected between the BST and SW pins.

The bootstrap circuit comprises a Schottky diode, D1, and
bootstrap capacitor, C

BST

. When the ADP3410 is starting up,

the SW pin is at ground, so the bootstrap capacitor will charge
up to VCC

through D1. As the input voltage ramps up and

exceeds the UVLO threshold, the high-side driver is enabled.
When the PWM input goes high, the high-side driver will begin
to turn the high-side FET, Q1, ON by pulling charge out of
C

BST

. As Q1 turns ON, the SW pin will rise up to V

BATT

forcing the BST pin to V

BATT

+ V

C(BST)

, which is enough gate-

to-source voltage to hold Q1 ON. To complete the cycle, Q1 is
switched OFF by pulling the gate down to the voltage at the
SW pin. When the low-side FET, Q2, turns ON, the SW pin is
pulled to ground. This allows the bootstrap capacitor to charge
up to VCC

again.

The high-side driver's output is in phase with the PWM input.
When the driver is in under-voltage lockout, the high-side gate
is held low.

Overlap Protection Circuit

The Overlap Protection Circuit (OPC) prevents both of the
main power switches, Q1 and Q2, from being ON at the same
time. This is done to prevent shoot-through currents from
flowing through both power switches and the associated losses
that can occur during their ON-OFF transitions. The overlap
protection circuit accomplishes this by adaptively controlling the
delay from Q1's turn OFF to Q2's turn ON, and by program-
ming the delay from Q2's turn OFF to Q1's turn ON.

To prevent the overlap of the gate drives during Q1's turn OFF
and Q2's turn ON, the overlap circuit monitors the voltage at
the SW pin. When the PWM input signal goes low, Q1 will
begin to turn OFF (after a propagation delay), but before Q2
can turn ON, the overlap protection circuit waits for the voltage
at the SW pin to fall from V

BATT

to 1 V. Once the voltage on the

SW pin has fallen to 1 V, Q2 will begin turn ON. By waiting for
the voltage on the SW pin to reach 1 V, the overlap protection
circuit ensures that Q1 is OFF before Q2 turns on, regardless of
variations in temperature, supply voltage, gate charge, and drive
current.

To prevent the overlap of the gate drives during Q2's turn OFF
and Q1's turn ON, the overlap circuit provides a programmable
delay that is set by a capacitor on the DLY pin. When the PWM
input signal goes high, Q2 will begin to turn OFF (after a propa-
gation delay), but before Q1 can turn ON, the overlap protection
circuit waits for the voltage at DRVL to drop to around 10% of
VCC. Once the voltage at DRVL has reached the 10% point,
the overlap protection circuit will wait for a 20 ns typical propa-
gation delay plus an additional delay based on the external
capacitor, C

DLY

. The delay capacitor adds an additional 1 ns/pF

of delay. Once the programmable delay period has expired, Q1
will begin turn ON. The delay allows time for current to com-
mutate from the body diode of Q2 to an external Schottky
diode, which allows turn-off losses to be reduced. Although not
as foolproof as the adaptive delay, the programmable delay adds
a safety margin to account for variations in size, gate charge, and
internal delay of the external power MOSFETs.

Overvoltage Protection

An overvoltage protection circuit monitors the output voltage
for an overvoltage condition. This condition is possible if Q1
should fail. If this should occur, the output voltage would begin
to rise up to the battery voltage where it would pose the threat
of damage to the devices connected to the output. By adding a
resistor divider, Ra and Rb, to the OVPSET pin, the output
voltage can be monitored for this fault condition.

If the voltage on the OVPSET pin exceeds the 1.2 V threshold,
this indicates a fault condition and Q1 is turned OFF and the
low-side FET (synchronous rectifier) is turned ON. The power
switches will remain in this state until the voltage on the
OVPSET pin falls below 400 mV. The turn-on of Q2 is not
delayed by monitoring the SW voltage, but the triggering of
OVP is intentionally slow to avoid false triggering.

Low-Side Driver Enable

The low-side driver enable (

DRVLSD) allows external control

of the synchronous rectifier. This is particularly useful for main-
taining efficiency under light load conditions. At light loads, the
PWM duty cycle becomes small, meaning the high-side switch is
ON for a very short time and the synchronous rectifier is ON for
the remainder of the period. Under these conditions, the induc-
tor current ramps up during the short high-side switch ON time,
and then ramps down during the synchronous rectifier's ON
time. If the inductor current reaches zero and there is still time
left in the period, the inductor current will begin to go negative.
Negative current indicates that current is being drawn out of the
output capacitor through the inductor and low-side FET to
ground, incurring extra losses in the process. If the

DRVLSD is

used to shut down the low-side driver when the inductor
current reaches zero, the light load efficiency can be dramatically
improved. If inductor current information is not available, but
a microprocessor is performing a power management function,
it can shut down the synchronous rectifier when in a sleep or
stand-by mode.

When the

DRVLSD input is low, the low-side driver output

goes low. When the

DRVLSD input is high the low-side driver

is enabled and controlled by the PWM input. The propagation

REV. 0

ADP3410

delay from the

DRVLSD input to the DRVL output is about

30 ns.

Synchronous Rectifier Monitor

The synchronous rectifier monitor provides a TTL output signal
for use by the PWM controller. The SRMON output follows the
DRVL signal when the low-side driver is enabled and goes high
when the low-side driver is shut down.

Shutdown

The shutdown input is used for power management. If the cir-
cuits running off of the buck converter are not needed, the
ADP3410 can be shut down to conserve power.

When the

SD pin is high, the ADP3410 is enabled for normal

operation. Pulling the

SD pin low forces the VCCGD, DRVH

and DRVL outputs low turning the buck converter OFF and
reducing the VCC

supply current to less than 10

Undervoltage Lockout

The undervoltage lockout (UVLO) circuit holds both FET
driver outputs low during VCC

supply ramp up. The UVLO

logic becomes active and in control of the driver outputs at a
supply voltage of 1.5 V. The UVLO circuit will wait until the
VCC

supply has reached a voltage high enough to bias logic

level FETs fully ON, around 4.4 V, before releasing control
of the drivers to the PWM input.

VCC Good

The power ready signal, VCCGD, indicates the status of the
VCC

supply. When the device is in UVLO, the VCCGD output

is pulled low by an NMOS transistor. Upon exiting UVLO mode,
the VCCGD pin is pulled up to VCC

with a 5

PMOS transis-

tor capable of sourcing current to external load circuits. As can
be seen from the block diagram, the UVLO comparator output
and the

SD signal are ANDed together to become the VCCGD

output, so when the device is put into shutdown the VCCGD
output will be low regardless of the VCC voltage.

Thermal Shutdown

The thermal shutdown circuit protects the ADP3410 against
damage due to excessive power dissipation. Under extreme
conditions, high ambient temperature and high-power dissipation,
the die temperature can rise up to the over-temperature trip
point of 165

C. If the die temperature exceeds 165

C, the

thermal shutdown circuit will turn the output drivers OFF. The
drivers will remain disabled until the junction temperature has
decreased by 10

C, at which point the drivers are enabled again.

APPLICATION INFORMATION
Supply Capacitor Selection

For the supply input (VCC) of the ADP3410, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents drawn. Use a 5

F to 10

F, low ESR

capacitor. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size and can be
obtained from the following vendors:

Murata

GRM235Y5V106Z16 http://www.murata.com

Taiyo-Yuden EMK325F106ZF

http://www.t-yuden.com

Tokin

C23Y5V1C106ZP

http://www.tokin.com

A lower cost alternative may be to use a 5

F to 10

F tantalum

capacitor with a small (1

F) ceramic in parallel. Keep the

ceramic capacitor as close as possible to the ADP3410.

Bootstrap Circuit

The bootstrap circuit requires a charge storage capacitor, C

BST

and a Schottky diode, D1, as shown in Figure 2. Selecting these
components can be done after the high-side FET has been chosen.

The bootstrap capacitor must have a voltage rating that is able
to handle the maximum battery voltage plus 5 V. A minimum
50 V rating is recommended. The capacitance is determined
using the following equation:

BST

GATE

BST

(1)

where Q

GATE

is the total gate charge of the high-side FET, and

BST

is the voltage droop allowed on the high-side FET drive.

For example, the IRF7811 has a total gate charge of about
20 nC. For an allowed droop of 200 mV, the required bootstrap
capacitance is 100 nF. Look for a good quality ceramic capacitor.

A Schottky diode is recommended for the bootstrap diode due
to its low forward drop, which maximizes the drive available for
the high-side FET. The bootstrap diode must have a minimum
40 V rating to withstand the maximum battery voltage plus 5 V.
The average forward current can be estimated by:

F AVG

GATE

MAX

(

)

(2)

where f

MAX

is the maximum switching frequency of the controller.

The peak surge current rating should be checked in circuit since
this is dependent on the source impedance of the 5 V supply,
and the ESR of C

BST

Setting the OVP Threshold

The ADP3410 can shut down the high-side FET drive when the
OVPSET input exceeds the threshold voltage. The voltage at
which V

OUT

trips the overvoltage protection is set by selecting

the values for Ra and Rb shown in Figure 2. The threshold for
the OVP is calculated using:

OVP

1 2

(3)

where V

OVP

is the desired OVP threshold voltage at V

OUT

In order to minimize the bias current error, Rb should be less
than or equal to 24 k

. By selecting a value for Rb

24 k

and

solving for Ra gives the following formula:

OVP

1 2

(4)

Note that the minimum the OVP threshold can be is 1.2 V when
Ra is zero.

Delay Capacitor Selection

The delay capacitor, C

DLY

, is used to add an additional delay

when the low-side FET drive turns off and when the high-side
drive starts to turn on. The delay capacitor adds 1 ns/pF of
additional time to the 20 ns of fixed delay.

If a delay capacitor is required, a good quality ceramic capacitor
with an NPO or COG dielectric or a good quality mica capacitor
should be used. Both types of capacitors are available in the
1 pF to 100 pF range and have excellent temperature and
leakage characteristics.

REV. 0

ADP3410

Printed Circuit Board Layout Considerations

Use the following general guidelines when designing printed
circuit boards:

1. Trace out the high-current paths and use short, wide traces

to make these connections.

2. Split the ground connections. Use separate planes for the

signal and power grounds, and tie them together at a single
point near the ADP3410.

3. The VCC

bypass capacitor should be located as close as

possible to VCC

and PGND pins.

Typical Application Circuit

The circuit in Figure 16 shows how the ADP3410 can be com-
bined with the ADP3421 to form a total power conversion solution
for a microprocessor. The combination provides the supply
voltages for the core processor, the I/O interface, and the clock.

VHYS

ADP3421

CLSET

LTO

LTI

LTB

VID4

VID3

VID2

VID1

VID0

CLKDRV

CLKFB

IODRV

IOFB

PWRGD 16

UVLO 17

SSL 18

SSC 19

CORE 20

DACOUT 21

GND 22

OUT 23

VCC 24

RAMP 25

REG 26

CS+ 27

CS 28

51.1k

160k

3.3V

R10

10k

100nF

C3
68 F

VRON

2N3906

C14
100 F

M1
IRF7811

D2
10BQ040

OVPSET

ADP3410

GND

DRVLSD

DLY

VCCGD

VCC

DRVL

PGND

SRMON

DRVH

BST

C20
10 F

Q1
MJD210

FROM

CPU

R11
220k

R12

470k

C22
1nF

C21
1.5nF

C1
100nF

C31

1pF

R16

3.3k

C41
1pF

C29
100pF

R17
75k

7.5k

10k

R18

576k

C23
1nF

C25

22nF

R21, 10k

R19
2k

R15

332

R22

100k

C18

10pF

C28

10 F

C17
100nF

IRF7811

2.2

R9
2.2

IRF7811

VIN

1 H

D1
10BQ040

C32

15nF

C10

10 F

C15

10 F

C16

10 F

C4C6,

C11, C12,

C26, C27

220 F 7

VCC ON CORE SENSE

V GATE

VCC CPU IO

VCC CPU CLK

VCC
CPU

CORE

GND

R20
10

Figure 16. Typical Application Circuit

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADP3410

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADP3410