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REV. A
Information furnished by Analog Devices is believed to be accurate and
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use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADP3610
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
320 mA Switched Capacitor
Voltage Doubler
FEATURES
Push-Pull Charge Pump Doubler Reduces Output Ripple
+3.0 V to +3.6 V Operation
V
OUT
> +5.4 V @ 320 mA Maximum Load
Output Impedance, R
TOTAL
1.66
Shutdown Capability
Overvoltage Protection: V
IN
> +4 V
Operating Temperature Range: 20 C to +85 C
Thermally Enhanced 16-Lead TSSOP Package
APPLICATIONS
High Current Doublers
LCD Panels
Cellular Phones
Inductorless Boost Converters
GENERAL DESCRIPTION
The ADP3610 is a push-pull switched-capacitor converter volt-
age doubler. The term "push-pull" refers to two charge pumps
working in parallel and in opposing phase to deliver charge to
support the output voltage. When one capacitor is pumping
charge to the output, the other is recharging. This technique
minimizes voltage loss and output voltage ripple.
The converter accommodates input voltages from +3 V to
+3.6 V and can provide 320 mA using 2.2
F MLCC pump
capacitors. Converter operation can be enabled or disabled
simply by an input signal. The package is enhanced with Analog
Devices' proprietary Thermal Coastline feature, which allows
up to 980 mW of power dissipation at room temperature. The
exceptionally thin TSSOP-16 package and the requirement of
only capacitors (no inductors) to support the converter opera-
tion allows slim designs, e.g., for TFT or LCD display panels.
C
IN
1 F
CP2
2.2 F
CP1
2.2 F
V
IN
V
OUT
SD
V
OUT
V
IN
GND
ADP3610
C
O
1 F
Figure 1. Typical Application Circuit
FUNCTIONAL BLOCK DIAGRAM
1MHz
OSC
V
IN
OVER-
VOLTAGE
PROTECTION
SD
GND
V
OUT
CM2
CP2
CM1
CP1
DRV
DRIVE LOGIC
DRV
ADP3610
REV. A
2
ADP3610SPECIFICATIONS
Parameter
Symbol
Condition
Min
Typ
Max
Units
OPERATING SUPPLY RANGE
V
IN
3.0
3.6
V
QUIESCENT CURRENT
I
Q
SD = V
IN
0.3
A
SD = GND, I
L
= 0 mA
8.6
10
mA
INPUT OVP THRESHOLD
V
OVP
4
V
TOTAL OUTPUT IMPEDANCE
R
TOTAL
4
I
O
= 0 mA to 320 mA
1
1.66
OUTPUT VOLTAGE
V
O
I
O
= 240 mA, V
IN
= +3 V
5.6
5.75
V
I
O
= 320 mA, V
IN
= +3 V
5.47
5.65
V
I
O
= 240 mA, V
IN
= +3.3 V
6.2
6.35
V
I
O
= 320 mA, V
IN
= +3.3 V
6.07
6.27
V
OUTPUT CURRENT
I
O
320
mA
OUTPUT SWITCHING FREQUENCY
f
SW
400
560
650
kHz
SD INPUT
Logic Input High
V
IH
2.0
V
Input Current
I
IH
0.1
A
Logic Input Low
V
IL
0.8
V
Input Current
I
IL
0.1
A
NOTES
1
Capacitors in the test circuit are multilayer ceramic type.
2
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
3
Junction temperature is influenced by ambient temperature, device mounting and heatsinking, and power dissipation which is a function of I/O voltages and load.
4
R
TOTAL
includes the switch resistance, and the equivalent series resistance of the 2.2
F (X7R) MLCC pump capacitors.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1
Input Voltage (V+ to GND) . . . . . . . . . . . . . . . . . . . . +4.0 V
Output Short Circuit to GND (<1 A) . . . . . . . . . . . . . . 60 sec
Power Dissipation
JA
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +102
C/W
Operating Ambient Temperature Range . . . . 20
C to +85
C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150
C
Lead Temperature Range (Soldering 10 sec) . . . . . . . +300
C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220
C
NOTES
1
This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
2
JA
is specified for worst case conditions with device soldered on a FR-4, 1 oz.
copper clad four layer circuit board.
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
ADP3610ARU 20
C to +85
C Thin Shrink Small RU-16
Outline Package
(TSSOP-16)
(20 C
T
A
+85 C, V
IN
= +3.3 V, CP1 = CP2 = 2.2 F, C
O
= 1 F, SD = GND,
unless otherwise noted)
1, 2, 3
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3610 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
ADP3610
3
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
IN
SD
CM1
GND
GND
GND
CM2
V
IN
V
IN
V
IN
CP1
GND
V
OUT
V
OUT
CP2
V
IN
ADP3610
Table I. Other Members of ADP36xx Family
1
Output
Package
Model
Current
Options
2
Comments
ADP3603
50 mA
SO-8
Nom 3 V
3% Inverter
ADP3604
120 mA
SO-8
Nom 3 V
3% Inverter
ADP3605-3
120 mA
SO-8,
Nom 3 V
5% Inverter
TSSOP-14
ADP3607-5
50 mA
SO-8
Nom 5 V
5% Boost
ADP3607
50 mA
SO-8
Adjustable
5% Boost
NOTES
1
See individual data sheets for detailed ordering information.
2
SO = Small Outline; TSSOP = Thin Shrink Small Outline Package.
Table II. Alternative Capacitor Technologies
Type
Life
High Freq
Temp
Size
Cost
Aluminum
Electrolytic
Capacitor
Fair
Fair
Fair
Small
Low
Multilayer
Ceramic
Capacitor
Long
Good
Poor*
Fair
High
Solid
Tantalum
Above
Capacitor
Avg
Avg
Avg
Avg
Avg
OS-CON
Above
Capacitor
Avg
Good
Good
Good
Avg
*Refer to capacitor manufacturer's data sheet for operation below 0
C.
Table III. Recommended Capacitor Manufacturers
Manufacturer
Capacitor
Capacitor Type
Sprague
672D, 673D,
Aluminum Electrolytic
674D, 678D
Sprague
675D, 173D,
Tantalum
199D
Nichicon
PF and PL
Aluminum Electrolytic
Mallory
TDC and TDL
Tantalum
TOKIN
MLCC
Multilayer Ceramic
MuRata
GRM
Multilayer Ceramic
PIN FUNCTION DESCRIPTIONS
Pin
Name Function
1, 8, 9,
V
IN
Input Voltage. Pins 1, 8, 9, 15 and 16
15, 16
must be connected together for proper
operation.
2
SD
Shutdown. A logic low input allows normal
operation. A logic high input shuts the device
off.
3
CM1
Pump Capacitor C1 Negative Input
4, 5, 6,
GND
Ground. Pins 4, 5, 6, and 13 must be
13
connected together for proper operation.
7
CM2
Pump Capacitor C2 Negative Input
10
CP2
Pump Capacitor C2 Positive Input
11, 12
V
OUT
Output Voltage. Pins 11 and 12 must be
connected together for proper operation
.
14
CP1
Pump Capacitor C1 Positive Input
REV. A
ADP3610
4
TEMPERATURE C
OUTPUT VOLTAGE Volts
20
5
85
20
10
35
50
65
80
6.23
V
IN
= +3.3V
I
L
= 0mA
V
IN
= +3.3V
I
L
= 320mA
6.26
6.29
6.32
6.35
6.38
6.41
6.44
6.47
6.50
6.53
6.56
6.59
6.62
Figure 4. Output Voltage vs.
Temperature,
V
IN
= +3.3 V
LOAD CURRENT mA
OUTPUT VOLTAGE Volts
6.1
6.0
5.6
0
100
400
200
300
5.9
5.8
5.7
Figure 7. Output Voltage vs. Load
Current for V
IN
= +3.0 V
SUPPLY VOLTAGE Volts
570
560
550
2.7
3.6
2.8
OSCILLATOR FREQUENCY kHz
565
555
2.9 3.0
3.1
3.2
3.3 3.4
3.5
I
L
= 0mA
Figure 2. Oscillator Frequency vs.
Supply Voltage
TEMPERATURE C
OSCILLATOR FREQUENCY kHz
20
5
85
20
10
35
50
65
80
575
V
IN
= +3.0V
V
IN
= +3.3V
V
IN
= +3.6V
565
560
555
550
545
570
Figure 5. Oscillator Frequency vs.
Temperature
LOAD CURRENT mA
OUTPUT VOLTAGE Volts
6.7
6.6
6.2
0
100
400
200
300
6.5
6.4
6.3
Figure 8. Output Voltage vs. Load
Current for V
IN
= +3.3 V
TEMPERATURE C
SUPPLY CURRENT mA
9.5
8.9
20
5
85
20
8.1
10
35
50
65
80
7.7
7.9
8.3
8.5
8.7
9.1
9.3
9.7
V
IN
= +3.0V
V
IN
= +3.3V
V
IN
= +3.6V
Figure 3. Supply Current vs.
Temperature
TEMPERATURE C
SUPPLY CURRENT
A
20
5
85
20
10
35
50
65
80
0
V
IN
= +3.0V
V
IN
= +3.3V
V
IN
= +3.6V
0.2
0.4
0.6
Figure 6. Supply Current in Shutdown
Mode vs. Temperature
LOAD CURRENT mA
OUTPUT VOLTAGE Volts
7.3
7.2
6.8
0
100
400
200
300
7.1
7.0
6.9
Figure 9. Output Voltage vs. Load
Current for V
IN
= +3.6 V
Typical Performance Characteristics
REV. A
ADP3610
5
I
L
= 320mA
V
IN
Volts
20
10
3.0
3.2
3.4
3.6
5
I
L
= 0mA
QUIESCENT CURRENT I
Q
(mA)
15
Figure 10. Quiescent Current vs.
Input Voltage
LOAD CURRENT mA
100
20
0
80
320
160
240
5
EFFICIENCY %
40
60
80
Figure 11. Efficiency vs. Load Current,
V
IN
= +3.3 V
Figure 12. Output Voltage Ripple (I
O
=
320 mA, CP1 = CP2 = 2.2
F, C
O
= 1
F)
V
OUT
V
IN
Figure 13. Start-Up Under Full Load
(V
IN
= +3.6 V, I
O
= 320 mA)
10V
V
O
SD
5V
0V
Figure 14. Shutdown at Full Load
(V
IN
= +3.3 V, I
O
= 320 mA)
REV. A
ADP3610
6
THEORY OF OPERATION
The ADP3610 is an unregulated switched capacitor voltage
doubler that provides an output voltage greater than 5.4 V from
a +3.0 V to +3.6 V input. The unique push-pull voltage dou-
bling architecture allows it to deliver a maximum of 320 mA
output current. A typical application circuit, as shown in Figure
20, requires five small external capacitors. The ADP3610 has an
internal 1 MHz oscillator that is divided by two and used to
generate two nonoverlapping phase clocks.
The basic principle behind a conventional switched capacitor
voltage doubler is shown in Figure 15. During phase one, S1
and S2 are ON, charging the pump capacitor to the input volt-
age. In phase two, switches S1 and S2 are turned OFF and S3
and S4 are turned ON. During phase two, the pump capacitor
is placed in series with the input voltage, thereby charging the
output capacitor to the sum of input voltage and pump ca-
pacitor voltage, resulting in voltage doubling at the output
terminal.
+
S2
S1
V
IN
V
OUT
S3
S4
C
P
A
PHASE
1
PHASE
2
B
B
A
A
B
Figure 15. Conventional Voltage Doubler Configuration
The ADP3610 has two sets of switched capacitor voltage dou-
blers connected in parallel delivering charge to the output as
shown in Figure 16.
+
V
IN
V
OUT
S8
B
A
CP2
S6
S7
S2
S3
A
A
B
CP1
+
S5
S4
S1
B
B
A
Figure 16. Switch Configuration Charging the Pump
Capacitor
The two voltage doublers run in opposite phases, i.e., when one
pump capacitor is being charged, the other is charging the out-
put, as shown in Figure 17. In this architecture, one of the
pump capacitors is always delivering charge to the output. As a
result, output ripple is at a frequency that is double the switch-
ing frequency. This allows the use of a smaller output capacitor
compared to a conventional voltage doubler.
PHASE 1
(a)
V
IN
V
OUT
S8
CP2
S7
S2
CP1
A
A
A
+
+
S3
B
S4
B
S5
B
S6
B
S1
A
PHASE 2
(b)
B
S6
S3
S5
S4
B
V
OUT
+
+
CP1
CP2
V
IN
B
B
S8
A
S1
A
A
S2
A
S7
Figure 17. (a) Phase 1 "Push" Charging
(b) Phase 2 "Pull" Charging
Overvoltage Protection
The input voltage is scaled with a resistor network and com-
pared to the bandgap reference voltage of 1.25 V by a 50 mV
hysteresis comparator. When the input voltage exceeds 4.0 V,
the overvoltage protection signal stops the oscillator.
R1
R2
ADP3610
BANDGAP
= 1.25V
V
IN
OSC
EN
50mV
Figure 18. Overvoltage Protection
Shutdown Mode
The ADP3610's output can be disabled by pulling the SD pin
high to a TTL/CMOS logic compatible level which will stop the
internal oscillator. In shutdown mode, all analog circuitry in-
cluding overvoltage protection is shut off, thereby reducing the
quiescent current to 10
A typical. Applying a digital low level
or tying the SD pin to ground will turn on the output. If the
shutdown feature is not used, SD pin should be tied to the
ground pin. The output voltage in shutdown mode is approxi-
mately V
IN
0.6 V.
REV. A
ADP3610
7
APPLICATION INFORMATION
Capacitor Selection
The ADP3610's high internal oscillator frequency permits the
use of small capacitors for both the pump and the output ca-
pacitors. For a given load current, factors affecting the output
voltage performance are:
Pump (CP) and output (C
O
) capacitance
ESR of the CP and C
O
When selecting the capacitors, keep in mind that not all manu-
facturers guarantee capacitor ESR in the range required by the
circuit. In general, the capacitor's ESR is inversely proportional
to its physical size, so larger capacitance values and higher volt-
age ratings tend to reduce ESR. Since the ESR is also a function
of the operating frequency, when selecting a capacitor, make
sure its value is rated at the circuit's operating frequency. An-
other factor affecting capacitor performance is temperature. Fig-
ure 19 illustrates the temperature effect on various capacitors.
Aluminium electrolytic capacitors lose their capacitance at
low temperatures and their ESR increases considerably. Some
capacitor technologies do offer improved performance over
temperature; for example, certain tantalum capacitors provide
good low temperature ESR but at a higher cost. Table II pro-
vides the ratings for different types of capacitor technologies to
help the designer select the right capacitors for the application.
The exact values of C
IN
and C
O
are not critical. However, low
ESR capacitors such as solid tantalum and multilayer ceramic
capacitors are recommended to minimize voltage loss at high
currents. Table III shows a partial list of the recommended low
ESR capacitor manufacturers.
Input Capacitor
A small 1
F input bypass capacitor, preferably with low ESR,
such as tantalum or multilayer ceramic, is recommended to
reduce noise and supply transients and supply part of the peak
input current drawn by the ADP3610. A large capacitor is rec-
ommended if the input supply is connected to the ADP3610
through long leads, or if the pulse current drawn by the device
might affect other circuitry through supply coupling.
Output Capacitor
The output capacitor (C
O
) is alternately charged to the sum of
input voltage and pump capacitor voltage when CP is switched
in series with C
O
. The ESR of C
O
introduces steps in the V
OUT
waveform whenever the charge pump charges C
O
, which tends
to increase V
OUT
ripple. Thus, ceramic or tantalum capacitors
are recommended for C
O
to minimize ripple on the output.
Note that as the capacitor value increases beyond the point
where the dominant contribution to the output ripple is due to
the ESR, no significant reduction in V
OUT
ripple is achieved by
added capacitance.
Multiple smaller capacitors can be connected in parallel to yield
lower ESR and potential cost savings. For lighter loads, propor-
tionally smaller capacitors are required. To reduce high fre-
quency noise, bypass the output with a 0.1
F ceramic capacitor.
Pump Capacitor
The ADP3610 alternately charges CP to the input voltage when
it is switched in parallel with the input supply, and then trans-
fers charge to C
O
when it is switched in series with the input and
connected to the output.
ALUMINUM
CERAMIC
TANTALUM
ORGANIC SEMIC
TEMPERATURE C
ESR
10
1.0
0.01
50
0
100
50
0.1
TANTALUM
ORGANIC SEMIC
CERAMIC
ALUMINUM
Figure 19. ESR vs. Temperature
Power Dissipation
The power dissipation of the ADP3610 circuit must be limited
so the junction temperature of the device does not exceed the
maximum junction temperature rating. Total power dissipation
is calculated as follows:
P
D
= (2 V
IN
V
OUT
) I
OUT
+ V
IN
(I
S
)
Where I
OUT
and I
S
are output current and supply current, V
IN
and V
OUT
are input and output voltages respectively.
For example: assuming worst case conditions, V
IN
= 3 V,
V
OUT
= 5.62 V, I
OUT
= 320 mA and I
S
= 14 mA. Calculated
device power dissipation is:
P
D
(6 V 5.62 V)
0.32 + 3 (0.014) = 163.6 mW
The proprietary thermal coastline package used in the ADP3610
has a thermal resistance of 102
C/W. Therefore, the rise in
junction temperature for this application would be:
T
RISE
= 0.164 W
102
C/W = 16.7
C
General Board Layout Guidelines
Since the ADP3610's internal switches turn on and off very fast,
good PC board layout practices are critical to ensure optimal
operation of the device. Improper layouts will result in poor load
regulation, especially under heavy loads. Following these simple
layout guidelines will improve output performance.
1. Use adequate ground and power traces or planes.
2. Use single point ground for device ground and input and
output capacitor grounds.
3. Keep external components as close to the device as possible.
4. Use short traces from the input and output capacitors to the
input and output pins respectively.
5. All multiple GND, V
IN
and V
OUT
pins must be connected
together for proper operation.
REV. A
ADP3610
8
LOAD CURRENT mA
V
IN
= 3 V
6.0
0
0
OUTPUT VOLTAGE Volts
4.5
3.0
1.5
100
200
300
400
6 5.62
0.32
SLOPE = R
TOTAL
=
= 1.18
(5.62, 320 mA)
Figure 21. Load Regulation
Unregulated Voltage Doubler
Figure 20 shows a typical application for the ADP3610 in un-
regulated voltage doubling mode. The inherent limit on the
output voltage for a voltage doubler is two times the input volt-
age. However, due to the losses in the switches and ESR of
capacitors, this scaling factor is somewhat reduced. Figure 21
shows the magnitude of unregulated output voltage as the load
current is increased from 0 mA to 320 mA. This gives a measure
of the equivalent resistance R
TOTAL
. R
TOTAL
is comprised of
internal switch resistance and ESR of the capacitors.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
IN
SD
CM1
GND
GND
GND
CM2
V
IN
V
IN
V
IN
CP1
GND
V
OUT
V
OUT
CP2
V
IN
ADP3610
C
IN1
1 F
INPUT
V
IN
= 3.3V
OUTPUT
V
O
= 6.2V
@320mA
C
IN2
1 F
CP1
2.2 F
C
O
1 F
CP2
2.2 F
Figure 20. Unregulated Voltage Doubler
REV. A
ADP3610
9
TFT LCD System Design
The ADP3610 is very useful for applications like notebook LCD
displays which require a low profile solution. Figure 22 shows a
typical LCD display application. A TFT LCD display requires
+5 V main voltage and +17 V and 5 V auxiliary voltages. The
ADP3610 doubles the input voltage, which is then fed through a
discrete linear regulator to generate +5 V. The main voltage is
also fed to the ADP3605, which inverts the input voltage to
generate 5 V. The CP+ node of the ADP3605 pump capacitor
is fed to a diode-capacitor ladder network to quadruple the main
voltage, i.e., 4
V
MAIN
6
V
DIODE
17 V.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
IN
SD
CM1
GND
GND
GND
CM2
V
IN
V
IN
V
IN
CP1
GND
V
OUT
V
OUT
CP2
V
IN
ADP3610
1 F
V
IN
= 3.0V TO 3.6V
1 F
CP1
2.2 F
1 F
CP2
2.2 F
2.2 F
2.2 F
1 F
1 F
1 F
1 F
0.1 F
1 F
25.5k
24.9k
1k
470
V
MAIN
= 5V @
150mA
V
GH
= 17V @
3mA
CP+
GND
V
IN
V
OUT
SD
NC
V
SNS
CP
2.2 F
1 F
V
GL
= 5V @
30mA
NC = NO CONNECT
ADP3605
2.2 F
TL431
Figure 22. LCD Display Application
REV. A
ADP3610
10
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-16)
16
9
8
1
0.201 (5.10)
0.193 (4.90)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
C3442a07/99
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