Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Blackfin®

Embedded Processor

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

FEATURES

Up to 600 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit Shifter

RISC-like register and instruction model for ease of pro-

gramming and compiler-friendly support

Advanced debug, trace, and performance monitoring

0.8 V to 1.2 V core V

with on-chip voltage regulation

3.3 V and 2.5 V tolerant I/O
160-ball mini-BGA, 169-ball lead free PBGA, and 176-lead

LQFP packages

MEMORY

Up to 148K bytes of on-chip memory:

16K bytes of instruction SRAM/Cache
64K bytes of instruction SRAM
32K bytes of data SRAM/Cache
32K bytes of data SRAM
4K bytes of scratchpad SRAM

Two dual-channel memory DMA controllers
Memory Management Unit providing memory protection

External Memory Controller with glueless support for

SDRAM, SRAM, FLASH, and ROM

Flexible memory booting options from SPI and external

memory

PERIPHERALS

Parallel Peripheral Interface (PPI)/GPIO, supporting

ITU-R 656 video data formats

Two dual-channel, full duplex synchronous serial ports, sup-

porting eight stereo I

S channels

12-channel DMA controller
SPI compatible port
Three Timer/Counters with PWM support
UART with support for IrDA

Event Handler
Real-Time Clock
Watchdog Timer
Debug/JTAG interface
On-chip PLL capable of 1x to 63x frequency multiplication
Core Timer

Figure 1. Functional Block Diagram

VOLTAGE

REGULATOR

DMA

CONTROLLER

EVENT

CONTROLLER/

CORE TIMER

REAL-TIME CLOCK

UART PORT

IRDA®

TIMER0, TIMER1,

TIMER2

PPI / GPIO

SERIAL PORTS (2)

SPI PORT

EXTERNAL PORT

FLASH, SDRAM

CONTROL

BOOT ROM

JTAG TEST AND

EMULATION

WATCHDOG TIMER

INSTRUCTION

MEMORY

DATA

MEMORY

MMU

CORE / SYSTEM BUS INTERFACE

Rev. 0

Page 2 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

TABLE OF CONTENTS

General Description ................................................. 3

Portable Low Power Architecture ............................. 3

System Integration ................................................ 3

ADSP-BF531/2/3 Processor Peripherals ..................... 3

Blackfin Processor Core .......................................... 3

Memory Architecture ............................................ 4

DMA Controllers .................................................. 8

Real-Time Clock ................................................... 8

Watchdog Timer .................................................. 9

Timers ............................................................... 9

Serial Ports (SPORTs) ............................................ 9

Serial Peripheral Interface (SPI) Port ......................... 9

UART Port ........................................................ 10

Programmable Flags (PFx) .................................... 10

Parallel Peripheral Interface ................................... 10

Dynamic Power Management ................................ 11

Voltage Regulation .............................................. 12

Clock Signals ..................................................... 12

Booting Modes ................................................... 13

Instruction Set Description ................................... 14

Development Tools ............................................. 14

Designing an Emulator Compatible Processor Board ... 15

Pin Descriptions .................................................... 16

Specifications ........................................................ 19

Recommended Operating Conditions ...................... 19

Electrical Characteristics ....................................... 19

Absolute Maximum Ratings .................................. 20

ESD Sensitivity ................................................... 20

Timing Specifications ........................................... 21

Clock and Reset Timing ..................................... 22

Asynchronous Memory Read Cycle Timing ............ 23

Asynchronous Memory Write Cycle Timing ........... 24

SDRAM Interface Timing .................................. 25

External Port Bus Request and Grant Cycle Timing .. 26

Parallel Peripheral Interface Timing ...................... 27

Serial Ports ..................................................... 28

Serial Peripheral Interface (SPI) Port

--Master Timing ........................................... 33

Serial Peripheral Interface (SPI) Port

--Slave Timing ............................................. 34

Universal Asynchronous Receiver-Transmitter

(UART) Port--Receive and Transmit Timing ...... 35

Programmable Flags Cycle Timing ....................... 36

Timer Cycle Timing .......................................... 37

JTAG Test And Emulation Port Timing ................. 38

Output Drive Currents ......................................... 39

Power Dissipation ............................................... 41

Test Conditions .................................................. 42

Environmental Conditions .................................... 45

160-Lead BGA Pinout ............................................. 46

169-Ball PBGA Pinout ............................................. 49

176-Lead LQFP Pinout ............................................ 51

Outline Dimensions ................................................ 53

Ordering Guide ..................................................... 56

REVISION HISTORY

Revision 0: Initial Version

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 3 of 56

March 2004

GENERAL DESCRIPTION

The ADSP-BF531/2/3 processors are members of the Blackfin
family of products, incorporating the Analog Devices/Intel
Micro Signal Architecture (MSA). Blackfin processors combine
a dual-MAC state-of-the-art signal processing engine, the
advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set
architecture.

The ADSP-BF531/2/3 processors are completely code and pin
compatible, differing only with respect to their performance and
on-chip memory. Specific performance and memory configura-
tions are shown in

Table 1

By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like program-
mability, multimedia support, and leading-edge signal
processing in one integrated package.

PORTABLE LOW POWER ARCHITECTURE

Blackfin processors provide world-class power management
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature
Dynamic Power Management, the ability to vary both the volt-
age and frequency of operation to significantly lower overall
power consumption. Varying the voltage and frequency can
result in a substantial reduction in power consumption, com-
pared with just varying the frequency of operation. This
translates into longer battery life for portable appliances.

SYSTEM INTEGRATION

The ADSP-BF531/2/3 processors are highly integrated system-
on-a-chip solutions for the next generation of digital communi-
cation and consumer multimedia applications. By combining
industry-standard interfaces with a high performance signal
processing core, users can develop cost-effective solutions
quickly without the need for costly external components. The
system peripherals include a UART port, an SPI port, two serial
ports (SPORTs), four general-purpose timers (three with PWM
capability), a real-time clock, a watchdog timer, and a Parallel
Peripheral Interface.

ADSP-BF531/2/3 PROCESSOR PERIPHERALS

The ADSP-BF531/2/3 processor contains a rich set of peripher-
als connected to the core via several high bandwidth buses,
providing flexibility in system configuration as well as excellent
overall system performance (see the functional block diagram in

Figure 1 on Page 1

). The general-purpose peripherals include

functions such as UART, Timers with PWM (Pulse-Width
Modulation) and pulse measurement capability, general-pur-
pose flag I/O pins, a Real-Time Clock, and a Watchdog Timer.
This set of functions satisfies a wide variety of typical system
support needs and is augmented by the system expansion capa-
bilities of the part. In addition to these general-purpose
peripherals, the ADSP-BF531/2/3 processor contains high speed
serial and parallel ports for interfacing to a variety of audio,
video, and modem codec functions; an interrupt controller for
flexible management of interrupts from the on-chip peripherals
or external sources; and power management control functions
to tailor the performance and power characteristics of the pro-
cessor and system to many application scenarios.

All of the peripherals, except for general-purpose I/O, Real-
Time Clock, and timers, are supported by a flexible DMA struc-
ture. There is also a separate memory DMA channel dedicated
to data transfers between the processor's various memory
spaces, including external SDRAM and asynchronous memory.
Multiple on-chip buses running at up to 133 MHz provide
enough bandwidth to keep the processor core running along
with activity on all of the on-chip and external peripherals.

The ADSP-BF531/2/3 processor includes an on-chip voltage
regulator in support of the ADSP-BF531/2/3 processor
Dynamic Power Management capability. The voltage regulator
provides a range of core voltage levels from a single 2.25 V to
3.6 V input. The voltage regulator can be bypassed at the user's
discretion.

BLACKFIN PROCESSOR CORE

As shown in

Figure 2 on Page 5

, the Blackfin processor core

contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-
tation units process 8-bit, 16-bit, or 32-bit data from the
register file.

The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.

Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.

The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 2

multiply, divide primitives,

Table 1. Processor Comparison

ADSP-BF531

ADSP-BF532

ADSP-BF533

Maximum
Performance

400 MHz
800 MMACs

600 MHz
1200 MMACs

Instruction
SRAM/Cache

16K bytes

Instruction
SRAM

16K bytes

32K bytes

64K bytes

Data
SRAM/Cache

16K bytes

32K bytes

Data SRAM

32K bytes

Scratchpad

4K bytes

Rev. 0

Page 4 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

saturation and rounding, and sign/exponent detection. The set
of video instructions includes byte alignment and packing oper-
ations, 16-bit and 8-bit adds with clipping, 8-bit average
operations, and 8-bit subtract/absolute value/accumulate (SAA)
operations. Also provided are the compare/select and vector
search instructions.

For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). By also using the second
ALU, quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.

The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.

The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit Index, Modify,
Length, and Base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).

Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.

In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The Memory Manage-
ment Unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.

The architecture provides three modes of operation: User mode,
Supervisor mode, and Emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while Supervisor mode has
unrestricted access to the system and core resources.

The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.

The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE

The ADSP-BF531/2/3 processor views memory as a single uni-
fied 4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low latency on-chip memory as cache
or SRAM, and larger, lower cost and performance off-chip
memory systems. See

Figure 3 on Page 5

Figure 4 on Page 5

and

Figure 5 on Page 6

The L1 memory system is the primary highest performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the External Bus Interface Unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132M bytes of physical
memory.

The memory DMA controller provides high bandwidth data-
movement capability. It can perform block transfers of code or
data between the internal memory and the external memory
spaces.

Internal (On-Chip) Memory

The ADSP-BF531/2/3 processor has three blocks of on-chip
memory providing high bandwidth access to the core.

The first is the L1 instruction memory, consisting of up to
80K bytes SRAM, of which 16K bytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.

The second on-chip memory block is the L1 data memory, con-
sisting of up to two banks of up to 32K bytes each. Each memory
bank is configurable, offering both cache and SRAM functional-
ity. This memory block is accessed at full processor speed.

The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.

External (Off-Chip) Memory

The External Bus interface can be used with both asynchronous
devices such as SRAM, FLASH, EEPROM, ROM, and I/O
devices, and synchronous devices such as SDRAMs. The bus
width is always 16 bits. A1 is the least significant address of a
16-bit word. 8-bit peripherals should be addressed as if they
were 16-bit devices, where only the lower 8 bits of data should
be used.

The PC133-compliant SDRAM controller can be programmed
to interface to up to 128M bytes of SDRAM. The SDRAM con-
troller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 5 of 56

March 2004

Figure 2. Blackfin Processor Core

S EQUENCER

ALIG N

DECO DE

LOO P BUF FE R

DAG0

DAG 1

A 0

BARREL
SHIFTER

DATA ARITHME TIC UNI T

CONTRO L

UNIT

ADDRE SS ARITHMETIC UNIT

I 3

I 2

I 1

I 0

LD0 32 BITS

LD1 32 BITS

SD 32 BI TS

R7.L
R6.L

R5.L

R4.L

R3.L

R2.L
R1.L

R0.L

R7.H
R6.H

R5.H

R4.H

R3.H

R2.H
R1.H

R0.H

R7
R6

R2
R1

Figure 3. ADSP-BF533 Internal/External Memory Map

RESERVED

CORE MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

INSTRUCTION SRAM (64K BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

DATA BANK B SRAM / CACHE (16K BYTE)

DATA BANK B SRAM (16K BYTE)

DATA BANK A SRAM / CACHE (16K BYTE)

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

SDRAM MEMORY (16M BYTE TO 128M BYTE)

INSTRUCTION SRAM / CACHE (16K BYTE)

I
N

0xFFFF FFFF

0xFFE0 0000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

0xFFC0 0000

0xFFB0 1000

0xFFA0 0000

RESERVED

DATA BANK A SRAM (16K BYTE)

0xFF90 0000

0xFF80 0000

RESERVED

Figure 4. ADSP-BF532 Internal/External Memory Map

CORE MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

DATA BANK B SRAM / CACHE (16K BYTE)

RESERVED

DATA BANK A SRAM / CACHE (16K BYTE)

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

SDRAM MEMORY (16M BYTE TO 128M BYTE)

INSTRUCTION SRAM / CACHE (16K BYTE)

I
N

0xFFFF FFFF

0xFFE0 0000

0xFFB0 0000

0xFFA1 4000

0xFFA0 8000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

0xFFC0 0000

0xFFB0 1000

0xFFA0 0000

RESERVED

0xFFA1 0000

INSTRUCTION SRAM (32K BYTE)

RESERVED

Rev. 0

Page 6 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully popu-
lated with 1M byte of memory.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory-mapped registers (MMRs) at addresses near the top of
the 4G byte address space. These are separated into two smaller
blocks, one of which contains the control MMRs for all core
functions, and the other of which contains the registers needed
for setup and control of the on-chip peripherals outside of the
core. The MMRs are accessible only in supervisor mode and
appear as reserved space to on-chip peripherals.

Booting

The ADSP-BF531/2/3 processor contains a small boot kernel,
which configures the appropriate peripheral for booting. If the
ADSP-BF531/2/3 processor is configured to boot from boot
ROM memory space, the processor starts executing from the
on-chip boot ROM. For more information, see

Booting Modes

on Page 13

Event Handling

The event controller on the ADSP-BF531/2/3 processor handles
all asynchronous and synchronous events to the processor. The
ADSP-BF531/2/3 processor provides event handling that sup-
ports both nesting and prioritization. Nesting allows multiple
event service routines to be active simultaneously. Prioritization
ensures that servicing of a higher priority event takes prece-
dence over servicing of a lower priority event. The controller
provides support for five different types of events:

· Emulation An emulation event causes the processor to

enter emulation mode, allowing command and control of
the processor via the JTAG interface.

· Reset This event resets the processor.

· Non-Maskable Interrupt (NMI) The NMI event can be

generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.

· Exceptions Events that occur synchronously to program

flow (i.e., the exception will be taken before the instruction
is allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.

· Interrupts Events that occur asynchronously to program

flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.

The ADSP-BF531/2/3 processor Event Controller consists of
two stages, the Core Event Controller (CEC) and the System
Interrupt Controller (SIC). The Core Event Controller works
with the System Interrupt Controller to prioritize and control all
system events. Conceptually, interrupts from the peripherals
enter into the SIC, and are then routed directly into the general-
purpose interrupts of the CEC.

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG157),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority inter-
rupts (IVG1514) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF531/2/3 processor.

Table 2

describes the inputs to the CEC, identifies their names

in the Event Vector Table (EVT), and lists their priorities.

System Interrupt Controller (SIC)

The System Interrupt Controller provides the mapping and
routing of events from the many peripheral interrupt sources to
the prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF531/2/3 processor provides a default
mapping, the user can alter the mappings and priorities of

Figure 5. ADSP-BF531 Internal/External Memory Map

CORE MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

DATA BANK A SRAM / CACHE (16K BYTE)

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

SDRAM MEMORY (16M BYTE TO 128M BYTE)

INSTRUCTION SRAM / CACHE (16K BYTE)

I
N

0xFFFF FFFF

0xFFE0 0000

0xFFB0 0000

0xFFA1 4000

0xFFA0 8000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

0xFFC0 0000

0xFFB0 1000

0xFFA0 0000

RESERVED

0xFFA1 0000

INSTRUCTION SRAM (16K BYTE)

RESERVED

0xFFA0 C000

RESERVED

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 7 of 56

March 2004

interrupt events by writing the appropriate values into the Inter-
rupt Assignment Registers (IAR).

Table 3

describes the inputs

into the SIC and the default mappings into the CEC.

Event Control

The ADSP-BF531/2/3 processor provides the user with a very
flexible mechanism to control the processing of events. In the
CEC, three registers are used to coordinate and control events.
Each register is 16 bits wide:

· CEC Interrupt Latch Register (ILAT) The ILAT register

indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may be written only when its corresponding IMASK bit
is cleared.

· CEC Interrupt Mask Register (IMASK) The IMASK reg-

ister controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event, pre-
venting the processor from servicing the event even though
the event may be latched in the ILAT register. This register
may be read or written while in supervisor mode. (Note
that general-purpose interrupts can be globally enabled and
disabled with the STI and CLI instructions, respectively.)

· CEC Interrupt Pending Register (IPEND) The IPEND

register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.

The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in

Table 3 on Page 7

· SIC Interrupt Mask Register (SIC_IMASK) This register

controls the masking and unmasking of each peripheral
interrupt event. When a bit is set in the register, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in the register masks
the peripheral event, preventing the processor from servic-
ing the event.

· SIC Interrupt Status Register (SIC_ISR) As multiple

peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.

· SIC Interrupt Wakeup Enable Register (SIC_IWR) By

enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated. (

For more infor-

mation, see Dynamic Power Management on Page 11.

)

Table 2. Core Event Controller (CEC)

Priority
(0 is Highest)

Event Class

EVT Entry

Emulation/Test Control

EMU

Reset

RST

Non-Maskable Interrupt

NMI

Exception

EVX

Reserved

Hardware Error

IVHW

Core Timer

IVTMR

General Interrupt 7

IVG7

General Interrupt 8

IVG8

General Interrupt 9

IVG9

General Interrupt 10

IVG10

General Interrupt 11

IVG11

General Interrupt 12

IVG12

General Interrupt 13

IVG13

General Interrupt 14

IVG14

General Interrupt 15

IVG15

Table 3. System Interrupt Controller (SIC)

Peripheral Interrupt Event

Default Mapping

PLL Wakeup

IVG7

DMA Error

IVG7

PPI Error

IVG7

SPORT 0 Error

IVG7

SPORT 1 Error

IVG7

SPI Error

IVG7

UART Error

IVG7

Real-Time Clock

IVG8

DMA Channel 0 (PPI)

IVG8

DMA Channel 1 (SPORT 0 RX)

IVG9

DMA Channel 2 (SPORT 0 TX)

IVG9

DMA Channel 3 (SPORT 1 RX)

IVG9

DMA Channel 4 (SPORT 1 TX)

IVG9

DMA Channel 5 (SPI)

IVG10

DMA Channel 6 (UART RX)

IVG10

DMA Channel 7 (UART TX)

IVG10

Timer 0

IVG11

Timer 1

IVG11

Timer 2

IVG11

PF Interrupt A

IVG12

PF Interrupt B

IVG12

DMA Channels 8 and 9
(Memory DMA Stream 1)

IVG13

DMA Channels 10 and 11
(Memory DMA Stream 0)

IVG13

Software Watchdog Timer

IVG13

Rev. 0

Page 8 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.

DMA CONTROLLERS

The ADSP-BF531/2/3 processor has multiple, independent
DMA controllers that support automated data transfers with
minimal overhead for the processor core. DMA transfers can
occur between the ADSP-BF531/2/3 processor's internal memo-
ries and any of its DMA-capable peripherals. Additionally,
DMA transfers can be accomplished between any of the DMA-
capable peripherals and external devices connected to the exter-
nal memory interfaces, including the SDRAM controller and
the asynchronous memory controller. DMA-capable peripher-
als include the SPORTs, SPI port, UART, and PPI. Each
individual DMA-capable peripheral has at least one dedicated
DMA channel.

The ADSP-BF531/2/3 processor DMA controller supports both
1-dimensional (1D) and 2-dimensional (2D) DMA transfers.
DMA transfer initialization can be implemented from registers
or from sets of parameters called descriptor blocks.

The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be
de-interleaved on the fly.

Examples of DMA types supported by the ADSP-BF531/2/3
processor DMA controller include:

· A single, linear buffer that stops upon completion

· A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

· 1-D or 2-D DMA using a linked list of descriptors

· 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page

In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels provided for transfers between the
various memories of the ADSP-BF531/2/3 processor system.
This enables transfers of blocks of data between any of the
memories--including external SDRAM, ROM, SRAM, and
flash memory--with minimal processor intervention. Memory

DMA transfers can be controlled by a very flexible descriptor
based methodology or by a standard register based autobuffer
mechanism.

REAL-TIME CLOCK

The ADSP-BF531/2/3 processor Real-Time Clock (RTC) pro-
vides a robust set of digital watch features, including current
time, stopwatch, and alarm. The RTC is clocked by a
32.768 KHz crystal external to the ADSP-BF531/2/3 processor.
The RTC peripheral has dedicated power supply pins so that it
can remain powered up and clocked even when the rest of the
processor is in a low-power state. The RTC provides several
programmable interrupt options, including interrupt per sec-
ond, minute, hour, or day clock ticks, interrupt on
programmable stopwatch countdown, or interrupt at a pro-
grammed alarm time.

The 32.768 KHz input clock frequency is divided down to a
1 Hz signal by a prescaler. The counter function of the timer
consists of four counters: a 60-second counter, a 60-minute
counter, a 24-hour counter, and a 32,768-day counter.

When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of that
day.

The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.

Like other peripherals, the RTC can wake up the processor from
Sleep mode upon generation of any RTC wakeup event.
Additionally, an RTC wakeup event can wake up the processor
from Deep Sleep mode, and wake up the on-chip internal volt-
age regulator from a powered-down state.

Connect RTC pins RTXI and RTXO with external components
as shown in

Figure 6

Figure 6. External Components for RTC

RTXO

SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12 PF LOAD (SURFACE-MOUNT PACKAGE)
C1 = 22 PF
C2 = 22 PF
R1 = 10 M OHM

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.

RTXI

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 9 of 56

March 2004

WATCHDOG TIMER

The ADSP-BF531/2/3 processor includes a 32-bit timer that can
be used to implement a software watchdog function. A software
watchdog can improve system availability by forcing the proces-
sor to a known state through generation of a hardware reset,
non-maskable interrupt (NMI), or general-purpose interrupt, if
the timer expires before being reset by software. The program-
mer initializes the count value of the timer, enables the
appropriate interrupt, then enables the timer. Thereafter, the
software must reload the counter before it counts to zero from
the programmed value. This protects the system from remain-
ing in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.

If configured to generate a hardware reset, the watchdog timer
resets both the core and the ADSP-BF531/2/3 processor periph-
erals. After a reset, software can determine if the watchdog was
the source of the hardware reset by interrogating a status bit in
the watchdog timer control register.

The timer is clocked by the system clock (SCLK), at a maximum
frequency of f

SCLK

TIMERS

There are four general-purpose programmable timer units in
the ADSP-BF531/2/3 processor. Three timers have an external
pin that can be configured either as a Pulse-Width Modulator
(PWM) or timer output, as an input to clock the timer, or as a
mechanism for measuring pulse-widths and periods of external
events. These timers can be synchronized to an external clock
input to the PF1 pin, an external clock input to the PPI_CLK
pin, or to the internal SCLK.

The timer units can be used in conjunction with the UART to
measure the width of the pulses in the data stream to provide an
auto-baud detect function for a serial channel.

The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.

In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.

SERIAL PORTS (SPORTS)

The ADSP-BF531/2/3 processor incorporates two dual-channel
synchronous serial ports (SPORT0 and SPORT1) for serial and
multiprocessor communications. The SPORTs support the fol-
lowing features:

· I

S capable operation.

· Bidirectional operation Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels
of I

S stereo audio.

· Buffered (8-deep) transmit and receive ports Each port

has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.

· Clocking Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies
ranging from (f

SCLK

/131,070) Hz to (f

SCLK

/2) Hz.

· Word length Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most-significant-bit
first or least-significant-bit first.

· Framing Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.

· Companding in hardware Each SPORT can perform

A-law or µ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.

· DMA operations with single-cycle overhead Each SPORT

can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.

· Interrupts Each transmit and receive port generates an

interrupt upon completing the transfer of a data-word or
after transferring an entire data buffer or buffers through
DMA.

· Multichannel capability Each SPORT supports 128 chan-

nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The ADSP-BF531/2/3 processor has an SPI-compatible port
that enables the processor to communicate with multiple SPI-
compatible devices.

The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSI, and Master Input-
Slave Output, MISO) and a clock pin (Serial Clock, SCK). An
SPI chip select input pin (SPISS) lets other SPI devices select the
processor, and seven SPI chip select output pins (SPISEL71) let
the processor select other SPI devices. The SPI select pins are
reconfigured Programmable Flag pins. Using these pins, the SPI
port provides a full-duplex, synchronous serial interface, which
supports both master/slave modes and multimaster
environments.

The SPI port's baud rate and clock phase/polarities are pro-
grammable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. The
SPI's DMA controller can only service unidirectional accesses at
any given time.

The SPI port's clock rate is calculated as:

Where the 16-bit SPI_Baud register contains a value of 2 to
65,535.

SPI Clock Rate

SCLK

2 SPI_Baud

---------------------------------

Rev. 0

Page 10 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.

UART PORT

The ADSP-BF531/2/3 processor provides a full-duplex Univer-
sal Asynchronous Receiver/Transmitter (UART) port, which is
fully compatible with PC-standard UARTs. The UART port
provides a simplified UART interface to other peripherals or
hosts, supporting full-duplex, DMA-supported, asynchronous
transfers of serial data. The UART port includes support for 5 to
8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The
UART port supports two modes of operation:

· PIO (Programmed I/O) The processor sends or receives

data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.

· DMA (Direct Memory Access) The DMA controller

transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.

The UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:

· Supporting bit rates ranging from (f

SCLK

/ 1,048,576) to

SCLK

/16) bits per second.

· Supporting data formats from 7 to12 bits per frame.

· Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

The UART port's clock rate is calculated as:

Where the 16-bit UART_Divisor comes from the DLH register
(most significant 8 bits) and DLL register (least significant
8 bits).

In conjunction with the general-purpose timer functions, auto-
baud detection is supported.

The capabilities of the UART are further extended with support
for the Infrared Data Association (IrDA®) Serial Infrared Physi-
cal Layer Link Specification (SIR) protocol.

PROGRAMMABLE FLAGS (PFX)

The ADSP-BF531/2/3 processor has 16 bidirectional, general-
purpose Programmable Flag (PF150) pins. Each programma-
ble flag can be individually controlled by manipulation of the
flag control, status and interrupt registers:

· Flag Direction Control Register Specifies the direction of

each individual PFx pin as input or output.

· Flag Control and Status Registers The ADSP-BF531/2/3

processor employs a "write one to modify" mechanism that
allows any combination of individual flags to be modified
in a single instruction, without affecting the level of any
other flags. Four control registers are provided. One regis-
ter is written in order to set flag values, one register is
written in order to clear flag values, one register is written
in order to toggle flag values, and one register is written in
order to specify a flag value. Reading the flag status register
allows software to interrogate the sense of the flags.

· Flag Interrupt Mask Registers The two Flag Interrupt

Mask Registers allow each individual PFx pin to function as
an interrupt to the processor. Similar to the two Flag Con-
trol Registers that are used to set and clear individual flag
values, one Flag Interrupt Mask Register sets bits to enable
interrupt function, and the other Flag Interrupt Mask reg-
ister clears bits to disable interrupt function. PFx pins
defined as inputs can be configured to generate hardware
interrupts, while output PFx pins can be triggered by soft-
ware interrupts.

· Flag Interrupt Sensitivity Registers The two Flag Inter-

rupt Sensitivity Registers specify whether individual PFx
pins are level- or edge-sensitive and specify--if edge-sensi-
tive--whether just the rising edge or both the rising and
falling edges of the signal are significant. One register
selects the type of sensitivity, and one register selects which
edges are significant for edge-sensitivity.

PARALLEL PERIPHERAL INTERFACE

The processor provides a Parallel Peripheral Interface (PPI) that
can connect directly to parallel A/D and D/A converters, ITU-R
601/656 video encoders and decoders, and other general-pur-
pose peripherals. The PPI consists of a dedicated input clock
pin, up to 3 frame synchronization pins, and up to 16 data pins.
The input clock supports parallel data rates up to half the system
clock rate.

In ITU-R 656 modes, the PPI receives and parses a data stream
of 8-bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information is
supported.

Three distinct ITU-R 656 modes are supported:

· Active Video Only - The PPI does not read in any data

between the End of Active Video (EAV) and Start of Active
Video (SAV) preamble symbols, or any data present during

UART Clock Rate

SCLK

16 UART_Divisor

------------------------------------------------

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 11 of 56

March 2004

the vertical blanking intervals. In this mode, the control
byte sequences are not stored to memory; they are filtered
by the PPI.

· Vertical Blanking Only - The PPI only transfers Vertical

Blanking Interval (VBI) data, as well as horizontal blanking
information and control byte sequences on VBI lines.

· Entire Field - The entire incoming bitstream is read in

through the PPI. This includes active video, control pream-
ble sequences, and ancillary data that may be embedded in
horizontal and vertical blanking intervals.

Though not explicitly supported, ITU-R 656 output functional-
ity can be achieved by setting up the entire frame structure
(including active video, blanking, and control information) in
memory and streaming the data out the PPI in a frame sync-less
mode. The processor's 2D DMA features facilitate this transfer
by allowing the static frame buffer (blanking and control codes)
to be placed in memory once, and simply updating the active
video information on a per-frame basis.

The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:

· Data Receive with Internally Generated Frame Syncs

· Data Receive with Externally Generated Frame Syncs

· Data Transmit with Internally Generated Frame Syncs

· Data Transmit with Externally Generated Frame Syncs

These modes support ADC/DAC connections, as well as video
communication with hardware signaling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception/transmission of data.

DYNAMIC POWER MANAGEMENT

The ADSP-BF531/2/3 processor provides five operating modes,
each with a different performance/power profile. In addition,
Dynamic Power Management provides the control functions to
dynamically alter the processor core supply voltage, further
reducing power dissipation. Control of clocking to each of the
ADSP-BF531/2/3 processor peripherals also reduces power con-
sumption. See

Table 4

for a summary of the power settings for

each mode.

Full-On Operating Mode--Maximum Performance

In the Full-On mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.

Active Operating Mode--Moderate Power Savings

In the Active mode, the PLL is enabled but bypassed. Because
the PLL is bypassed, the processor's core clock (CCLK) and sys-
tem clock (SCLK) run at the input clock (CLKIN) frequency. In
this mode, the CLKIN to CCLK multiplier ratio can be changed,

although the changes are not realized until the Full-On mode is
entered. DMA access is available to appropriately configured L1
memories.

In the Active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the Full-On or Sleep modes.

Hibernate Operating Mode--Maximum Static Power
Savings

The Hibernate mode maximizes static power savings by dis-
abling the voltage and clocks to the processor core (CCLK) and
to all the synchronous peripherals (SCLK). The internal voltage
regulator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (V

DDINT

) to 0 V to provide the lowest static power

dissipation. Any critical information stored internally (memory
contents, register contents, etc.) must be written to a non-vola-
tile storage device prior to removing power if the processor state
is to be preserved. Since V

DDEXT

is still supplied in this mode, all

of the external pins tri-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
have power still applied without drawing unwanted current.
The internal supply regulator can be woken up either by a Real-
Time Clock wakeup or by asserting the RESET pin.

Sleep Operating Mode--High Dynamic Power Savings

The Sleep mode reduces dynamic power dissipation by dis-
abling the clock to the processor core (CCLK). The PLL and
system clock (SCLK), however, continue to operate in this
mode. Typically an external event or RTC activity will wake up
the processor. When in the Sleep mode, assertion of wakeup will
cause the processor to sense the value of the BYPASS bit in the
PLL Control register (PLL_CTL). If BYPASS is disabled, the
processor will transition to the Full On mode. If BYPASS is
enabled, the processor will transition to the Active mode.

When in the Sleep mode, system DMA access to L1 memory is
not supported.

Deep Sleep Operating Mode--Maximum Dynamic Power
Savings

The Deep Sleep mode maximizes dynamic power savings by
disabling the clocks to the processor core (CCLK) and to all syn-
chronous peripherals (SCLK). Asynchronous peripherals, such

Table 4. Power Settings

Mode

PLL

PLL
Bypassed

Core
Clock
(CCLK)

System
Clock
(SCLK)

Core
Power

Full On

Enabled

Enabled Enabled On

Active

Enabled/
Disabled

Yes

Enabled Enabled On

Sleep

Enabled

Disabled Enabled On

Deep Sleep Disabled

Disabled Disabled On

Hibernate

Disabled

Disabled Disabled Off

Rev. 0

Page 12 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

as the RTC, may still be running but will not be able to access
internal resources or external memory. This powered-down
mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in Deep Sleep mode, an RTC asynchronous inter-
rupt causes the processor to transition to the Active mode.
Assertion of RESET while in Deep Sleep mode causes the pro-
cessor to transition to the Full-On mode.

Power Savings

As shown in

Table 5

, the ADSP-BF531/2/3 processor supports

three different power domains. The use of multiple power
domains maximizes flexibility, while maintaining compliance
with industry standards and conventions. By isolating the inter-
nal logic of the ADSP-BF531/2/3 processor into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of Dynamic Power Management, without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains.

The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.

The Dynamic Power Management feature of the ADSP-
BF531/2/3 processor allows both the processor's input voltage
(V

DDINT

) and clock frequency (f

CCLK

) to be dynamically

controlled.

The savings in power dissipation can be modeled using the
Power Savings Factor and % Power Savings calculations.

The Power Savings Factor is calculated as:

where the variables in the equations are:

· f

CCLKNOM

is the nominal core clock frequency

· f

CCLKRED

is the reduced core clock frequency

· V

DDINTNOM

is the nominal internal supply voltage

· V

DDINTRED

is the reduced internal supply voltage

· T

NOM

is the duration running at f

CCLKNOM

· T

RED

is the duration running at f

CCLKRED

The percent power savings is calculated as:

VOLTAGE REGULATION

The Blackfin processor provides an on-chip voltage regulator
that can generate processor core voltage levels 0.85V(-5% /
+10%) to 1.2V(-5% / +10%) from an external 2.25 V to 3.6 V
supply.

Figure 7

shows the typical external components

required to complete the power management system.

The regu-

lator controls the internal logic voltage levels and is
programmable with the Voltage Regulator Control Register
(VR_CTL) in increments of 50 mV. To reduce standby power
consumption, the internal voltage regulator can be programmed
to remove power to the processor core while keeping I/O power
(V

DDEXT

) supplied. While in hibernation, V

DDEXT

can still be

applied, eliminating the need for external buffers. The voltage
regulator can be activated from this power-down state either
through an RTC wakeup or by asserting RESET, which will then
initiate a boot sequence. The regulator can also be disabled and
bypassed at the user's discretion.

CLOCK SIGNALS

The ADSP-BF531/2/3 processor can be clocked by an external
crystal, a sine wave input, or a buffered, shaped clock derived
from an external clock oscillator.

If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor's CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.

Table 5. Power Domains

Power Domain

VDD Range

All internal logic, except RTC

DDINT

RTC internal logic and crystal I/O

DDRTC

All other I/O

DDEXT

Power Savings Factor

CCLKRED

CCLKNOM

---------------------

DDINTRED

DDINTNOM

--------------------------

RED

NOM

-------------

See EE-228: Switching Regulator Design Considerations for ADSP-BF533

Blackfin Processors.

Figure 7. Voltage Regulator Circuit

% Power Savings

1 Power Savings Factor

(

)

100%

DDEXT

DDINT

OUT

1-0

EXTERNAL COMPONENTS

2.25V TO 3.6V
INPUT VOLTAGE
RANGE

NDS8434

ZHCS1000

100 µF

1 µF

10 µH

0.1 µF

NOTE: VR

OUT

1-0 SHOULD BE TIED TOGETHER EXTERNALLY

AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO NDS8434.

100 µF

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 13 of 56

March 2004

Alternatively, because the ADSP-BF531/2/3 processor includes
an on-chip oscillator circuit, an external crystal may be used.
The crystal should be connected across the CLKIN and XTAL
pins, with two capacitors connected as shown in

Figure 8

Capacitor values are dependent on crystal type and should be
specified by the crystal manufacturer. A parallel-resonant,
fundamental frequency, microprocessor-grade crystal should be
used.

As shown in

Figure 9 on Page 13

, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a user programmable 1x to 63x multiplica-
tion factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10x, but it can be
modified by a software instruction sequence. On-the-fly fre-
quency changes can be effected by simply writing to the
PLL_DIV register.

All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL30 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.

Table 6

illustrates typical system clock ratios.

The maximum frequency of the system clock is f

SCLK

. Note that

the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of f

SCLK

. The SSEL value can be changed

dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).

The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL10 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7

. This programmable core clock capability is useful for

fast core frequency modifications.

BOOTING MODES

The ADSP-BF531/2/3 processor has two mechanisms (listed in

Table 8

) for automatically loading internal L1 instruction mem-

ory after a reset. A third mode is provided to execute from
external memory, bypassing the boot sequence.

Figure 8. External Crystal Connections

Figure 9. Frequency Modification Methods

CLKIN

CLKOUT

XTAL

PLL

0. 5

- 64

÷ 1:15

÷ 1, 2, 4, 8

VCO

SCLK

CCLK

SCLK

133 MHZ

CLKI N

"FI NE" ADJUSTMENT

REQUI RES PLL SEQ UENCING

"CO ARSE" ADJUSTMENT

ON-THE-FLY

CCLK

SCLK

Table 6. Example System Clock Ratios

Signal Name
SSEL30

Divider Ratio
VCO/SCLK

Example Frequency Ratios
(MHz)

VCO

SCLK

0001

1:1

100

0011

3:1

400

133

1010

10:1

500

Table 7. Core Clock Ratios

Signal Name
CSEL10

Divider Ratio
VCO/CCLK

Example Frequency Ratios

VCO

CCLK

1:1

300

2:1

300

150

4:1

500

125

8:1

200

Table 8. Booting Modes

BMODE1 0

Description

Execute from 16-Bit External Memory (Bypass
Boot ROM)

Boot from 8-Bit or 16-Bit FLASH

Reserved

Boot from SPI Serial EEPROM (8-, 16-, or 24-Bit
address range)

Rev. 0

Page 14 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

The BMODE pins of the Reset Configuration Register, sampled
during power-on resets and software-initiated resets, imple-
ment the following modes:

· Execute from 16-bit external memory Execution starts

from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).

· Boot from 8-bit or 16-bit external FLASH memory The

FLASH boot routine located in boot ROM memory space is
set up using Asynchronous Memory Bank 0. All configura-
tion settings are set for the slowest device possible (3-cycle
hold time; 15-cycle R/W access times; 4-cycle setup).

· Boot from SPI serial EEPROM (8, 16, or 24-bit

addressable) The SPI uses the PF2 output pin to select a
single SPI EEPROM device, submits successive read com-
mands at addresses 0x00, 0x0000, and 0x000000 until a
valid 8, 16, or 24-bit addressable EEPROM is detected, and
begins clocking data into the beginning of L1 instruction
memory.

For each of the boot modes, an 10-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.

In addition, bit 4 of the Reset Configuration Register can be set
by application code to bypass the normal boot sequence during
a software reset. For this case, the processor jumps directly to
the beginning of L1 instruction memory.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources.

The assembly language, which takes advantage of the proces-
sor's unique architecture, offers the following advantages:

· Seamlessly integrated DSP/CPU features are optimized for

both 8-bit and 16-bit operations.

· A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.

· All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-
ming model.

· Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.

· Code density enhancements, which include intermixing of

16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.

DEVELOPMENT TOOLS

The ADSP-BF531/2/3 processor is supported with a complete
set of CROSSCORE®

software and hardware development

tools, including Analog Devices emulators and VisualDSP++®

development environment. The same emulator hardware that
supports other Blackfin processors also fully emulates the
ADSP-BF531/2/3 processor.

The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to processor assembly. The processor
has architectural features that improve the efficiency of com-
piled C/C++ code.

The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer's development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.

Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:

· View mixed C/C++ and assembly code (interleaved source

and object information).

· Insert breakpoints.

CROSSCORE is a registered trademark of Analog Devices, Inc.

VisualDSP++ is a registered trademark of Analog Devices, Inc.

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 15 of 56

March 2004

· Set conditional breakpoints on registers, memory,

and stacks.

· Trace instruction execution.

· Perform linear or statistical profiling of program execution.

· Fill, dump, and graphically plot the contents of memory.

· Perform source level debugging.

· Create custom debugger windows.

The VisualDSP++ IDDE lets programmers define and manage
software development. Its dialog boxes and property pages let
programmers configure and manage all of the Blackfin develop-
ment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:

· Control how the development tools process inputs and

generate outputs.

· Maintain a one-to-one correspondence with the tool's

command line switches.

The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
Threads, Critical and Unscheduled regions, Semaphores,
Events, and Device flags. The VDK also supports Priority-based,
Preemptive, Cooperative, and Time-Sliced scheduling
approaches. In addition, the VDK was designed to be scalable. If
the application does not use a specific feature, the support code
for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.

VCSE is Analog Devices technology for creating, using, and
reusing software components (independent modules of sub-
stantial functionality) to quickly and reliably assemble software
applications. Download components from the Web and drop
them into the application. Publish component archives from
within VisualDSP++. VCSE supports component implementa-
tion in C/C++ or assembly language.

Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with existing Linker Definition
File (LDF), allowing the developer to move between the graphi-
cal and textual environments.

Analog Devices emulators use the IEEE 1149.1 JTAG Test
Access Port of the ADSP-BF531/2/3 processor to monitor and
control the target board processor during emulation. The emu-

lator provides full speed emulation, allowing inspection and
modification of memory, registers, and processor stacks. Non-
intrusive in-circuit emulation is assured by the use of the
processor's JTAG interface--the emulator does not affect target
system loading or timing.

In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the Blackfin processor family. Hard-
ware tools include Blackfin processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.

DESIGNING AN EMULATOR COMPATIBLE
PROCESSOR BOARD

The Analog Devices family of emulators are tools that every sys-
tem developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG processor. The emulator
uses the TAP to access the internal features of the processor,
allowing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The proces-
sor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor
system is set running at full speed with no impact on system
timing.

To use these emulators, the target board must include a header
that connects the processor's JTAG port to the emulator.

For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices web site (

www.analog.com

)--

use site search on "EE-68." This document is updated regularly
to keep pace with improvements to emulator support.

Rev. 0

Page 16 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

PIN DESCRIPTIONS

ADSP-BF531/2/3 processor pin definitions are listed in

Table 9

All pins are three-stated during and immediately after reset,
except the Memory Interface, Asynchronous Memory Control,
and Synchronous Memory Control pins, which are driven high.

If BR is active, then the memory pins are also three-stated. All
unused I/O pins have their input buffers disabled with the
exception of the pins that need pullups or pulldowns as noted in
the table footnotes.

In order to maintain maximum functionality and reduce pack-
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function-
ality is shown in italics.

Table 9. Pin Descriptions

Pin Name

I/O Function

Driver Type

Memory Interface

ADDR191

Address Bus for Async/Sync Access

DATA150

I/O Data Bus for Async/Sync Access

ABE10/SDQM10

Byte Enables/Data Masks for Async/Sync Access

Bus Request

Bus Grant

BGH

Bus Grant Hang

Asynchronous Memory Control

AMS30

Bank Select

ARDY

Hardware Ready Control

AOE

Output Enable

ARE

Read Enable

AWE

Write Enable

Synchronous Memory Control

SRAS

Row Address Strobe

SCAS

Column Address Strobe

SWE

Write Enable

SCKE

Clock Enable

CLKOUT

Clock Output

SA10

A10 Pin

SMS

Bank Select

Timers

TMR0

I/O Timer 0

TMR1/PPI_FS1

I/O Timer 1/PPI Frame Sync1

TMR2/PPI_FS2

I/O Timer 2/PPI Frame Sync2

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 17 of 56

March 2004

Parallel Peripheral Interface Port/GPIO

PF0/SPISS

I/O Programmable Flag 0/SPI Slave Select Input

PF1/SPISEL1/TMRCLK

I/O Programmable Flag 1/SPI Slave Select Enable 1/External Timer Reference C

PF2/SPISEL2

I/O Programmable Flag 2/SPI Slave Select Enable 2

PF3/SPISEL3/PPI_FS3

I/O Programmable Flag 3/SPI Slave Select Enable 3/PPI Frame Sync 3

PF4/SPISEL4/PPI15

I/O Programmable Flag 4/SPI Slave Select Enable 4 / PPI 15

PF5/SPISEL5/PPI14

I/O Programmable Flag 5/SPI Slave Select Enable 5 / PPI 14

PF6/SPISEL6/PPI13

I/O Programmable Flag 6/SPI Slave Select Enable 6 / PPI 13

PF7/SPISEL7/PPI12

I/O Programmable Flag 7/SPI Slave Select Enable 7 / PPI 12

PF8/PPI11

I/O Programmable Flag 8/PPI 11

PF9/PPI10

I/O Programmable Flag 9/PPI 10

PF10/PPI9

I/O Programmable Flag 10/PPI 9

PF11/PPI8

I/O Programmable Flag 11/PPI 8

PF12/PPI7

I/O Programmable Flag 12/PPI 7

PF13/PPI6

I/O Programmable Flag 13/PPI 6

PF14/PPI5

I/O Programmable Flag 14/PPI 5

PF15/PPI4

I/O Programmable Flag 15/PPI 4

PPI30

I/O PPI30

PPI_CLK

PPI Clock

Serial Ports

RSCLK0

I/O SPORT0 Receive Serial Clock

RFS0

I/O SPORT0 Receive Frame Sync

DR0PRI

SPORT0 Receive Data Primary

DR0SEC

SPORT0 Receive Data Secondary

TSCLK0

I/O SPORT0 Transmit Serial Clock

TFS0

I/O SPORT0 Transmit Frame Sync

DT0PRI

SPORT0 Transmit Data Primary

DT0SEC

SPORT0 Transmit Data Secondary

RSCLK1

I/O SPORT1 Receive Serial Clock

RFS1

I/O SPORT1 Receive Frame Sync

DR1PRI

SPORT1 Receive Data Primary

DR1SEC

SPORT1 Receive Data Secondary

TSCLK1

I/O SPORT1 Transmit Serial Clock

TFS1

I/O SPORT1 Transmit Frame Sync

DT1PRI

SPORT1 Transmit Data Primary

DT1SEC

SPORT1 Transmit Data Secondary

SPI Port

MOSI

I/O Master Out Slave In

MISO

I/O Master In Slave Out

SCK

I/O SPI Clock

Table 9. Pin Descriptions (Continued)

Pin Name

I/O Function

Driver Type

Rev. 0

Page 18 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

UART Port

UART Receive

UART Transmit

Real Time Clock

RTXI

RTC Crystal Input

RTXO

RTC Crystal Output

JTAG Port

TCK

JTAG Clock

TDO

JTAG Serial Data Out

TDI

JTAG Serial Data In

TMS

JTAG Mode Select

TRST

JTAG Reset

EMU

Emulation Output

Clock

CLKIN

Clock/Crystal Input

XTAL

Crystal Output

Mode Controls

RESET

Reset

NMI

Non-maskable Interrupt

BMODE10

Boot Mode Strap

Voltage Regulator

VROUT10

External FET Drive

Supplies

DDEXT

I/O Power Supply

DDINT

Core Power Supply

DDRTC

Real Time Clock Power Supply

GND

External Ground

Refer to

Figure 26 on Page 39

Figure 30 on Page 40

See

Figure 25

and

Figure 26 on Page 39

This pin should be pulled HIGH when not used.

See

Figure 27

and

Figure 28 on Page 39

See

Figure 29

and

Figure 30 on Page 40

See

Figure 31

and

Figure 32 on Page 40

This pin should always be pulled HIGH through a 4.7K Ohm resistor if booting via the SPI port.

This pin should always be pulled LOW when not used.

This pin should be pulled LOW if the JTAG port will not be used.

Table 9. Pin Descriptions (Continued)

Pin Name

I/O Function

Driver Type

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 19 of 56

March 2004

SPECIFICATIONS

Component specifications are subject to change
without notice.

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

Parameter

Minimum

Nominal

Maximum

Unit

DDINT

Internal Supply Voltage

0.8

1.2

1.32

DDEXT

External Supply Voltage

2.25

2.5 or 3.3

3.6

DDRTC

Real-time Clock Power Supply Voltage

2.25

3.6

High Level Input Voltage

1, 2

@ V

DDEXT

= maximum

The ADSP-BF531/2/3 processor is 3.3 V tolerant (always accepts up to 3.6 V maximum V

), but voltage compliance (on outputs, V

) depends on the input V

DDEXT

, because

(maximum) approximately equals V

DDEXT

(maximum). This 3.3 V tolerance applies to bidirectional pins (DATA150, TMR20, PF150, PPI30, RSCLK10,

TSCLK10, RFS10, TFS10, MOSI, MISO, SCK) and input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC, DR1PRI, DR1SEC, RX, RTXI, TCK, TDI, TMS, TRST,
CLKIN, RESET, NMI, and BMODE10).

Parameter value applies to all input and bidirectional pins except CLKIN.

2.0

3.6

IHCLKIN

High Level Input Voltage

@ V

DDEXT

= maximum

Parameter value applies to CLKIN pin only.

2.2

3.6

Low Level Input Voltage

2, 4

@ V

DDEXT

=minimum

Parameter value applies to all input and bidirectional pins.

0.3

0.6

Parameter

Test Conditions

Minimum

Maximum

Unit

High Level Output Voltage

Applies to output and bidirectional pins.

@ V

DDEXT

=3.0V, I

= 0.5 mA

2.4

Low Level Output Voltage

@ V

DDEXT

=3.0V, I

= 2.0 mA

0.4

High Level Input Current

Applies to input pins except JTAG inputs.

@ V

DDEXT

=maximum, V

= V

maximum

10.0

µA

IHP

High Level Input Current JTAG

Applies to JTAG input pins (TCK, TDI, TMS, TRST).

@ V

DDEXT

=maximum, V

= V

maximum

20.0

µA

Low Level Input Current

@ V

DDEXT

=maximum, V

= 0 V

10.0

µA

OZH

Three-State Leakage Current

Applies to three-statable pins.

@ V

DDEXT

= maximum, V

= V

maximum

10.0

µA

OZL

Three-State Leakage Current

@ V

DDEXT

= maximum, V

= 0 V

10.0

µA

Input Capacitance

5, 6

Applies to all signal pins.

Guaranteed, but not tested.

= 1 MHz, T

MBIENT

= 25°C, V

= 2.5 V

8.0

Rev. 0

Page 20 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in the table may cause perma-
nent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

For proper SDRAM controller operation, the maximum load
capacitance is 50 pF (at 3.3 V) or 30 pF (at 2.5 V) for
ADDR191, DATA150, ABE10/SDQM10, CLKOUT,
SCKE, SA10, SRAS, SCAS, SWE, and SMS.

ESD SENSITIVITY

Parameter

Rating

Internal (Core) Supply Voltage (V

DDINT

)

0.3 V to +1.4 V

External (I/O) Supply Voltage (V

DDEXT

)

0.3 V to +3.8 V

Input Voltage

0.5 V to 3.6 V

Output Voltage Swing

0.5 V to V

DDEXT

+ 0.5 V

Load Capacitance

200 pF

ADSP-BF533 Core Clock (CCLK)

600 MHz

ADSP-BF532/BF531 Core Clock (CCLK)

400 MHz

Peripheral Clock (SCLK)

133 MHz

Storage Temperature Range

65ºC to + 150ºC

Junction Temperature Under Bias

125ºC

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-BF531/2/3 processor features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 21 of 56

March 2004

TIMING SPECIFICATIONS

Table 10

through

Table 14

describe the timing requirements for

the ADSP-BF531/2/3 processor clocks. Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock and system clock as described in

Absolute Maximum

Ratings on Page 20

, and the Voltage Controlled Oscillator

(VCO) operating frequencies described in

Table 13

describes Phase-Locked Loop operating conditions.

Table 10. Core and System Clock Requirements--ADSP-BF533SKBC600

Parameter

Min

Max

Unit

CCLK

Core Cycle Period (V

DDINT

= 1.2 V 5%)

1.67

CCLK

Core Cycle Period (V

DDINT

= 1.1 V 5%)

2.10

CCLK

Core Cycle Period (V

DDINT

= 1.0 V 5%)

2.35

CCLK

Core Cycle Period (V

DDINT

= 0.9 V 5%)

2.66

CCLK

Core Cycle Period (V

DDINT

= 0.8 V )

4.00

SCLK

System Clock Period

Maximum of 7.5 or t

CCLK

Table 11. Core and System Clock Requirements--ADSP-BF533SBBC500 and ADSP-BF533SBBZ500

Parameter

Min

Max

Unit

CCLK

Core Cycle Period (V

DDINT

= 1.2 V 5%)

2.0

CCLK

Core Cycle Period (V

DDINT

= 1.1 V 5%)

2.25

CCLK

Core Cycle Period (V

DDINT

= 1.0 V 5%)

2.50

CCLK

Core Cycle Period (V

DDINT

= 0.9 V 5%)

3.00

CCLK

Core Cycle Period (V

DDINT

= 0.8 V )

4.00

SCLK

System Clock Period

Maximum of 7.5 or t

CCLK

Table 12. Core and System Clock Requirements--ADSP-BF532/531 All Package Types

Parameter

Min

Max

Unit

CCLK

Core Cycle Period (V

DDINT

=1.2 V 5%)

2.5

CCLK

Core Cycle Period (V

DDINT

=1.1 V 5%)

2.75

CCLK

Core Cycle Period (V

DDINT

=1.0 V 5%)

3.00

CCLK

Core Cycle Period (V

DDINT

=0.9 V 5%)

3.25

CCLK

Core Cycle Period (V

DDINT

=0.8 V)

4.0

SCLK

System Clock Period

Maximum of 7.5 or t

CCLK

Table 13. Phase-Locked Loop Operating Conditions

Parameter

Min

Max

Unit

VCO

Voltage Controlled Oscillator (VCO) Frequency

Max CCLK

MHz

Table 14. Maximum SCLK Conditions

Parameter

Condition

DDEXT

= 3.3 V

DDEXT

= 2.5 V

Unit

MBGA

SCLK

DDINT

1.14 V

133

MHz

SCLK

DDINT

1.14 V

100

MHz

LQFP

SCLK

DDINT

1.14 V

133

MHz

SCLK

DDINT

1.14 V

MHz

Set bit 7 (output delay) of PLL_CTL register.

Rev. 0

Page 26 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

External Port Bus Request and Grant Cycle Timing

Table 19

and

Figure 14

describe external port bus request and

bus grant operations.

Table 19. External Port Bus Request and Grant Cycle Timing

Parameter

, 1, 2

Min

Max

Unit

Timing Requirements

BR Asserted to CLKOUT High Setup

4.6

CLKOUT High to BR Deasserted Hold Time

0.0

Switching Characteristics

CLKOUT Low to xMS, Address, and RD/WR disable

4.5

CLKOUT Low to xMS, Address, and RD/WR enable

4.5

DBG

CLKOUT High to BG High Setup

3.6

EBG

CLKOUT High to BG Deasserted Hold Time

3.6

DBH

CLKOUT High to BGH High Setup

3.6

EBH

CLKOUT High to BGH Deasserted Hold Time

3.6

These are preliminary timing parameters that are based on worst-case operating conditions.

The pad loads for these timing parameters are 20 pF.

Figure 14. External Port Bus Request and Grant Cycle Timing

ADDR19-1

AMSx

CLKOUT

AWE

BGH

ARE

ABE1-0

EBG

DBG

EBH

DBH

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 27 of 56

March 2004

Parallel Peripheral Interface Timing

Table 20

and

Figure 15 on Page 27

describe Parallel Peripheral

Interface operations.

Table 20. Parallel Peripheral Interface Timing

Parameter

Min

Max

Unit

Timing Requirements

PCLKW

PPI_CLK Width

6.0

PCLK

PPI_CLK Period

15.0

SFSPE

External Frame Sync Setup Before PPI_CLK

3.0

HFSPE

External Frame Sync Hold After PPI_CLK

3.0

SDRPE

Receive Data Setup Before PPI_CLK

2.0

HDRPE

Receive Data Hold After PPI_CLK

4.0

Switching Characteristics - GP Output and Frame Capture Modes

DFSPE

Internal Frame Sync Delay After PPI_CLK

10.0

HOFSPE

Internal Frame Sync Hold After PPI_CLK

0.0

DDTPE

Transmit Data Delay After PPI_CLK

10.0

HDTPE

Transmit Data Hold After PPI_CLK

0.0

PPI_CLK frequency cannot exceed f

SCLK

Figure 15. GP Output Mode and Frame Capture Timing

DDTPE

HDTPE

PPI_CLK

PPI_FS1

PPIx

DRIVE

EDGE

SAMPLE

EDGE

SFSPE

HFSPE

PCLKW

DFSPE

HOFSPE

PPI_FS2

SDRPE

HDRPE

Rev. 0

Page 28 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

Serial Ports

Table 21

through

Table 26 on Page 29

and

Figure 16 on Page 30

through

Figure 18 on Page 32

describe Serial Port operations.

Table 21. Serial Ports--External Clock

Parameter

Min

Max

Unit

Timing Requirements

SFSE

TFS/RFS Setup Before TSCLK/RSCLK

3.0

HFSE

TFS/RFS Hold After TSCLK/RSCLK

3.0

SDRE

Receive Data Setup Before RSCLK

3.0

HDRE

Receive Data Hold After RSCLK

3.0

SCLKEW

TSCLK/RSCLK Width

4.5

SCLKE

TSCLK/RSCLK Period

15.0

Referenced to sample edge.

Table 22. Serial Ports--Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

SFSI

TFS/RFS Setup Before TSCLK/RSCLK

8.0

HFSI

TFS/RFS Hold After TSCLK/RSCLK

2.0

SDRI

Receive Data Setup Before RSCLK

6.0

HDRI

Receive Data Hold After RSCLK

0.0

SCLKEW

TSCLK/RSCLK Width

4.5

SCLKE

TSCLK/RSCLK Period

15.0

Referenced to sample edge.

Table 23. Serial Ports--External Clock

Parameter

Min

Max

Unit

Switching Characteristics

DFSE

TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)

10.0

HOFSE

TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)

0.0

DDTE

Transmit Data Delay After TSCLK

10.0

HDTE

Transmit Data Hold After TSCLK

0.0

Referenced to drive edge.

Table 24. Serial Ports--Internal Clock

Parameter

Min

Max

Unit

Switching Characteristics

DFS

TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)

3.0

HOFS

TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)

1.0

DDT

Transmit Data Delay After TSCLK

3.0

HDT

Transmit Data Hold After TSCLK

2.0

SCLKIW

TSCLK/RSCLK Width

4.5

Referenced to drive edge.

Rev. 0

Page 30 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

Figure 16. Serial Ports

DDTTE

DTENE

DDTTI

DTENI

DRIVE

EDGE

DRIVE

EDGE

DRIVE

EDGE

DRIVE

EDGE

TSCLK / RSCLK

TSCLK (EXT)

TFS ("LATE", EXT.)

TSCLK (INT)

TFS ("LATE", INT.)

SDRI

RSCLK

RFS

DRIVE

EDGE

SAMPLE

EDGE

HDRI

SFSI

HFSI

DFSE

HOFSE

SCLKIW

DATA RECEIVE- INTERNAL CLOCK

SDRE

DATA RECEIVE- EXTERNAL CLOCK

RSCLK

RFS

DRIVE

EDGE

SAMPLE

EDGE

HDRE

SFSE

HFSE

DFSE

SCLKEW

HOFSE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DDTI

HDTI

TSCLK

TFS

DRIVE

EDGE

SAMPLE

EDGE

SFSI

HFSI

SCLKIW

DFSI

HOFSI

DATA TRANSMIT- INTERNAL CLOCK

DDTE

HDTE

TSCLK

TFS

DRIVE

EDGE

SAMPLE

EDGE

SFSE

HFSE

DFSE

SCLKEW

HOFSE

DATA TRANSMIT- EXTERNAL CLOCK

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 33 of 56

March 2004

Serial Peripheral Interface (SPI) Port
--Master Timing

Table 27

and

Figure 19

describe SPI port master operations.

Table 27. Serial Peripheral Interface (SPI) Port--Master Timing

Parameter

Min

Max

Unit

Timing Requirements

SSPIDM

Data Input Valid to SCK Edge (Data Input Setup)

7.5

HSPIDM

SCK Sampling Edge to Data Input Invalid

1.5

Switching Characteristics

SDSCIM

SPISELx Low to First SCK edge (x =0 or 1)

SCLK

1.5

SPICHM

Serial Clock High period

SCLK

1.5

SPICLM

Serial Clock Low period

SCLK

1.5

SPICLK

Serial Clock Period

SCLK

1.5

HDSM

Last SCK Edge to SPISELx High (x= 0 or 1)

SCLK

1.5

SPITDM

Sequential Transfer Delay

SCLK

1.5

DDSPIDM

SCK Edge to Data Out Valid (Data Out Delay)

HDSPIDM

SCK Edge to Data Out Invalid (Data Out Hold)

1.0

4.0

Figure 19. Serial Peripheral Interface (SPI) Port--Master Timing

SSPIDM

HSPIDM

HDSPIDM

LSB

MSB

HSPIDM

DDSPIDM

MOSI

(OUTPUT)

MISO

(INPUT)

SPISELx

(OUTPUT)

SCK

(CPOL = 0)

(OUTPUT)

SCK

(CPOL = 1)

(OUTPUT)

SPICHM

SPICLM

SPICLK

SPICHM

HDSM

SPITDM

HDSPIDM

LSB VALID

LSB

MSB

MSB VALID

HSPIDM

DDSPIDM

MOSI

(OUTPUT)

MISO

(INPUT)

SSPIDM

CPHA=1

CPHA=0

MSB VALID

SDSCIM

SSPIDM

LSB VALID

Rev. 0

Page 34 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

Serial Peripheral Interface (SPI) Port
--Slave Timing

Table 28

and

Figure 20

describe SPI port slave operations.

Table 28. Serial Peripheral Interface (SPI) Port--Slave Timing

Parameter

Min

Max

Unit

Timing Requirements

SPICHS

Serial Clock High Period

SCLK

1.5

SPICLS

Serial Clock low Period

SCLK

1.5

SPICLK

Serial Clock Period

SCLK

1.5

HDS

Last SCK Edge to SPISS Not Asserted

SCLK

1.5

SPITDS

Sequential Transfer Delay

SCLK

1.5

SDSCI

SPISS Assertion to First SCK Edge

SCLK

1.5

SSPID

Data Input Valid to SCK Edge (Data Input Setup)

1.6

HSPID

SCK Sampling Edge to Data Input Invalid

1.6

Switching Characteristics

DSOE

SPISS Assertion to Data Out Active

DSDHI

SPISS Deassertion to Data High impedance

DDSPID

SCK Edge to Data Out Valid (Data Out Delay)

HDSPID

SCK Edge to Data Out Invalid (Data Out Hold)

Figure 20. Serial Peripheral Interface (SPI) Port--Slave Timing

HSPID

DDSPID

DSDHI

LSB

MSB

MSB VALID

HSPID

DSOE

DDSPID

HDSPID

MISO

(OUTPUT)

MOSI

(INPUT)

SSPID

SPISS

(INPUT)

SCK

(CPOL = 0)

(INPUT)

SCK

(CPOL = 1)

(INPUT)

SDSCI

SPICHS

SPICLS

SPICLK

HDS

SPICHS

SSPID

HSPID

DSDHI

LSB VALID

MSB

MSB VALID

DSOE

DDSPID

MISO

(OUTPUT)

MOSI

(INPUT)

SSPID

LSB VALID

LSB

CPHA=1

CPHA=0

SPITDS

Rev. 0

Page 38 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

JTAG Test And Emulation Port Timing

Table 31

and

Figure 24

describe JTAG port operations.

Table 31. JTAG Port Timing

Parameter

Min

Max

Unit

Timing Requirements

TCK

TCK Period

STAP

TDI, TMS Setup Before TCK High

HTAP

TDI, TMS Hold After TCK High

SSYS

System Inputs Setup Before TCK High

HSYS

System Inputs Hold After TCK High

TRSTW

TRST Pulse Width

(Measured in TCK cycles)

TCK

Switching Characteristics

DTDO

TDO Delay from TCK Low

DSYS

System Outputs Delay After TCK Low

System Inputs =DATA150, ARDY, TMR20, PF150, PPI_CLK, RSCLK01, RFS01, DR0PRI, DR0SEC, TSCLK01, TFS01, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,

RESET, NMI, BMODE10, BR, PP30.

50 MHz maximum

System Outputs=DATA150, ADDR191, ABE10, AOE, ARE, AWE, AMS30, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR20, PF150, RSCLK01, RFS01,

TSCLK01, TFS01, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI30.

Figure 24. JTAG Port Timing

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

TCK

HTAP

STAP

DTDO

SSYS

HSYS

DSYS

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 39 of 56

March 2004

OUTPUT DRIVE CURRENTS

Figure 25

through

Figure 32

show typical current-voltage char-

acteristics for the output drivers of the ADSP-BF531/2/3
processor. The curves represent the current drive capability of
the output drivers as a function of output voltage.

Figure 25. Drive Current A (Low V

DDEXT

)

Figure 26. Drive Current A (High V

DDEXT

)

SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)

150

100

50

100

150

0.5

1.0

1.5

2.0

2.5

3.0

DDEXT

= 2.25V @ 95°C

DDEXT

= 2.50V @ 25°C

DDEXT

= 2.75V @ 40°C

SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)

150

100

50

100

150

0.5

1.0

1.5

2.0

2.5

3.5

3.0

DDEXT

= 2.95V @ 95°C

DDEXT

= 3.30V @ 25°C

DDEXT

= 3.65V @ 40°C

Figure 27. Drive Current B (Low V

DDEXT

)

Figure 28. Drive Current B (High V

DDEXT

)

SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)

150

100

50

100

150

0.5

1.0

1.5

2.0

2.5

3.0

DDEXT

= 2.25V @ 95°C

DDEXT

= 2.50V @ 25°C

DDEXT

= 2.75V @ 40°C

DDEXT

= 2.95V @ 95°C

DDEXT

= 3.30V @ 25°C

DDEXT

= 3.65V @ 40°C

SOURCE VOLTAGE (V)

150

100

50

100

150

0.5

1.0

1.5

2.0

2.5

3.5

3.0

SOURCE CURRENT (mA)

Rev. 0

Page 40 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

Figure 29. Drive Current C (Low V

DDEXT

)

Figure 30. Drive Current C (High V

DDEXT

)

SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)

20

40

60

0.5

1.0

1.5

2.0

2.5

3.0

DDEXT

= 2.25V @ 95°C

DDEXT

= 2.50V @ 25°C

DDEXT

= 2.75V @ 40°C

20

40

60

80

100

SOURCE CURRENT (mA)

DDEXT

= 2.95V @ 95°C

DDEXT

= 3.30V @ 25°C

DDEXT

= 3.65V @ 40°C

0.5

1.0

1.5

2.0

2.5

3.5

3.0

SOURCE VOLTAGE (V)

Figure 31. Drive Current D (Low V

DDEXT

)

Figure 32. Drive Current D (High V

DDEXT

)

SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)

100

60

20

40

80

100

0.5

1.0

1.5

2.0

2.5

3.0

DDEXT

= 2.25V @ 95°C

DDEXT

= 2.50V @ 25°C

DDEXT

= 2.75V @ 40°C

150

100

50

100

150

SOURCE CURRENT (mA)

0.5

1.0

1.5

2.0

2.5

3.5

3.0

SOURCE VOLTAGE (V)

DDEXT

= 2.95V @ 95°C

DDEXT

= 3.30V @ 25°C

DDEXT

= 3.65V @ 40°C

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 41 of 56

March 2004

POWER DISSIPATION

Total power dissipation has two components: one due to inter-
nal circuitry (P

INT

) and one due to the switching of external

output drivers (P

EXT

Table 32

shows the power dissipation for

internal circuitry (V

DDINT

). Internal power dissipation is depen-

dent on the instruction execution sequence and the data
operands involved.

The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:

· Number of output pins (O) that switch during each cycle

· Maximum frequency (f) at which they can switch

· Their load capacitance (C)

· Their voltage swing (V

DDEXT

)

The external component is calculated using:

The frequency f includes driving the load high and then back
low. For example: DATA150 pins can drive high and low at a
maximum rate of 1/(2

SCLK

) while in SDRAM burst mode.

A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:

Note that the conditions causing a worst-case P

EXT

differ from

those causing a worst-case P

INT

. Maximum P

INT

cannot occur

while 100% of the output pins are switching from all ones (1s) to
all zeros (0s). Note, as well, that it is not common for an applica-
tion to have 100% or even 50% of the outputs switching
simultaneously.

Table 32. Internal Power Dissipation

See EE-229: Estimating Power for ADSP-BF533 Blackfin Processors.

Test Conditions

data is specified for typical process parameters. All data at 25ºC.

Parameter

CCLK

50 MHz
V

DDINT

0.8 V

CCLK

400 MHz
V

DDINT

1.2 V

CCLK

500 MHz
V

DDINT

1.2 V

CCLK

600 MHz
V

DDINT

1.2 V

Unit

DDTYP

Processor executing 75% dual Mac, 25% ADD with moderate data bus activity.

26 160 190 220 mA

DDSLEEP

See the ADSP-BF53x Blackfin Processor Hardware Reference Manual for defini-

tions of Sleep and Deep Sleep operating modes.

16 37 37 37 mA

DDDEEPSLEEP

14 31 31 31 mA

DDHIBERNATE

Measured at V

DDEXT

= 3.65V with voltage regulator off (V

DDINT

= 0V).

DDRTC

Measured at V

DDRTC

= 3.3V at 25ºC.

EXT

TOTAL

EXT

DDINT

(

)

Rev. 0

Page 42 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

TEST CONDITIONS

All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section.

Output Enable Time

Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time t

ENA

is the interval from

the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram (

Figure 33

). The time

ENA_MEASURED

is the interval from when the reference signal

switches to when the output voltage reaches 2.0 V (output high)
or 1.0 V (output low). Time t

TRIP

is the interval from when the

output starts driving to when the output reaches the 1.0 V or
2.0 V trip voltage. Time t

ENA

is calculated as shown in the

equation:

If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.

Output Disable Time

Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by

V is dependent on the capacitive load, C

and the

load current, I

. This decay time can be approximated by the

equation:

The output disable time t

DIS

is the difference between

DIS_MEASURED

and t

DECAY

as shown in

Figure 33

. The time

DIS_MEASURED

is the interval from when the reference signal

switches to when the output voltage decays

V from the mea-

sured output high or output low voltage. The time t

DECAY

calculated with test loads C

and I

, and with

V equal to 0.5 V.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,
first calculate t

DECAY

using the equation given above. Choose

V to be the difference between the ADSP-BF531/2/3 proces-

sor's output voltage and the input threshold for the device
requiring the hold time. A typical

V will be 0.4 V. C

is the

total bus capacitance (per data line), and I

is the total leakage or

three-state current (per data line). The hold time will be t

DECAY

plus the minimum disable time (for example, t

DSDAT

for an

SDRAM write cycle).

Capacitive Loading

Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see

Figure 34

Figure 36

through

Figure 43 on

Page 44

show how output rise time varies with capacitance. The

delay and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.

ENA

ENA_MEASURED

TRIP

DECAY

(

)

Figure 33. Output Enable/Disable

Figure 34. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)

Figure 35. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

REFERENCE

SIGNAL

DIS

OUTPUT STARTS DRIVING

(MEASURED)

(MEASURED) +

DIS_MEASURED

(MEASURED)

2.0V

1.0V

(MEASURED)

HIGH IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS

VOLTAGE TO BE APPROXIMATELY 1.5V.

OUTPUT STOPS DRIVING

ENA

DECAY

ENA-MEASURED

TRIP

1.5V

30pF

OUTPUT

PIN

50 OHMS

INPUT

OUTPUT

1.5V

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 43 of 56

March 2004

Figure 36. Typical Output Delay or Hold for Driver A at EVDD

MIN

Figure 37. Typical Output Delay or Hold for Driver A at EVDD

MAX

ABE_B[0] (133 MHZ DRIVER), EVDD

MIN

= 2.25V, TEMPERATURE = 85°C

LOAD CAPACITANCE (PF)

RISE TIME

RISE AND F

ALL

TIME NS (10%-90%)

100

150

200

250

FALL TIME

ABE0 (133 MHZ DRIVER), EVDD

MAX

= 3.65V, TEMPERATURE = 85°C

LOAD CAPACITANCE (PF)

RISE TIME

RISE AND F

ALL

TIME NS (10%-90%)

100

150

200

250

FALL TIME

Figure 38. Typical Output Delay or Hold for Driver B at EVDD

MIN

Figure 39. Typical Output Delay or Hold for Driver B at EVDD

MAX

CLKOUT (CLKOUT DRIVER), EVDD

MIN

= 2.25V, TEMPERATURE = 85°C

LOAD CAPACITANCE (PF)

RISE TIME

RISE AND F

ALL

TIME NS (10%-90%)

100

150

200

250

FALL TIME

CLKOUT (CLKOUT DRIVER), EVDD

MAX

= 3.65V, TEMPERATURE = 85°C

LOAD CAPACITANCE (PF)

RISE TIME

RISE AND F

ALL

TIME NS (10%-90%)

100

150

200

250

FALL TIME

Rev. 0

Page 44 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

Figure 40. Typical Output Delay or Hold for Driver C at EVDD

MIN

Figure 41. Typical Output Delay or Hold for Driver C at EVDD

MAX

TMR0 (33 MHZ DRIVER), EVDD

MIN

= 2.25V, TEMPERATURE = 85°C

LOAD CAPACITANCE (PF)

RISE TIME

RISE AND F

ALL

TIME NS (10%-90%)

100

150

200

250

FALL TIME

TMR0 (33 MHZ DRIVER), EVDD

MAX

= 3.65V, TEMPERATURE = 85°C

LOAD CAPACITANCE (PF)

RISE TIME

RISE AND F

ALL

TIME NS (10%-90%)

100

150

200

250

FALL TIME

Figure 42. Typical Output Delay or Hold for Driver D at EVDD

MIN

Figure 43. Typical Output Delay or Hold for Driver D at EVDD

MAX

SCK (66 MHZ DRIVER), EVDD

MIN

= 2.25V, TEMPERATURE = 85°C

LOAD CAPACITANCE (PF)

RISE TIME

RISE AND F

ALL

TIME NS (10%-90%)

100

150

200

250

FALL TIME

SCK (66 MHZ DRIVER), EVDD

MAX

= 3.65V, TEMPERATURE = 85°C

LOAD CAPACITANCE (PF)

RISE TIME

RISE AND F

ALL

TIME NS (10%-90%)

100

150

200

250

FALL TIME

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 45 of 56

March 2004

ENVIRONMENTAL CONDITIONS

To determine the junction temperature on the application
printed circuit board use:

where:

= Junction temperature ( C)

CASE

= Case temperature ( C) measured by customer at top

center of package.

= From

Table 33

= Power dissipation (see

Power Dissipation on Page 41

for

the method to calculate P

)

Values of

are provided for package comparison and printed

circuit board design considerations.

can be used for a first

order approximation of T

by the equation:

where:

= Ambient temperature ( C)

Table 33

, airflow measurements comply with JEDEC stan-

dards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.

Thermal resistance

Table 33

is the figure of merit relating

to performance of the package and board in a convective envi-
ronment.

JMA

represents the thermal resistance under two

conditions of airflow.

represents the heat extracted from the

periphery of the board.

represents the correlation between

and T

CASE

. Values of

are provided for package compari-

son and printed circuit board design considerations.

Table 33. Thermal Characteristics for BC-160 Package

Parameter

Condition

Typical

Unit

0 Linear m/s Airflow

34.1

C/W

JMA

1 Linear m/s Airflow

30.1

C/W

JMA

2 Linear m/s Airflow

28.8

C/W

Not applicable

25.55

C/W

Not applicable

8.75

C/W

0 Linear m/s Airflow

0.13

C/W

Table 34. Thermal Characteristics for ST-176-1 Package

Parameter

Condition

Typical

Unit

0 Linear m/s Airflow

34.9

C/W

JMA

1 Linear m/s Airflow

33.0

C/W

JMA

2 Linear m/s Airflow

32.0

C/W

0 Linear m/s Airflow

0.50

C/W

1 Linear m/s Airflow

0.75

C/W

2 Linear m/s Airflow

1.00

C/W

CASE

(

)

(

)

Table 35. Thermal Characteristics for B-169 Package

Parameter

Condition

Typical

Unit

0 Linear m/s Airflow

28.6

C/W

JMA

1 Linear m/s Airflow

24.6

C/W

JMA

2 Linear m/s Airflow

23.8

C/W

Not applicable

21.75

C/W

Not applicable

12.7

C/W

0 Linear m/s Airflow

0.78

C/W

Rev. 0

Page 46 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

160-LEAD BGA PINOUT

Table 36

lists the BGA pinout by signal.

Table 37 on Page 47

lists the BGA pinout by ball number.

Table 36. 160-Ball BGA Pin Assignment (Alphabetically by Signal)

Signal

Ball No.

Signal

Ball No.

Signal

Ball No.

Signal

Ball No.

ABE0

H13

DATA12

GND

SCK

ABE1

H12

DATA13

GND

SCKE

B13

ADDR1

J14

DATA14

GND

L10

SMS

C13

ADDR10

M13

DATA15

GND

SRAS

D13

ADDR11

M14

DATA2

GND

M10

SWE

D12

ADDR12

N14

DATA3

GND

P14

TCK

ADDR13

N13

DATA4

MISO

TDI

ADDR14

N12

DATA5

MOSI

TDO

ADDR15

M11

DATA6

NMI

B10

TFS0

ADDR16

N11

DATA7

PF0

TFS1

ADDR17

P13

DATA8

PF1

TMR0

ADDR18

P12

DATA9

PF10

TMR1

ADDR19

P11

DR0PRI

PF11

TMR2

ADDR2

K14

DR0SEC

PF12

TMS

ADDR3

L14

DR1PRI

PF13

TRST

ADDR4

J13

DR1SEC

PF14

TSCLK0

ADDR5

K13

DT0PRI

PF15

TSCLK1

ADDR6

L13

DT0SEC

PF2

ADDR7

K12

DT1PRI

PF3

VDDEXT

ADDR8

L12

DT1SEC

PF4

VDDEXT

ADDR9

M12

EMU

PF5

VDDEXT

C12

AMS0

E14

GND

A10

PF6

VDDEXT

AMS1

F14

GND

A14

PF7

VDDEXT

AMS2

F13

GND

B11

PF8

VDDEXT

F12

AMS3

G12

GND

PF9

VDDEXT

AOE

G13

GND

PPI0

VDDEXT

ARDY

E13

GND

C11

PPI1

VDDEXT

J12

ARE

G14

GND

PPI2

VDDEXT

AWE

H14

GND

PPI3

VDDEXT

L11

P10

GND

PPI_CLK

VDDEXT

BGH

N10

GND

D10

RESET

C10

VDDINT

BMODE0

GND

D11

RFS0

VDDINT

BMODE1

GND

RFS1

VDDINT

E11

D14

GND

F11

RSCLK0

VDDINT

J11

CLKIN

A12

GND

G11

RSCLK1

VDDINT

CLKOUT

B14

GND

RTXI

VDDINT

DATA0

GND

H11

RTXO

VDDRTC

DATA1

GND

VROUT0

A13

DATA10

GND

K11

SA10

E12

VROUT1

B12

DATA11

GND

SCAS

C14

XTAL

A11

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 47 of 56

March 2004

Table 37

lists the BGA pinout by ball number.

Table 36 on

Page 46

lists the BGA pinout by signal.

Figure 44

lists the top view of the BGA ball configuration.

Figure 45

lists the bottom view of the BGA ball configuration.

Table 37. 160-Ball BGA Pin Assignment (Numerically by Ball Number)

Ball No.

Signal

Ball No.

Signal

Ball No.

Signal

Ball No.

Signal

VDDEXT

C13

SMS

DT0PRI

TDI

PF8

C14

SCAS

DT0SEC

GND

PF9

SCK

TFS0

DATA12

PF10

PF0

GND

DATA9

PF11

MOSI

H11

GND

DATA6

PF14

GND

H12

ABE1

DATA3

PPI2

VDDEXT

H13

ABE0

DATA0

RTXO

VDDINT

H14

AWE

M10

GND

RTXI

GND

TSCLK0

M11

ADDR15

A10

GND

DR0SEC

M12

ADDR9

A11

XTAL

VDDEXT

RFS0

M13

ADDR10

A12

CLKIN

D10

GND

VDDEXT

M14

ADDR11

A13

VROUT0

D11

GND

J11

VDDINT

TRST

A14

GND

D12

SWE

J12

VDDEXT

TMS

PF4

D13

SRAS

J13

ADDR4

TDO

PF5

D14

J14

ADDR1

BMODE0

PF6

TFS1

DR0PRI

DATA13

PF7

MISO

TMR2

DATA10

PF12

DT1SEC

DATA7

PF13

VDDINT

GND

DATA4

PPI3

E11

VDDINT

K11

GND

DATA1

PPI1

E12

SA10

K12

ADDR7

N10

BGH

VDDRTC

E13

ARDY

K13

ADDR5

N11

ADDR16

B10

NMI

E14

AMS0

K14

ADDR2

N12

ADDR14

B11

GND

TSCLK1

RSCLK0

N13

ADDR13

B12

VROUT1

DT1PRI

TMR0

N14

ADDR12

B13

SCKE

DR1SEC

VDDEXT

B14

CLKOUT

GND

VDDINT

TCK

PF1

F11

GND

BMODE1

PF2

F12

VDDEXT

GND

DATA15

PF3

F13

AMS2

VDDEXT

DATA14

GND

F14

AMS1

GND

DATA11

GND

RSCLK1

VDDINT

DATA8

PF15

RFS1

L10

GND

DATA5

VDDEXT

DR1PRI

L11

VDDEXT

DATA2

PPI0

VDDEXT

L12

ADDR8

P10

PPI_CLK

G11

GND

L13

ADDR6

P11

ADDR19

C10

RESET

G12

AMS3

L14

ADDR3

P12

ADDR18

C11

GND

G13

AOE

TMR1

P13

ADDR17

C12

VDDEXT

G14

ARE

EMU

P14

GND

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 49 of 56

March 2004

169-BALL PBGA PINOUT

Table

lists the PBGA pinout by signal.

Table

39 on Page 52

lists the PBGA pinout by ball number.

Table 38. 169-Ball PBGA Pin Assignment (Alphabetically by Signal)

Signal

Ball No.

Signal

Ball No.

Signal

Ball No.

Signal

Ball No.

Signal

Ball No.

ABE [0]

H16

DATA [13]

GND

G11

PF [8]

VDD

K12

ABE [1]

H17

DATA [14]

GND

PF [9]

VDD

L12

ADDR [1]

J16

DATA [15]

GND

PPI [0]

VDD

M10

ADDR [10]

N16

DATA [2]

U13

GND

PPI [1]

VDD

M11

ADDR [11]

P17

DATA [3]

T11

GND

H10

PPI [2]

VDD

M12

ADDR [12]

P16

DATA [4]

U12

GND

H11

PPI [3]

VROUT

B12

ADDR [13]

R17

DATA [5]

U11

GND

PPI_CLK

B10

VROUT

B13

ADDR [14]

R16

DATA [6]

T10

GND

RESET

A12

XTAL

A13

ADDR [15]

T17

DATA [7]

U10

GND

RFS0

ADDR [16]

U15

DATA [8]

GND

J10

RFS1

ADDR [17]

T15

DATA [9]

GND

J11

RSCLK0

ADDR [18]

U16

DR0PRI

GND

RSCLK1

ADDR [19]

T14

DR0SEC

GND

RTCVDD

F10

ADDR [2]

J17

DR1PRI

GND

RTXI

A10

ADDR [3]

K16

DR1SEC

GND

K10

RTXO

A11

ADDR [4]

K17

DT0PRI

GND

K11

ADDR [5]

L16

DT0SEC

GND

SA10

B15

ADDR [6]

L17

DT1PRI

GND

SCAS

A16

ADDR [7]

M16

DT1SEC

GND

SCK

ADDR [8]

M17

EMU

GND

L10

SCKE

B14

ADDR [9]

N17

EVDD

GND

L11

SMS

A17

AMS [0]

D17

EVDD

GND

SRAS

A15

AMS [1]

E16

EVDD

GND

T16

SWE

B17

AMS [2]

E17

EVDD

MISO

TCK

AMS [3]

F16

EVDD

MOSI

TDI

AOE

F17

EVDD

NMI

B11

TDO

ARDY

C16

EVDD

PF [0]

TFS0

ARE

G16

EVDD

PF [1]

TFS1

AWE

G17

EVDD

PF [10]

TMR0

T13

EVDD

PF [11]

TMR1

BGH

U17

EVDD

PF [12]

TMR2

BMODE [0]

EVDD

PF [13]

TMS

BMODE [1]

EVDD

PF [14]

TRST

C17

EVDD

PF [15]

TSCLK0

CLKIN

A14

GND

B16

PF [2]

TSCLK1

CLKOUT

D16

GND

F11

PF [3]

DATA [0]

U14

GND

PF [4]

VDD

F12

DATA [1]

T12

GND

PF [5]

VDD

G12

DATA [10]

GND

PF [6]

VDD

H12

DATA [11]

GND

G10

PF [7]

VDD

J12

Rev. 0

Page 50 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

Table

lists the PBGA pinout by ball number.

Table

38 on

Page 51

lists the PBGA pinout by signal.

Table 39. 169-Ball PBGA Pin Assignment (Numerically by Ball Number)

Ball No.

Signal

Ball No.

Signal

Ball No.

Signal

Ball No.

Signal

Ball No.

Signal

PF [4]

D16

CLKOUT

RSCLK1

M12

VDD

DATA [11]

PF [5]

D17

AMS [0]

EVDD

M16

ADDR [7]

DATA [9]

PF [7]

MOSI

GND

M17

ADDR [8]

U10

DATA [7]

PF [9]

MISO

GND

RFS0

U11

DATA [5]

PF [11]

E16

AMS [1]

GND

RSCLK0

U12

DATA [4]

PF [12]

E17

AMS [2]

J10

GND

N16

ADDR [10]

U13

DATA [2]

PF [14]

DT1PRI

J11

GND

N17

ADDR [9]

U14

DATA [0]

PPI [3]

DT1SEC

J12

VDD

TMR2

U15

ADDR [16]

PPI [1]

EVDD

J16

ADDR [1]

TMR1

U16

ADDR [18]

A10

RTXI

EVDD

J17

ADDR [2]

P16

ADDR [12]

U17

BGH

A11

RTXO

EVDD

DT0SEC

P17

ADDR [11]

A12

RESET

EVDD

DT0PRI

TMR0

A13

XTAL

F10

RTCVDD

EVDD

A14

CLKIN

F11

GND

R16

ADDR [14]

A15

SRAS

F12

VDD

GND

R17

ADDR [13]

A16

SCAS

F16

AMS [3]

GND

A17

SMS

F17

AOE

K10

GND

EVDD

PF [2]

TSCLK1

K11

GND

TMS

EVDD

TFS1

K12

VDD

TDO

PF [6]

EVDD

K16

ADDR [3]

BMODE [1]

PF [8]

GND

K17

ADDR [4]

DATA [15]

PF [10]

GND

TFS0

DATA [13]

PF [13]

GND

TSCLK0

DATA [10]

PF [15]

G10

GND

EVDD

DATA [8]

PPI [2]

G11

GND

T10

DATA [6]

PPI [0]

G12

VDD

GND

T11

DATA [3]

B10

PPI_CLK

G16

ARE

GND

T12

DATA [1]

B11

NMI

G17

AWE

L10

GND

T13

B12

VROUT

DR1PRI

L11

GND

T14

ADDR [19]

B13

VROUT

DR1SEC

L12

VDD

T15

ADDR [17]

B14

SCKE

EVDD

L16

ADDR [5]

T16

GND

B15

SA10

GND

L17

ADDR [6]

T17

ADDR [15]

B16

GND

DR0SEC

EMU

B17

SWE

GND

DR0PRI

TRST

PF [1]

H10

GND

EVDD

TDI

PF [3]

H11

GND

EVDD

TCK

C16

ARDY

H12

VDD

EVDD

BMODE [0]

C17

H16

ABE [0]

GND

DATA [14]

SCK

H17

ABE [1]

M10

VDD

DATA [12]

PF [0]

RFS1

M11

VDD

DATA [11]

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0

Page 51 of 56

March 2004

176-LEAD LQFP PINOUT

Table 40

lists the LQFP pinout by signal.

Table 41 on Page 52

lists the LQFP pinout by lead number.

Table 40. 176-Lead LQFP Pin Assignment (Alphabetically by Signal)

Signal

Lead No.

Signal

Lead No.

Signal

Lead No.

Signal

Lead No.

Signal

Lead No.

ABE0

151

DATA11

102

GND

PPI_CLK

VDDEXT

ABE1

150

DATA12

101

GND

PPI0

VDDEXT

ADDR1

149

DATA13

100

GND

PPI1

VDDEXT

107

ADDR10

137

DATA14

GND

PPI2

VDDEXT

118

ADDR11

136

DATA15

GND

PPI3

VDDEXT

134

ADDR12

135

DATA2

114

GND

RESET

VDDEXT

145

ADDR13

127

DATA3

113

GND

106

RFS0

VDDEXT

156

ADDR14

126

DATA4

112

GND

117

RFS1

VDDEXT

171

ADDR15

125

DATA5

110

GND

128

RSCLK0

VDDINT

ADDR16

124

DATA6

109

GND

129

RSCLK1

VDDINT

ADDR17

123

DATA7

108

GND

130

RTXI

VDDINT

ADDR18

122

DATA8

105

GND

131

RTXO

VDDINT

ADDR19

121

DATA9

104

GND

132

VDDINT

111

ADDR2

148

DR0PRI

GND

133

SA10

164

VDDINT

143

ADDR3

147

DR0SEC

GND

144

SCAS

166

VDDINT

157

ADDR4

146

DR1PRI

GND

155

SCK

VDDINT

168

ADDR5

142

DR1SEC

GND

170

SCKE

173

VDDRTC

ADDR6

141

DT0PRI

GND

174

SMS

172

VROUT1

ADDR7

140

DT0SEC

GND

175

SRAS

167

VROUT2

ADDR8

139

DT1PRI

GND

176

SWE

165

XTAL

ADDR9

138

DT1SEC

MISO

TCK

AMS0

161

EMU

MOSI

TDI

AMS1

160

GND

NMI

TDO

AMS2

159

GND

PF0

TFS0

AMS3

158

GND

PF1

TFS1

AOE

154

GND

PF10

TMR0

ARDY

162

GND

PF11

TMR1

ARE

153

GND

PF12

TMR2

AWE

152

GND

PF13

TMS

119

GND

PF14

TRST

BGH

120

GND

PF15

TSCLK0

BMODE0

GND

PF2

TSCLK1

BMODE1

GND

PF3

163

GND

PF4

VDDEXT

CLKIN

GND

PF5

VDDEXT

CLKOUT

169

GND

PF6

VDDEXT

DATA0

116

GND

PF7

VDDEXT

DATA1

115

GND

PF8

VDDEXT

DATA10

103

GND

PF9

VDDEXT

Rev. 0

Page 52 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

Table 41

lists the LQFP pinout by lead number.

Table 40 on

Page 51

lists the LQFP pinout by signal.

Table 41. 176-Lead LQFP Pin Assignment (Numerically by Lead Number)

Lead No.

Signal

Lead No.

Signal

Lead No.

Signal

Lead No.

Signal

Lead No.

Signal

GND

121

ADDR19

161

AMS0

GND

122

ADDR18

162

ARDY

GND

EMU

123

ADDR17

163

VROUT2

GND

TRST

124

ADDR16

164

SA10

VROUT1

VDDEXT

TMS

125

ADDR15

165

SWE

VDDEXT

PF5

TDI

126

ADDR14

166

SCAS

GND

PF4

TDO

127

ADDR13

167

SRAS

GND

PF3

GND

128

GND

168

VDDINT

GND

PF2

GND

129

GND

169

CLKOUT

CLKIN

PF1

GND

130

GND

170

GND

XTAL

PF0

GND

131

GND

171

VDDEXT

VDDINT

GND

132

GND

172

SMS

RESET

SCK

VDDEXT

133

GND

173

SCKE

NMI

MISO

TCK

134

VDDEXT

174

GND

MOSI

BMODE1

135

ADDR12

175

GND

RTXO

GND

BMODE0

136

ADDR11

176

GND

RTXI

VDDEXT

GND

137

ADDR10

VDDRTC

DT1SEC

DATA15

138

ADDR9

GND

DT1PRI

DATA14

139

ADDR8

VDDEXT

TFS1

100

DATA13

140

ADDR7

PPI_CLK

TSCLK1

101

DATA12

141

ADDR6

PPI0

DR1SEC

102

DATA11

142

ADDR5

PPI1

DR1PRI

103

DATA10

143

VDDINT

PPI2

RFS1

104

DATA9

144

GND

VDDINT

RSCLK1

105

DATA8

145

VDDEXT

PPI3

VDDINT

106

GND

146

ADDR4

PF15

DT0SEC

107

VDDEXT

147

ADDR3

PF14

DT0PRI

108

DATA7

148

ADDR2

PF13

TFS0

109

DATA6

149

ADDR1

GND

110

DATA5

150

ABE1

VDDEXT

111

VDDINT

151

ABE0

PF12

TSCLK0

112

DATA4

152

AWE

PF11

DR0SEC

113

DATA3

153

ARE

PF10

DR0PRI

114

DATA2

154

AOE

PF9

RFS0

115

DATA1

155

GND

PF8

RSCLK0

116

DATA0

156

VDDEXT

PF7

TMR2

117

GND

157

VDDINT

PF6

TMR1

118

VDDEXT

158

AMS3

GND

TMR0

119

159

AMS2

GND

VDDINT

120

BGH

160

AMS1

Rev. 0

Page 56 of 56

March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

D03728-0-3/04(0)

ORDERING GUIDE

Part Number

Temperature
Range
(Ambient )

Package Description

Instruction
Rate (Max)

Operating Voltage

ADSP-BF533SKBC600 0ºC to 70ºC

Chip Scale Package Ball Grid Array (mini-BGA) BC-160 600 MHz

1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF533SBBC500 40ºC to 85ºC Chip Scale Package Ball Grid Array (mini-BGA) BC-160 500 MHz

1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF533SBBZ500

Z = Pb-free part.

40ºC to 85ºC Plastic Ball Grid Array (PBGA) B-169

500 MHz

1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF532SBBC400 40ºC to 85ºC Chip Scale Package Ball Grid Array (mini-BGA) BC-160 400 MHz

1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF532SBST400 40ºC to 85ºC Quad Flatpack (LQFP) ST-176-1

400 MHz

1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF532SBBZ400

40ºC to 85ºC Plastic Ball Grid Array (PBGA) B-169

400 MHz

1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF531SBBC400 40ºC to 85ºC Chip Scale Package Ball Grid Array (mini-BGA) BC-160 400 MHz

1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF531SBST400 40ºC to 85ºC Quad Flatpack (LQFP) ST-176-1

400 MHz

1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF531SBBZ400

40ºC to 85ºC Plastic Ball Grid Array (PBGA) B-169

400 MHz

1.2 V internal, 2.5 V or 3.3 V I/O

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADSP-BF532

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADSP-BF532