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Preliminary Technical Data

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Blackfin

Embedded

Symmetric Multi-Processor

ADSP-BF561

Rev. PrC

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781/329-4700

www.analog.com

Fax:781/326-8703

FEATURES

Dual Symmetric 600 Mhz High Performance Blackfin Core
328 KBytes of On-chip Memory (See Memory Info

on Page 3

)

Each Blackfin Core Includes:

Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs,

40-Bit Shifter

RISC-Like Register and Instruction Model for Ease of Pro-

gramming and Compiler-Friendly Support

Advanced Debug, Trace, and Performance- Monitoring
0.8 - 1.2V core V

with On-Chip Voltage Regulation

3.3V and 2.5V Tolerant I/O
256-Ball Mini BGA and 297-Ball PBGA Package Options

PERIPHERALS

Two Parallel Input/Output Peripheral Interface Units Sup-

porting ITU-R 656 Video and Glueless Interface to ADI
Analog Front End ADCs

Two Dual Channel, Full Duplex Synchronous Serial Ports Sup-

porting Eight Stereo I

S Channels

Dual 16 Channel DMA Controllers and one internal memory

DMA controller

12 General Purpose 32-bit Timer/Counters, with PWM

Capability

SPI-Compatible Port
UART with Support for IrDA®
Dual Watchdog Timers
48 Programable Flags
On-Chip Phase Locked Loop Capable of 1x to 63x Frequency

Multiplication

Figure 1. Functional Block Diagram

DMA

EXTERNAL PORT

FLASH/SDRAM CONTROL

BOOT ROM

PAB

EAB

DAB

PPI

VOLTAGE

REGULATOR

JTAG TEST

EMULATION

GPIO

SPI

UART

IRDA®

SPORT0

TIMERS

SPORT1

IMDMA

CONTROLLER

INSTRUCTION

MEMORY

DATA

MEMORY

MMU

L2 SRAM

128 KBYTES

CORE SYSTEM / BUS INTERFACE

INSTRUCTION

MEMORY

DATA

MEMORY

MMU

IRQ CTRL/

TIMER

IRQ CTRL/

TIMER

CONTROLLER2

DMA

CONTROLLER1

Rev. PrC

Page 2 of 52

April 2004

ADSP-BF561

Preliminary Technical Data

TABLE OF CONTENTS

General Description ................................................. 3

Portable Low-Power Architecture ............................. 3

Blackfin Processor Core .......................................... 3

Memory Architecture ............................................ 4

Internal (On-chip) Memory ................................. 4

External (Off-Chip) Memory ................................ 5

I/O Memory Space ............................................. 6

Booting ........................................................... 6

Event Handling ................................................. 6

Core Event Controller (CEC) ................................ 6

System Interrupt Controller (SIC) .......................... 6

Event Control ................................................... 7

DMA Controllers .................................................. 8

WatchDog Timers ................................................ 8

Serial Ports (SPORTs) ............................................ 9

Serial Peripheral Interface (SPI) Ports ........................ 9

UART Port .......................................................... 9

Programmable Flags (PFx) .................................... 10

Timers ............................................................. 10

Parallel Peripheral Interface ................................... 10

General Purpose Mode Descriptions .................... 10

Input Mode .................................................... 10

ITU -R 656 Mode Descriptions ........................... 10

Active Video Only Mode ................................... 10

Vertical Blanking Interval Mode .......................... 11

Entire Field Mode ............................................ 11

Dynamic Power Management ................................ 11

Full-On Operating Mode Maximum Performance . 11

Active Operating Mode Moderate Power Savings .. 11

Hibernate Operating Mode--Maximum Static Power

Savings ....................................................... 11

Sleep Operating Mode High Power Savings ......... 11

Deep Sleep Operating Mode Max. Power Savings .. 11

Power Savings ................................................. 12

Voltage Regulation .............................................. 12

Clock Signals ..................................................... 13

Booting Modes ................................................... 13

Instruction Set Description ................................... 14

Development Tools .............................................. 14

Designing an Emulator-Compatible

Processor Board (Target) ................................... 15

Additional Information ........................................ 15

Pin Descriptions .................................................... 16

Specifications ........................................................ 20

Recommended Operating Conditions ...................... 20

Electrical Characteristics ....................................... 20

Absolute Maximum Ratings ................................... 21

ESD Sensitivity ................................................... 21

Timing Specifications ........................................... 22

Clock and Reset Timing ..................................... 23

Asynchronous Memory Read Cycle Timing ............ 24

Asynchronous Memory Write Cycle Timing ........... 25

SDRAM Interface Timing .................................. 26

External Port Bus Request and Grant Cycle Timing .. 27

Parallel Peripheral Interface Timing ..................... 28

Serial Ports ..................................................... 29

Serial Peripheral Interface (SPI) Port--Master Timing 34

Serial Peripheral Interface (SPI) Port--Slave Timing . 36

Universal Asynchronous Receiver-Transmitter (UART)

Port--Receive and Transmit Timing .................. 38

Timer Cycle Timing .......................................... 39

Programmable Flags Cycle Timing ....................... 40

JTAG Test And Emulation Port Timing ................. 41

Power Dissipation ............................................... 42

Output Drive Currents ......................................... 42

Test Conditions .................................................. 42

Output Enable Time ......................................... 43

Output Disable Time ......................................... 43

Example System Hold Time Calculation ................... 43

Capacitive Loading .............................................. 44

256-ball MBGA Pin Configurations ............................ 45

297-ball PBGA Pin Configurations ............................. 47

Outline Dimensions ................................................ 50

Outline Dimensions ................................................ 51

Ordering Guide ..................................................... 51

REVISION HISTORY

Revision PrC:

· Edits made to pinlists and timing specification.

ADSP-BF561

Preliminary Technical Data

Rev. PrC

Page 3 of 52

April 2004

GENERAL DESCRIPTION

The ADSP-BF561 processor is a high-performance member of
the Blackfin family of products targeting a variety of multimedia
and telecommunications applications. At the heart of this device
are two independent Analog Devices Blackfin processors. These
Blackfin processors combine a dual-MAC state-of-the-art signal
processing engine, the advantage of a clean, orthogonal RISC-
like microprocessor instruction set, and single-instruction, mul-
tiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture. The ADSP-BF561 device integrates
a general purpose set of digital imaging peripherals creating a
complete system on-chip solution for digital imaging and multi-
media applications.

The ADSP-BF561 processor has 328 KBytes of on-chip mem-
ory. Each Blackfin core includes:

· 16K Bytes of Instruction SRAM/Cache

· 16K Bytes of Instruction SRAM

· 32K Bytes of Data SRAM/Cache

· 32K Bytes of Data SRAM

· 4K Bytes of Scratchpad SRAM

Additional on-chip memory peripherals include:

· 128 KBytes of Low Latency On-chip SRAM

· Four Channel Internal Memory DMA Controller

· External Memory controller with glueless support for

SDRAM, SRAM, and Flash

PORTABLE LOW-POWER ARCHITECTURE

Blackfin processors provide world-class power management
and performance for embedded signal processing applications.
Blackfin processors are designed in a low power and low voltage
design methodology and feature Dynamic Power Management.
Dynamic Power Management is the ability to vary both the volt-
age and frequency of operation to significantly lower the overall
power dissipation. This translates into an exponential reduction
in power dissipation providing longer battery life to portable
applications.

BLACKFIN PROCESSOR CORE

As shown in

Figure 2

, each Blackfin core contains two multi-

plier/accumulators (MACs), two 40-bit ALUs, four video ALUs,
and a single shifter. The computational units process 8-bit, 16-
bit, or 32-bit data from the register file.

Figure 2. Blackfin Processor Core

SEQUENCER

ALIGN

DECODE

LOOP BUFFER

DAG0

DAG1

BARREL

SHIFTER

DATA ARITHMETIC UNIT

CONTROL

UNIT

ADDRESS ARITHMETIC UNIT

P4
P3

R7
R6

R5
R4

R3
R2

R1
R0

Rev. PrC

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April 2004

ADSP-BF561

Preliminary Technical Data

Each MAC performs a 16-bit by 16-bit multiply in every cycle,
with an accumulation to a 40-bit result, providing 8 bits of
extended precision. The ALUs perform a standard set of arith-
metic and logical operations. With two ALUs capable of
operating on 16- or 32-bit data, the flexibility of the computa-
tion units covers the signal processing requirements of a varied
set of application needs.

Each of the two 32-bit input registers can be regarded as two 16-
bit halves, so each ALU can accomplish very flexible single 16-
bit arithmetic operations. By viewing the registers as pairs of 16-
bit operands, dual 16-bit or single 32-bit operations can be
accomplished in a single cycle. By further taking advantage of
the second ALU, quad 16-bit operations can be accomplished
simply, accelerating the per cycle throughput.

The powerful 40-bit shifter has extensive capabilities for per-
forming shifting, rotating, normalization, extraction, and
depositing of data. The data for the computational units is
found in a multi-ported register file of sixteen 16-bit entries or
eight 32-bit entries.

A powerful program sequencer controls the flow of instruction
execution, including instruction alignment and decoding. The
sequencer supports conditional jumps and subroutine calls, as
well as zero-overhead looping. A loop buffer stores instructions
locally, eliminating instruction memory accesses for tight
looped code.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from memory. The DAGs
share a register file containing four sets of 32-bit Index, Modify,
Length, and Base registers. Eight additional 32-bit registers pro-
vide pointers for general indexing of variables and stack
locations.

Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. Level 2 (L2) memories are other
memories, on-chip or off-chip, that may take multiple processor
cycles to access. At the L1 level, the instruction memory holds
instructions only. The two data memories hold data, and a dedi-
cated scratchpad data memory stores stack and local variable
information. At the L2 level, there is a single unified memory
space, holding both instructions and data.

In addition, half of L1 instruction memory and half of L1 data
memories may be configured as either Static RAMs (SRAMs) or
caches. The Memory Management Unit (MMU) provides mem-
ory protection for individual tasks that may be operating on the
core and may protect system registers from unintended access.

The architecture provides three modes of operation: User mode,
Supervisor mode, and Emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.

The Blackfin instruction set has been optimized so that 16-bit
op-codes represent the most frequently used instructions,
resulting in excellent compiled code density. Complex DSP
instructions are encoded into 32-bit op-codes, representing fully
featured multifunction instructions. Blackfin processors sup-

port a limited multi-issue capability, where a 32-bit instruction
can be issued in parallel with two 16-bit instructions, allowing
the programmer to use many of the core resources in a single
instruction cycle.

The Blackfin assembly language uses an algebraic syntax for
ease of coding and readability. The architecture has been opti-
mized for use in conjunction with the VisualDSP C/C++
compiler, resulting in fast and efficient software
implementations.

MEMORY ARCHITECTURE

The ADSP-BF561 views memory as a single unified 4G-byte
address space, using 32-bit addresses. All resources including
internal memory, external memory, and I/O control registers
occupy separate sections of this common address space. The
memory portions of this address space are arranged in a hierar-
chical structure to provide a good cost/performance balance of
some very fast, low-latency memory as cache or SRAM very
close to the processor, and larger, lower-cost and performance-
memory systems farther away from the processor. The ADSP-
BF561 memory map is shown in

Figure 3

The L1 memory system in each core is the highest-performance
memory available to each Blackfin core. The L2 memory pro-
vides additional capacity with lower performance. Lastly, the
off-chip memory system, accessed through the External Bus
Interface Unit (EBIU), provides expansion with SDRAM, flash
memory, and SRAM, optionally accessing more than 768M
bytes of physical memory. The memory DMA controllers pro-
vide high-bandwidth data-movement capability. They can
perform block transfers of code or data between the internal
L1/L2 memories and the external memory spaces.

Internal (On-chip) Memory

The ADSP-BF561 has four blocks of on-chip memory providing
high-bandwidth access to the core.

The first is the L1 instruction memory of each Blackfin core
consisting of 16K bytes of 4-way set-associative cache memory
and 16K bytes of SRAM. The cache memory may also be config-
ured as an SRAM. This memory is accessed at full processor
speed. When configured as SRAM, each of the two 16K banks of
memory is broken into 4K sub-banks which can be indepen-
dently accessed by the processor and DMA.

The second on-chip memory block is the L1 data memory of
each Blackfin core which consists of four banks of 16K bytes
each. Two of the L1 data memory banks can be configured as
one way of a two-way set associative cache or as an SRAM. The
other two banks are configured as SRAM. All banks are accessed
at full processor speed. When configured as SRAM, each of the
four 16K banks of memory is broken into 4K sub-banks which
can be independently accessed by the processor and DMA.

The third memory block associated with each core is a 4K-byte
scratchpad SRAM which runs at the same speed as the L1 mem-
ories, but is only accessible as data SRAM (it cannot be
configured as cache memory and is not accessible via DMA).

ADSP-BF561

Preliminary Technical Data

Rev. PrC

Page 5 of 52

April 2004

The fourth on-chip memory system is the L2 SRAM memory
array which provides 128K bytes of high speed SRAM operating
at one half the bandwidth of the core, and slightly longer latency
than the L1 memory banks. The L2 memory is a unified instruc-
tion and data memory and can hold any mixture of code and
data required by the system design. The Blackfin cores share a
dedicated low-latency 64-bit wide data path port into the L2
SRAM memory.

Each Blackfin core processor has its own set of core Memory
Mapped Registers (MMRs) but share the same system MMR
registers and 128 KB L2 SRAM memory.

External (Off-Chip) Memory

The ADSP-BF561 external memory is accessed via the External
Bus Interface Unit (EBIU). This interface provides a glueless
connection to up to four banks of synchronous DRAM

(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.

The PC133-compliant SDRAM controller can be programmed
to interface to up to four banks of SDRAM, with each bank con-
taining between 16M bytes and 128M bytes providing access to
up to 512M bytes of SDRAM. Each bank is independently pro-
grammable and is contiguous with adjacent banks regardless of
the sizes of the different banks or their placement. This allows
flexible configuration and upgradability of system memory
while allowing the core to view all SDRAM as a single, contigu-
ous, physical address space.

The asynchronous memory controller can also be programmed
to control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a

Figure 3. Memory Map

RESERVED

ASYNCMEMORYBANK3

ASYNCMEMORYBANK2

ASYNCMEMORYBANK1

ASYNCMEMORYBANK0

0xFF800000

0xFF701000

0xFF700000

0xFF614000

0xFF504000

0xFF500000

0xFF408000

0xFF404000

0xFF610000

0xFF604000

0xFF600000

0xFF508000

0xFF400000

L1SCRATCHPADSRAM(4K)

L1INSTRUCTIONSRAM/CACHE(16K)

L1INSTRUCTIONSRAM(16K)

L1DATABANKBSRAM/CACHE(16K)

L1DATABANKBSRAM(16K)

L1DATABANKASRAM/CACHE(16K)

L1DATABANKASRAM(16K)

COREAMEMORYMAP

COREBMEMORYMAP

COREMMRREGISTERS

SYSTEMMMRREGISTERS

L1SCRATCHPADSRAM(4K)

RESERVED

L1INSTRUCTIONSRAM/CACHE(16K)

L1INSTRUCTIONSRAM(16K)

L1DATABANKBSRAM/CACHE(16K)

L1DATABANKBSRAM(16K)

L1DATABANKASRAM/CACHE(16K)

L1DATABANKASRAM(16K)

L2SRAM(128K)

BOOTROM

SDRAMBANK3

SDRAMBANK2

SDRAMBANK1

SDRAMBANK0

0xFFE00000

0xFFC00000

0xFFB01000

0xFFB00000

0xFFA14000

0xFFA10000

0xFFA04000

0xFFA00000

0xFF908000

0xFF904000

0xFF900000

0xFF808000

0xFF804000

0xFEB20000

0xFEB00000

0xEF004000

0xEF000000

0x30000000

0x2C000000

0x28000000

0x24000000

0x20000000

0x00000000

RESERVED

INTERNALMEMORY

EXTERNALMEMORY

0xFFFFFFFF

Topof last SDRAMpage

RESERVED

0xFF800000

Rev. PrC

Page 6 of 52

April 2004

ADSP-BF561

Preliminary Technical Data

64M-byte segment regardless of the size of the devices used so
that these banks will only be contiguous if fully populated with
64M bytes of memory.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. On-
chip I/O devices have their control registers mapped into mem-
ory-mapped registers (MMRs) at addresses near the top of the
4G-byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The core MMRs are accessible only by the core and only in
supervisor mode and appear as reserved space by on-chip
peripherals. The system MMRs are accessible by the core in
supervisor mode and can be mapped as either visible or reserved
to other devices, depending on the system protection model
desired.

Booting

The ADSP-BF561 contains a small boot kernel, which config-
ures the appropriate peripheral for booting. If the ADSP-BF561
is configured to boot from boot ROM memory space, the pro-
cessor starts executing from the on-chip boot ROM.

Event Handling

The event controller on the ADSP-BF561 handles all asynchro-
nous and synchronous events to the processor. The ADSP-
BF561 provides event handling that supports both nesting and
prioritization. Nesting allows multiple event service routines to
be active simultaneously. Prioritization ensures that servicing of
a higher-priority event takes precedence over servicing of a
lower-priority event. The controller provides support for five
different types of events:

· Emulation An emulation event causes the processor to

enter emulation mode, allowing command and control of
the processor via the JTAG interface.

· Reset This event resets the processor.

· Non-Maskable Interrupt (NMI) The NMI event can be

generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut
down of the system.

· Exceptions Events that occur synchronously to program

flow, i.e., the exception will be taken before the instruction
is allowed to complete. Conditions such as data alignment
violations, undefined instructions, etc. cause exceptions.

· Interrupts Events that occur asynchronously to program

flow. They are caused by timers, peripherals, input pins,
and an explicit software instruction.

Each event has an associated register to hold the return address
and an associated return-from-event instruction. When an
event is triggered, the state of the processor is saved on the
supervisor stack.

The ADSP-BF561 event controller consists of two stages, the
Core Event Controller (CEC) and the System Interrupt Control-
ler (SIC). The Core Event Controller works with the System
Interrupt Controller to prioritize and control all system events.
Conceptually, interrupts from the peripherals enter into the
SIC, and are then routed directly into the general-purpose inter-
rupts of the CEC.

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG157),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority inter-
rupts (IVG1514) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF561.

Table 1

describes

the inputs to the CEC, identifies their names in the Event Vector
Table (EVT), and lists their priorities.

System Interrupt Controller (SIC)

The System Interrupt Controller provides the mapping and
routing of events from the many peripheral interrupt sources, to
the prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF561 provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writ-
ing the appropriate values into the Interrupt Assignment
Registers (IAR).

Table 2

describes the inputs into the SIC and

the default mappings into the CEC.

Table 1. Core Event Controller (CEC)

Priority
(0 is Highest)

Event Class

EVT Entry

Emulation/Test

EMU

Reset

RST

Non-Maskable NMI

Exceptions

EVX

Global Enable

Hardware Error

IVHW

Core Timer

IVTMR

General Interrupt 7

IVG7

General Interrupt 8

IVG8

General Interrupt 9

IVG9

General Interrupt 10

IVG10

General Interrupt 11

IVG11

General Interrupt 12

IVG12

General Interrupt 13

IVG13

General Interrupt 14

IVG14

General Interrupt 15

IVG15

ADSP-BF561

Preliminary Technical Data

Rev. PrC

Page 7 of 52

April 2004

Event Control

The ADSP-BF561 provides the user with a very flexible mecha-
nism to control the processing of events. In the CEC, three
registers are used to coordinate and control events. Each of the
registers, as follows, is 16-bits wide, while each bit represents a
particular event class:

· CEC Interrupt Latch Register (ILAT) The ILAT register

indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
may be written only when its corresponding IMASK bit is
cleared.

· CEC Interrupt Mask Register (IMASK) The IMASK reg-

ister controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event
thereby preventing the processor from servicing the event
even though the event may be latched in the ILAT register.
This register may be read from or written to while in super-
visor mode. (Note that general-purpose interrupts can be
globally enabled and disabled with the STI and CLI instruc-
tions, respectively.)

· CEC Interrupt Pending Register (IPEND) The IPEND

register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.

Table 2. Peripheral Interrupt Source Reset State

Peripheral Interrupt Source

Chan

IVG

PLL wakeup

IVG07

DMA1 Error

IVG07

DMA2 Error

IVG07

IMDMA Error

IVG07

PPI1 Error

IVG07

PPI2 Error

IVG07

SPORT0 Error

IVG07

SPORT1 Error

IVG07

SPI Error

IVG07

UART Error

IVG07

Reserved

IVG07

DMA1 0 interrupt

IVG08

DMA1 1 interrupt

IVG08

DMA1 2 interrupt

IVG08

DMA1 3 interrupt

IVG08

DMA1 4 interrupt

IVG08

DMA1 5 interrupt

IVG08

DMA1 6 interrupt

IVG08

DMA1 7 interrupt

IVG08

DMA1 8 interrupt

IVG08

DMA1 9 interrupt

IVG08

DMA1 10 interrupt

IVG08

DMA1 11 interrupt

IVG08

DMA2 0 interrupt

IVG09

DMA2 1 interrupt

IVG09

DMA2 2 interrupt

IVG09

DMA2 3 interrupt

IVG09

DMA2 4 interrupt

IVG09

DMA2 5 interrupt

IVG09

DMA2 6 interrupt

IVG09

DMA2 7 interrupt

IVG09

DMA2 8 interrupt

IVG09

DMA2 9 interrupt

IVG09

DMA2 10 interrupt

IVG09

DMA2 11 interrupt

IVG09

Timer0 interrupt

IVG10

Timer1 interrupt

IVG10

Timer2 interrupt

IVG10

Timer3 interrupt

IVG10

Timer4 interrupt

IVG10

Timer5 interrupt

IVG10

Timer6 interrupt

IVG10

Timer7 interrupt

IVG10

Timer8 interrupt

IVG10

Timer9 interrupt

IVG10

Timer10 interrupt

IVG10

Timer11 interrupt

IVG10

FIO0 interrupt A

IVG11

FIO0 interrupt B

IVG11

FIO1 interrupt A

IVG11

FIO1 interrupt B

IVG11

FIO2 interrupt A

IVG11

FIO2 interrupt B

IVG11

DMA1 write/read 0 interrupt

IVG08

DMA1 write/read1 interrupt

IVG08

DMA2 write/read 0 interrupt

IVG09

DMA2 write/read 1 interrupt

IVG09

IMDMA write/read 0 interrupt

IVG12

IMDMA write/read 1 interrupt

IVG12

Watchdog Timer

IVG13

Reserved

IVG07

Reserved

IVG07

Supplemental 0

IVG07

Supplemental 1

IVG07

Peripheral Interrupt Channel Number

Default User IVG Interrupt

Table 2. Peripheral Interrupt Source Reset State (Continued)

Peripheral Interrupt Source

Chan

IVG

Rev. PrC

Page 8 of 52

April 2004

ADSP-BF561

Preliminary Technical Data

The SIC allows further control of event processing by providing
six 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in

Table 2

· SIC Interrupt Mask Register (SIC_IMASK0, SIC_IMASK1)

This register controls the masking and unmasking of
each peripheral interrupt event. When a bit is set in the reg-
ister, that peripheral event is unmasked and will be
processed by the system when asserted. A cleared bit in the
register masks the peripheral event thereby preventing the
processor from servicing the event.

· SIC Interrupt Status Register (SIC_ISTAT0, SIC_ISTAT1)

As multiple peripherals can be mapped to a single event,
this register allows the software to determine which periph-
eral event source triggered the interrupt. A set bit indicates
the peripheral is asserting the interrupt, a cleared bit indi-
cates the peripheral is not asserting the event.

· SIC Interrupt Wakeup Enable Register (SIC_IWR0,

SIC_IWR1) By enabling the corresponding bit in this reg-
ister, each peripheral can be configured to wake up the
processor, should the processor be in a powered down
mode when the event is generated. (

For more information,

see Dynamic Power Management on Page 11.

)

Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the mode of the processor.

DMA CONTROLLERS

The ADSP-BF561 has multiple, independent DMA controllers
that support automated data transfers with minimal overhead
for the DSP core. DMA transfers can occur between the ADSP-
BF561's internal memories and any of its DMA-capable periph-
erals. Additionally, DMA transfers can be accomplished
between any of the DMA-capable peripherals and external
devices connected to the external memory interfaces, including
the SDRAM controller and the asynchronous memory control-
ler. DMA-capable peripherals include the SPORTs, SPI port,
UART, and PPI. Each individual DMA-capable peripheral has
at least one dedicated DMA channel.

The ADSP-BF561 DMA controllers support both 1-dimen-
sional (1D) and 2-dimensional (2D) DMA transfers. DMA
transfer initialization can be implemented from registers or
from sets of parameters called descriptor blocks.

The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to +/- 32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.

Examples of DMA types supported by the ADSP-BF561 DMA
controllers include:

· A single, linear buffer that stops upon completion

· A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

· 1-D or 2-D DMA using a linked list of descriptors

· 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page

In addition to the dedicated peripheral DMA channels, each
DMA Controller has four memory DMA channels provided for
transfers between the various memories of the ADSP-BF561
system. These enable transfers of blocks of data between any of
the memories--including external SDRAM, ROM, SRAM, and
flash memory--with minimal processor intervention. Memory
DMA transfers can be controlled by a very flexible descriptor-
based methodology or by a standard register-based autobuffer
mechanism.

Further, the ADSP-BF561 has a four channel Internal Memory
DMA (IMDMA) Controller. The IMDMA Controller allows
data transfers between any of the internal L1 and L2 memories.

WATCHDOG TIMERS

Each ADSP-BF561 core includes a 32-bit timer, which can be
used to implement a software watchdog function. A software
watchdog can improve system availability by forcing the proces-
sor to a known state, via generation of a hardware reset, non-
maskable interrupt (NMI), or general- purpose interrupt, if the
timer expires before being reset by software. The programmer
initializes the count value of the timer, enables the appropriate
interrupt, then enables the timer. Thereafter, the software must
reload the counter before it counts to zero from the pro-
grammed value. This protects the system from remaining in an
unknown state where software, which would normally reset the
timer, has stopped running due to an external noise condition
or software error.

After a reset, software can determine if the watchdog was the
source of the hardware reset by interrogating a status bit in the
timer control register, which is set only upon a watchdog gener-
ated reset.

The timer is clocked by the system clock (SCLK), at a maximum
frequency of SCLK.

ADSP-BF561

Preliminary Technical Data

Rev. PrC

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April 2004

SERIAL PORTS (SPORTS)

The ADSP-BF561 incorporates two dual-channel synchronous
serial ports (SPORT0 and SPORT1) for serial and multiproces-
sor communications. The SPORTs support the following
features:

· I

S capable operation.

· Bidirectional operation Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels
of I

S stereo audio.

· Buffered (8-deep) transmit and receive ports Each port

has a data register for transferring data words to and from
other DSP components and shift registers for shifting data
in and out of the data registers.

· Clocking Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies
ranging from (f

SCLK

/131,070) Hz to (f

SCLK

/2) Hz.

· Word length Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most-significant-bit
first or least-significant-bit first.

· Framing Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulsewidths and early or late
frame sync.

· Companding in hardware Each SPORT can perform

A-law or µ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.

· DMA operations with single-cycle overhead Each SPORT

can automatically receive and transmit multiple buffers of
memory data. The DSP can link or chain sequences of
DMA transfers between a SPORT and memory.

· Interrupts Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.

· Multichannel capability Each SPORT supports 128 chan-

nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORTS

The ADSP-BF561 has one SPI-compatible ports that enable the
processor to communicate with multiple SPI-compatible
devices.

The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSIx, and Master Input-
Slave Output, MISO) and a clock pin (Serial Clock, SCK). One
SPI chip select input pin (SPISS) let other SPI devices select the
DSP, and seven SPI chip select output pins (SPISEL71) let the
DSP select other SPI devices. The SPI select pins are reconfig-
ured Programmable Flag pins. Using these pins, the SPI ports

provide a full duplex, synchronous serial interface, which sup-
ports both master and slave modes and multimaster
environments.

Each SPI port's baud rate and clock phase/polarities are pro-
grammable (see SPI Clock Rate equation), and each has an
integrated DMA controller, configurable to support transmit or
receive data streams. The SPI's DMA controller can only service
unidirectional accesses at any given time.

During transfers, the SPI ports simultaneously transmit and
receive by serially shifting data in and out on their two serial
data lines. The serial clock line synchronizes the shifting and
sampling of data on the two serial data lines.

UART PORT

The ADSP-BF561 provides a full duplex Universal Asynchro-
nous Receiver/Transmitter (UART) ports (UART0 and
UART1) fully compatible with PC-standard UARTs. The UART
ports provide a simplified UART interface to other peripherals
or hosts, supporting full duplex, DMA supported, asynchronous
transfers of serial data. Each UART port includes support for 5
to 8 data bits; 1 or 2 stop bits; and none, even, or odd parity. The
UART ports support two modes of operation, as follows:

· PIO (Programmed I/O) The processor sends or receives

data by writing or reading I/O-mapped UATX or UARX
registers, respectively. The data is double-buffered on both
transmit and receive.

· DMA (Direct Memory Access) The DMA controller

transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower priority than most DMA chan-
nels because of their relatively low service rates.

Each UART port's baud rate (see UART Clock Rate equation),
serial data format, error code generation and status, and inter-
rupts are programmable. In the UART Clock Rate equation, the
divisor (D) can be 1 to 65536.

The UART programmable features include:

· Supporting bit rates ranging from (f

SCLK

/ 1048576) to

SCLK

/16) bits per second.

· Supporting data formats from 7 to12 bits per frame.

· Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

In conjunction with the general-purpose timer functions, auto-
baud detection is supported.

SPI Clock Rate

SCLK

2 SPIBAUD

-----------------------------------

UART Clock Rate

SCLK

16 D

----------------

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ADSP-BF561

Preliminary Technical Data

The capabilities of UART0 are further extended with support
for the InfraRed Data Association (IrDA®) Serial InfraRed Phys-
ical Layer Link Specification (SIR) protocol.

PROGRAMMABLE FLAGS (PFX)

The ADSP-BF561 has 48 bi-directional, general-purpose I/O,
Programmable Flag (PF470) pins. The Programmable Flag
pins have special functions for SPI port operation. Each pro-
grammable flag can be individually controlled as follows by
manipulation of the flag control, status, and interrupt registers:

· Flag Direction Control Register Specifies the direction of

each individual PFx pin as input or output.

· Flag Control and Status Registers Rather than forcing the

software to use a read-modify-write process to control the
setting of individual flags, the ADSP-BF561 employs a
"write one to set" and "write one to clear" mechanism that
allows any combination of individual flags to be set or
cleared in a single instruction, without affecting the level of
any other flags. Two control registers are provided, one
register is written to in order to set flag values while
another register is written to in order to clear flag values.
Reading the flag status register allows software to interro-
gate the sense of the flags.

· Flag Interrupt Mask Registers The Flag Interrupt Mask

Registers allow each individual PFx pin to function as an
interrupt to the processor. Similar to the Flag Control Reg-
isters that are used to set and clear individual flag values,
one Flag Interrupt Mask Register sets bits to enable inter-
rupt function, and the other Flag Interrupt Mask register
clears bits to disable interrupt function. PFx pins defined as
inputs can be configured to generate hardware interrupts,
while output PFx pins can be configured to generate soft-
ware interrupts.

· Flag Interrupt Sensitivity Registers The Flag Interrupt

Sensitivity Registers specify whether individual PFx pins
are level- or edge-sensitive and specify-if edge-sensitive-
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.

TIMERS

There are fourteen (14) programmable timer units in the ADSP-
BF561. Twelve general-purpose timers have an external pin that
can be configured either as a Pulse Width Modulator (PWM) or
timer output, as an input to lock the timer, or for measuring
pulse widths of external events. Each of the twelve general-pur-
pose timer units can be independently programmed as a PWM,
internally or externally clocked timer, or pulse width counter.
The general-purpose timer units can be used in conjunction
with the UART to measure the width of the pulses in the data
stream to provide an auto-baud detect function for a serial
channel.

The general-purpose timers can generate interrupts to the pro-
cessor core providing periodic events for synchronization,
either to the processor clock or to a count of external signals. In

addition to the twelve general-purpose programmable timers,
another timer is also provided for each core. These extra timers
are clocked by the internal processor clock (CCLK) and is typi-
cally used as a system tick clock for generation of operating
system periodic interrupts.

PARALLEL PERIPHERAL INTERFACE

The processor provides two Parallel Peripheral Interfaces (PPI)
that can connect directly to parallel A/D and D/A converters,
ITU-R-601/656 video encoders and decoders, and other general
purpose peripherals. Each PPI consists of a dedicated input
clock pin, up to 3 frame synchronization pins, and up to 16 data
pins.

In ITU-R 656 mode, the PPI receives and parses a data stream of
8- bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information is
supported.

General Purpose Mode Descriptions

The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:

· Data Receive with Internally Generated Frame Syncs.

· Data Receive with Externally Generated Frame Syncs.

· Data Transmit with Internally Generated Frame Syncs.

· Data Transmit with Externally Generated Frame Syncs.

Input Mode

These modes support ADC/DAC connections, as well as video
communication with hardware signaling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception / transmission of data.

ITU -R 656 Mode Descriptions

Three distinct ITU-R 656 modes are supported:

· Active Video Only Mode

· Vertical Blanking Only Mode

· Entire Field Mode

Active Video Only Mode

In this mode, the PPI does not read in any data between the End
of Active Video (EAV) and Start of Active Video (SAV) pream-
ble symbols, or any data present during the vertical blanking
intervals. In this mode, the control byte sequences are not stored
to memory; they are filtered by the PPI.

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval
(VBI) data, as well as horizontal blanking information and con-
trol byte sequences on VBI lines.

ADSP-BF561

Preliminary Technical Data

Rev. PrC

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April 2004

Entire Field Mode

In this mode, the entire incoming bitstream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and ver-
tical blanking intervals.

Though not explicitly supported, ITU,-656 output functionality
can be achieved by setting up the entire frame structure (includ-
ing active video, blanking and control information) in memory
and streaming the data out of the PPI in a frame sync-less mode.
The processor's 2D DMA features facilitate this transfer by
allowing the static frame buffer (blanking and control codes) to
be placed in memory once, and simply updating the active video
information on per-frame basis.

DYNAMIC POWER MANAGEMENT

The ADSP-BF561 provides four operating modes, each with a
different performance/power profile. In addition, Dynamic
Power Management provides the control functions to dynami-
cally alter the processor core supply voltage, further reducing
power dissipation. Control of clocking to each of the ADSP-
BF561 peripherals also reduces power consumption. See

Table 3

for a summary of the power settings for each mode.

Full-On Operating Mode Maximum Performance

In the Full-On mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the default execution state in which maximum performance
can be achieved. The processor cores and all enabled peripherals
run at full speed.

Active Operating Mode Moderate Power Savings

In the Active mode, the PLL is enabled but bypassed. Because
the PLL is bypassed, the processor's core clock (CCLK) and sys-
tem clock (SCLK) run at the input clock (CLKIN) frequency. In
this mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the Full-On mode is
entered. DMA access is available to appropriately configured L1
memories.

In the Active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the Full-On or Sleep modes.

Hibernate Operating Mode--Maximum Static Power
Savings

The Hibernate mode maximizes static power savings by dis-
abling the voltage and clocks to the processor core (CCLK) and
to all the synchronous peripherals (SCLK). The internal voltage
regulator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (V

DDINT

) to 0 V to provide the lowest static power

dissipation. Any critical information stored internally (memory
contents, register contents, etc.) must be written to a non-vola-
tile storage device prior to removing power if the processor state
is to be preserved. Since V

DDEXT

is still supplied in this mode, all

of the external pins tri-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
have power still applied without drawing unwanted current.
The internal supply regulator can be woken up by asserting the
RESET pin.

Sleep Operating Mode--High Dynamic Power Savings

The Sleep mode reduces power dissipation by disabling the
clock to the processor core (CCLK). The PLL and system clock
(SCLK), however, continue to operate in this mode. Typically an
external event will wake up the processor. When in the Sleep
mode, assertion of wakeup will cause the processor to sense the
value of the BYPASS bit in the PLL Control register (PLL_CTL).

When in the Sleep mode, system DMA access to L1 memory is
not supported.

Deep Sleep Operating Mode--Maximum Dynamic Power
Savings

The Deep Sleep mode maximizes power savings by disabling the
clocks to the processor cores (CCLK) and to all synchronous
peripherals (SCLK). Asynchronous peripherals will not be able
to access internal resources or external memory. This powered-
down mode can only be exited by assertion of the reset interrupt
(RESET). If BYPASS is disabled, the processor will transition to
the Full On mode. If BYPASS is enabled, the processor will tran-
sition to the Active mode.

Power Savings

As shown in

Table 4

, the ADSP-BF561 supports two different

power domains. The use of multiple power domains maximizes
flexibility, while maintaining compliance with industry stan-
dards and conventions. By isolating the internal logic of the
ADSP-BF561 into its own power domain, separate from the I/O,

Table 3. Power Settings

Mode

PLL

PLL
Bypassed

Core
Clock
(CCLK)

System
Clock
(SCLK)

Core
Power

Full On

Enabled

Enabled Enabled On

Active

Enabled/
Disabled

Yes

Enabled Enabled On

Sleep

Enabled

Disabled Enabled On

Deep Sleep Disabled

Disabled Disabled On

Hibernate

Disabled

Disabled Disabled Off

Table 3. Power Settings (Continued)

Mode

PLL

PLL
Bypassed

Core
Clock
(CCLK)

System
Clock
(SCLK)

Core
Power

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ADSP-BF561

Preliminary Technical Data

the processor can take advantage of Dynamic Power Manage-
ment, without affecting the I/O devices. There are no
sequencing requirements for the various power domains.

The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.

The Dynamic Power Management feature of the ADSP-BF561
allows both the processor's input voltage (V

DDINT

) and clock

frequency (f

CCLK

) to be dynamically controlled.

The savings in power dissipation can be modeled using the
Power Savings Factor and % Power Savings calculations.

The Power Savings Factor is calculated as:

where the variables in the equations are:

· f

CCLKNOM

is the nominal core clock frequency

· f

CCLKRED

is the reduced core clock frequency

· V

DDINTNOM

is the nominal internal supply voltage

· V

DDINTRED

is the reduced internal supply voltage

· T

NOM

is the duration running at f

CCLKNOM

· T

RED

is the duration running at f

CCLKRED

The percent power savings is calculated as:

VOLTAGE REGULATION

The ADSP-BF561 processor provides an on-chip voltage regula-
tor that can generate processor core voltage levels 0.85V(-5% /
+10%) to 1.2V(-5% / +10%) from an external 2.25 V to 3.6 V
supply.

Figure 4

shows the typical external components

required to complete the power management system. The regu-
lator controls the internal logic voltage levels and is
programmable with the Voltage Regulator Control Register
(VR_CTL) in increments of 50 mV. To reduce standby power
consumption, the internal voltage regulator can be programmed
to remove power to the processor core while keeping I/O power
(V

DDEXT

) supplied. While in hibernation, V

DDEXT

can still be

applied, eliminating the need for external buffers. The voltage
regulator can be activated from this powerdown state by assert-
ing RESET, which will then initiate a boot sequence. The
regulator can also be disabled and bypassed at the user's
discretion.

Table 4. ADSP-BF561 Power Domains

Power Domain

VDD Range

All internal logic

DDINT

I/O

DDEXT

Figure 4. Voltage Regulator Circuit

Power Savings Factor

CCLKRED

CCLKNOM

---------------------

DDINTRED

DDINTNOM

--------------------------

RED

NOM

-------------

% Power Savings

1 Power Savings Factor

(

) 100%

ADSP-BF561

Preliminary Technical Data

Rev. PrC

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April 2004

CLOCK SIGNALS

The ADSP-BF561 can be clocked by an external crystal, a sine
wave input, or a buffered, shaped clock derived from an external
clock oscillator.

If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor's CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.

Alternatively, because the ADSP-BF561 includes an on-chip
oscillator circuit, an external crystal may be used. The crystal
should be connected across the CLKIN and XTAL pins, with
two capacitors connected as shown in

Figure 5

Capacitor values are dependent on crystal type and should be
specified by the crystal manufacturer. A parallel-resonant, fun-
damental frequency, microprocessor-grade crystal should be
used.

As shown in

Figure 6

, the core clock (CCLK) and system

peripheral clock (SCLK) are derived from the input clock
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user programmable 1x to 63x multiplication
factor. The default multiplier is 10x, but it can be modified by a
software instruction sequence. On-the-fly frequency changes
can be effected by simply writing to the PLL_DIV register.

All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL30 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.

Table 5

illustrates typical system clock ratios:

The maximum frequency of the system clock is f

SCLK

. Note that

the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of f

SCLK

. The SSEL value can be changed

dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).

The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL[10] bits of the PLL_DIV regis-
ter. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown
in

Table 6

. This programmable core clock capability is useful for

fast core frequency modifications.

BOOTING MODES

The ADSP-BF561 has three mechanisms (listed in

Table 7

) for

automatically loading internal L1 instruction memory after a
reset. A fourth mode is provided to execute from external mem-
ory, bypassing the boot sequence.

Figure 5. External Crystal Connections

Figure 6. Frequency Modification Methods

CLKIN

CLKOUT

XTAL

PLL

× - 63×

× 1:15

× 1, 2, 4, 8

VCO

SCLK

CCLK

SCLK

133 MHZ

CLKI N

"FI NE" ADJUSTMENT

REQUI RES PLL SEQ UENCING

"CO ARSE" ADJUSTMENT

ON-THE-FLY

CCLK

SCLK

Table 5. Example System Clock Ratios

Signal Name
SSEL[30]

Divider Ratio
VCO/SCLK

Example Frequency Ratios
(MHz)

VCO

SCLK

0001

1:1

100

0110

6:1

300

1010

10:1

500

Table 6. Core Clock Ratios

Signal Name
CSEL[10]

Divider Ratio
VCO/CCLK

Example Frequency Ratios

VCO

CCLK

1:1

500

2:1

500

250

4:1

200

8:1

200

Table 7. Booting Modes

BMODE10

Description

Execute from 16-bit external memory (Bypass
Boot ROM)

Boot from 8/16-bit flash

Reserved

Boot from SPI serial ROM (16-bit address
range)

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ADSP-BF561

Preliminary Technical Data

The BMODE pins of the Reset Configuration Register, sampled
during power-on resets and software-initiated resets, imple-
ment the following modes:

· Execute from 16-bit external memory - Execution starts

from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time,
15-cycle R/W access times, 4-cycle setup).

· Boot from 8/16-bit external FLASH memory The 8/16-bit

FLASH boot routine located in boot ROM memory space is
set up using Asynchronous Memory Bank 0. All configura-
tion settings are set for the slowest device possible (3-cycle
hold time; 15-cycle R/W access times; 4-cycle setup).

· Boot from SPI serial EEPROM (16-bit addressable) The

SPI uses the PF2 output pin to select a single SPI EPROM
device, submits a read command at address 0x0000, and
begins clocking data into the beginning of L1 instruction
memory. A 16-bit addressable SPI-compatible EPROM
must be used.

For each of the boot modes, a boot loading protocol is used to
transfer program and data blocks, from an external memory
device, to their specified memory locations. Multiple memory
blocks may be loaded by any boot sequence. Once all blocks are
loaded, Core A program execution commences from the start of
L1 instruction SRAM (0xFFA0 0000). Core B remains in a held-
off state until a certain register bit is cleared. After that, Core B
will start execution at address 0xFF60 0000.

In addition, bit 4 of the Reset Configuration Register can be set
by application code to bypass the normal boot sequence during
a software reset. For this case, the processor jumps directly to
the beginning of L1 instruction memory.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set
employs an algebraic syntax that was designed for ease of coding
and readability. The instructions have been specifically tuned to
provide a flexible, densely encoded instruction set that compiles
to a very small final memory size. The instruction set also pro-
vides fully featured multifunction instructions that allow the
programmer to use many of the processor core resources in a
single instruction. Coupled with many features more often seen
on microcontrollers, this instruction set is very efficient when
compiling C and C++ source code. In addition, the architecture
supports both a user (algorithm/application code) and a super-
visor (O/S kernel, device drivers, debuggers, ISRs) mode of
operations, allowing multiple levels of access to core processor
resources.

The assembly language, which takes advantage of the proces-
sor's unique architecture, offers the following advantages:

· Seamlessly integrated DSP/CPU features are optimized for

both 8-bit and 16-bit operations.

· A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.

· All registers, I/O, and memory are mapped into a unified

4G-byte memory space providing a simplified program-
ming model.

· Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and ker-
nel stack pointers.

· Code density enhancements, which include intermixing of

16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded as
16-bits.

DEVELOPMENT TOOLS

The ADSP-BF561 is supported with a complete set of
CROSSCORE

software and hardware development tools,

including Analog Devices emulators and the VisualDSP++®
development environment. The same emulator hardware that
supports other Analog Devices processors also fully emulates
the ADSP-BF561.

The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy-to-use assembler that is based on an algebraic
syntax, an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ run-time library that includes DSP and mathemat-
ical functions. A key point for these tools is C/C++ code
efficiency. The compiler has been developed for efficient trans-
lation of C/C++ code to Blackfin assembly. The Blackfin
processor has architectural features that improve the efficiency
of compiled C/C++ code.

The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer's development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to non intrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.

Debugging both C/C++ and assembly programs with the Visu-
alDSP++ debugger, programmers can:

· View mixed C/C++ and assembly code (interleaved source

and object information)

· Insert breakpoints

· Set conditional breakpoints on registers, memory, and

stacks

· Trace instruction execution

· Perform linear or statistical profiling of program execution

ADSP-BF561

Preliminary Technical Data

Rev. PrC

Page 15 of 52

April 2004

· Fill, dump, and graphically plot the contents of memory

· Perform source level debugging

· Create custom debugger windows

The VisualDSP++ IDE lets programmers define and manage
software development. Its dialog boxes and property pages let
programmers configure and manage all development tools,
including Color Syntax Highlighting in the VisualDSP++ edi-
tor. These capabilities permit programmers to:

· Control how the development tools process inputs and

generate outputs.

· Maintain a one-to-one correspondence with the tool's

command line switches.

The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of embedded, real-time
programming. These capabilities enable engineers to develop
code more effectively, eliminating the need to start from the
very beginning, when Developing new application code. The
VDK features include Threads, Critical and Unscheduled
regions, Semaphores, Events, and Device flags. The VDK also
supports Priority-based, Pre-emptive, Cooperative and Time-
Sliced scheduling approaches. In addition, the VDK was
designed to be scalable. If the application does not use a specific
feature, the support code for that feature is excluded from the
target system.

Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used with standard
command-line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.

VCSE is Analog Devices technology for creating, using, and
reusing software components (independent modules of sub-
stantial functionality) to quickly and reliably assemble software
applications. Download components from the Web and drop
them into the application. Publish component archives from
within VisualDSP++. VCSE supports component implementa-
tion in C/C++ or assembly language.

Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with existing Linker Definition
File (LDF), allowing the developer to move between the graphi-
cal and textual environments.

Analog Devices' emulators use the IEEE 1149.1 JTAG test access
port of the ADSP-BF561 to monitor and control the target
board processor during emulation. The emulator provides full-
speed emulation, allowing inspection and modification of mem-
ory, registers, and processor stacks. Non intrusive in-circuit

emulation is assured by the use of the processor's JTAG inter-
face--the emulator does not affect target system loading or
timing.

In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the Blackfin processor family. Third
Party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.

DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD (TARGET)

The Analog Devices family of emulators are tools that every sys-
tem developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on the ADSP-BF561. The emulator uses
the TAP to access the internal features of the processor, allow-
ing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The proces-
sor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor is
set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header
that connects the processor's JTAG port to the emulator.

For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices web site (

www.analog.com

)--

use site search on "EE-68." This document is updated regularly
to keep pace with improvements to emulator support.

To use these emulators, the target board must include a header
that includes a header that connects the processor's JTAG port
to the emulation.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-BF561
architecture and functionality. For detailed information on the
Blackfin DSP family core architecture and instruction set, refer
to the ADSP-BF561 Hardware Reference and the Blackfin Family
Instruction Set Reference.

Rev. PrC

Page 16 of 52

April 2004

ADSP-BF561

Preliminary Technical Data

PIN DESCRIPTIONS

ADSP-BF561 pin definitions are listed in

Table 8

. Unused

inputs should be tied or pulled to V

DDEXT

or GND.

Table 8. Pin Descriptions

Block

Pin Name

Type Signals Function

Driver
Type

Pull-up/down requirement

EBIU

ADDR[25:2]

Address Bus for Async/Sync Access

none

DATA[31:0]

I/O

Data Bus for Async/Sync Access

none

ABE[3:0]/SDQM[3:0]

Byte Enables/Data Masks for Async

/Sync Access

none

Bus Grant

none

Bus Request

pull-up required if function not used

BGH

Bus Grant Hang

none

EBIU

(SDRAM)

SRAS

Row Address Strobe

none

SCAS

Column Address Strobe

none

SWE

Write Enable

none

SCKE

Clock Enable

none

SCLK0/CLKOUT

Clock Output Pin 0

none

SCLK1

Clock Output Pin 1

none

SA10

SDRAM A10 Pin

none

SMS[3:0]

Bank Select

none

EBIU

(ASYNC)

AMS[3:0]

Bank Select

none

ARDY

Hardware Ready Control

pull-up required if function not used

AOE

Output Enable

none

AWE

Write Enable

none

ARE

Read Enable

none

PPI1

PPI1D[15:8] /PF[47:40]

I/O

PPI Data / Programmable Flag Pins

software configurable, none

PPI1D[7:0]

I/O

PPI Data Pins

software configurable, none

PPI1CLK

PPI Clock

software configurable, none

PPI1SYNC1/ TMR8

I/O

PPI Sync / Timer

software configurable, none

PPI1SYNC2/ TMR9

I/O

PPI Sync / Timer

software configurable, none

PPI1SYNC3

I/O

PPI Sync

software configurable, none

PPI2

PPI2D[15:8] /PF[39:32]

I/O

PPI Data / Programmable Flag Pins

software configurable, none

PPI2D[7:0]

I/O

PPI Data Pins

software configurable, none

PPI2CLK

PPI Clock

software configurable, none

PPI2SYNC1/ TMR10

I/O

PPI Sync / Timer

software configurable, none

PPI2SYNC2/ TMR11

I/O

PPI Sync / Timer

software configurable, none

PPI2SYNC3

I/O

PPI Sync

software configurable, none

JTAG

EMU

Emulation Output

none

TCK

JTAG Clock

internal pull-down

TDO

JTAG Serial Data Out

none

TDI

JTAG Serial Data In

internal pull-down

TMS

JTAG Mode Select

internal pull-down

TRST

JTAG Reset

external down necessary if JTAG not
used

ADSP-BF561

Preliminary Technical Data

Rev. PrC

Page 17 of 52

April 2004

UART

RX/PF27

I/O

UART Receive
/ Programmable Flag

software configurable,
no pull-up/down necessary

TX/PF26

I/O

UART Transmit
/ Programmable Flag

software configurable,
no pull-up/down necessary

SPI

MOSI

I/O

Master Out Slave In

software configurable,
no pull-up/down necessary

MISO

I/O

Master In Slave Out

pull-up is necessary if booting via SPI

SCK

I/O

SPI Clock

software configurable,
no pull-up/down necessary

SPORT0

RSCLK0/PF28

I/O

Sport0 / Programmable Flag

software configurable,
no pull-up/down necessary

RFS0/PF19

I/O

Sport0 Receive Frame Sync

/ Programmable Flag

software configurable,
no pull-up/down necessary

DR0PRI

Sport0 Receive Data Primary

software configurable,
no pull-up/down necessary

DR0SEC/PF20

I/O

Sport0 Receive Data Secondary
/ Programmable Flag

software configurable,
no pull-up/down necessary

TSCLK0/PF29

I/O

Sport0 Transmit Serial Clock

/ Programmable Flag

software configurable,
no pull-up/down necessary

TFS0/PF16

I/O

Sport0 Transmit Frame Sync

/ Programmable Flag

software configurable,
no pull-up/down necessary

DT0PRI/PF18

I/O

Sport0 Transmit Data Primary

/ Programmable Flag

software configurable,
no pull-up/down necessary

DT0SEC/PF17

I/O

Sport0 Transmit Data Secondary

/ Programmable Flag

software configurable,
no pull-up/down necessary

SPORT1

RSCLK1/PF30

I/O

Sport1 / Programmable Flag

software configurable,
no pull-up/down necessary

RFS1/PF24

I/O

Sport1 Receive Frame Sync

/ Programmable Flag

software configurable,
no pull-up/down necessary

DR1PRI

Sport1 Receive Data Primary

software configurable,
no pull-up/down necessary

DR1SEC/PF25

I/O

Sport1 Receive Data Secondary
/ Programmable Flag

software configurable,
no pull-up/down necessary

TSCLK1/PF31

I/O

Sport1 Transmit Serial Clock

/ Programmable Flag

software configurable,
no pull-up/down necessary

TFS1/PF21

I/O

Sport1 Transmit Frame Sync

/ Programmable Flag

software configurable,
no pull-up/down necessary

DT1PRI/PF23

I/O

Sport1 Transmit Data Primary

/ Programmable Flag

software configurable,
no pull-up/down necessary

DT1SEC/PF22

I/O

Sport1 Transmit Data Secondary

/ Programmable Flag

software configurable,
no pull-up/down necessary

Table 8. Pin Descriptions (Continued)

Block

Pin Name

Type Signals Function

Driver
Type

Pull-up/down requirement

Rev. PrC

Page 18 of 52

April 2004

ADSP-BF561

Preliminary Technical Data

PF/TIMER

PF15/EXT CLK

I/O

Programmable Flag

/ external timer clock input

software configurable,
no pull-up/down necessary

PF14

I/O

Programmable Flag

software configurable,
no pull-up/down necessary

PF13

I/O

Programmable Flag

software configurable,
no pull-up/down necessary

PF12

I/O

Programmable Flag

software configurable,
no pull-up/down necessary

PF11

I/O

Programmable Flag

software configurable,
no pull-up/down necessary

PF10

I/O

Programmable Flag

software configurable,
no pull-up/down necessary

PF9

I/O

Programmable Flag

software configurable,
no pull-up/down necessary

PF8

I/O

Programmable Flag

software configurable,
no pull-up/down necessary

PF7/SPISEL7/

TMR7

I/O

Programmable Flag / SPI Select

/ Timer

software configurable,
no pull-up/down necessary

PF6/SPISEL6/

TMR6

I/O

Programmable Flag / SPI Select

/ Timer

software configurable,
no pull-up/down necessary

PF5/SPISEL5/

TMR5

I/O

Programmable Flag / SPI Select

/ Timer

software configurable,
no pull-up/down necessary

PF4/SPISEL4/

TMR4

I/O

Programmable Flag / SPI Select

/ Timer

software configurable,
no pull-up/down necessary

PF3/SPISEL3/

TMR3

I/O

Programmable Flag / SPI Select

/ Timer

software configurable,
no pull-up/down necessary

PF2/SPISEL2/

TMR2

I/O

Programmable Flag / SPI Select

/ Timer

software configurable,
no pull-up/down necessary

PF1/SPISEL1/

TMR1

I/O

Programmable Flag / SPI Select

/ Timer

software configurable,
no pull-up/down necessary

PF0/SPISS/

TMR0

I/O

Programmable Flag / Slave SPI Select
/ Timer

software configurable,
no pull-up/down necessary

Clock

Generator

CLKIN

Clock input

needs to be at a level or
clocking

XTAL

Crystal connection

none

Mode

Controls

RESET

Chip reset signal

always active if core power on

SLEEP

Sleep

none

BMODE[1:0]

Dedicated Mode Pin, Configures
the boot mode that is employed
following a hardware reset or
software reset

pull-up or pull-down required

BYPASS

PLL BYPASS control

pull-up or pull-down required

NMI0

Non Maskable interrupt Core A

pull-down required if function not
used

NMI1

Non Maskable interrupt Core B

pull-down required if function not
used

Regulator

VROUT1-0

Regulation output

N/A

Table 8. Pin Descriptions (Continued)

Block

Pin Name

Type Signals Function

Driver
Type

Pull-up/down requirement

Rev. PrC

Page 20 of 52

April 2004

ADSP-BF561

Preliminary Technical Data

SPECIFICATIONS

Note that component specifications are subject to change with-
out notice.

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

Parameter

Minimum

Nominal

Maximum

Unit

DDINT

Internal Supply Voltage

0.8

1.2

TBD

DDEXT

External Supply Voltage

2.25

2.5 or 3.3

3.6

High Level Input Voltage

, @ V

DDEXT

=maximum

The ADSP-BF561 is 3.3 V tolerant (always accepts up to 3.6 V maximum V

), but voltage compliance (on outputs, V

) depends on the input V

DDEXT

, because V

(maximum) approximately equals V

DDEXT

(maximum). This 3.3 V tolerance applies to bi-directional and input only pins.

2.0

3.6

Low Level Input Voltage

, @ V

DDEXT

=minimum

0.3

0.6

AMBIENT

Ambient Operating Temperature

Industrial

-40

ºC

Commercial

ºC

Parameter

Test Conditions

Minimum

Maximum

Unit

High Level Output Voltage

DDEXT

=3.0V, I

= 0.5 mA

2.4

Low Level Output Voltage

@ V

DDEXT

=3.0V, I

= 2.0 mA

0.4

Low Level Input Current

DDEXT

=maximum, V

= 0 V

-10

High Level Input Current

@ V

DDEXT

=maximum, V

= V

maximum

µA

High Level Input Current

@ V

DDEXT

=maximum, V

= V

maximum

µA

OZH

Three-State Leakage Current

@ V

DDEXT

= maximum, V

= V

maximum

µA

OZL

Three-State Leakage Current

@ V

DDEXT

= maximum, V

= 0 V

-10

µA

Input Capacitance

6, 7

= 1 MHz, T

AMBIENT

= 25°C, V

= 2.5 V

TBD

Applies to output and bidirectional pins.

Applies to all input pins.

Applies to all input pins except TCK, TDI, TMS, and TRST.

Applies to TCK, TDI, TMS, and TRST.

Applies to three-statable pins.

Applies to all signal pins.

Guaranteed, but not tested.

ADSP-BF561

Preliminary Technical Data

Rev. PrC

Page 21 of 52

April 2004

ABSOLUTE MAXIMUM RATINGS

ESD SENSITIVITY

Internal (Core) Supply Voltage

DDINT

)

Stresses greater than those listed above may cause permanent damage to the device.

These are stress ratings only. Functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

0.3 V to +1.4 V

External (I/O) Supply Voltage

DDEXT

)

0.3 V to +3.8 V

Input Voltage

0.5 V to 3.6 V

Output Voltage Swing

0.5 V to V

DDEXT

+0.5 V

Load Capacitance

For proper SDRAM controller operation, the maximum load capacitance is 50 pF (at

3.3V) or 30 pF (at 2.5V) for ADDR25-2, DATA31-0, ABE3-0/SDQM3-0, CLKOUT,
SCKE, SA10, SRAS, SCAS, SWE, and SMS.

200 pF

Core Clock (CCLK)

ADSP-BF561SKBCZ600

600 MHz

ADSP-BF561SKBCZ500

500 MHz

System Clock (SCLK)

133 MHz

Storage Temperature Range

65ºC to +150ºC

Junction Temperature Under Bias

125ºC

Lead Temperature (5 seconds)

185ºC

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-BF561 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precau-
tions are recommended to avoid performance degradation or loss of functionality.

Rev. PrC

Page 22 of 52

April 2004

ADSP-BF561

Preliminary Technical Data

TIMING SPECIFICATIONS

Table 9

and

Table 12

describe the timing requirements for the

ADSP-BF561 clocks. Take care in selecting MSEL, SSEL, and
CSEL ratios so as not to exceed the maximum core clock, system
clock and Voltage Controlled Oscillator (VCO) operating fre-

quencies, as described in

Absolute Maximum Ratings on

Page 21

Table 12

describes Phase-Locked Loop operating

conditions.

Table 9. Core and System Clock Requirements--ADSP-BF561SKBCZ500

Parameter

Minimum

Maximum

Unit

CCLK

Core Cycle Period (V

DDINT

=1.4 V± 50 mV)

CCLK

Core Cycle Period (V

DDINT

=1.35 V 5%)

CCLK

Core Cycle Period (V

DDINT

=1.2 V5%)

CCLK

Core Cycle Period (V

DDINT

=1.1 V5%)

2.25

CCLK

Core Cycle Period (V

DDINT

=1.0 V5%)

2.70

CCLK

Core Cycle Period (V

DDINT

=0.9 V5%)

3.20

CCLK

Core Cycle Period (V

DDINT

=0.8 V)

4.00

Table 10. Core and System Clock Requirements--ADSP-BF561SKBCZ600X

Parameter

Minimum

Maximum

Unit

CCLK

Core Cycle Period (V

DDINT

=1.4 V± 50 mV)

CCLK

Core Cycle Period (V

DDINT

=1.35 V 5%)

CCLK

Core Cycle Period (V

DDINT

=1.2 V5%)

1.66

CCLK

Core Cycle Period (V

DDINT

=1.1 V5%)

2.25

CCLK

Core Cycle Period (V

DDINT

=1.0 V5%)

2.70

CCLK

Core Cycle Period (V

DDINT

=0.9 V5%)

3.20

CCLK

Core Cycle Period (V

DDINT

=0.8 V)

4.00

Table 11. Core and System Clock Requirements--ADSP-BF561SBB600

Parameter

Minimum

Maximum

Unit

CCLK

Core Cycle Period (V

DDINT

=1.4 V± 50 mV)

CCLK

Core Cycle Period (V

DDINT

=1.35 V 5%)

1.66

CCLK

Core Cycle Period (V

DDINT

=1.2 V5%)

2.0

CCLK

Core Cycle Period (V

DDINT

=1.1 V5%)

2.25

CCLK

Core Cycle Period (V

DDINT

=1.0 V5%)

2.70

CCLK

Core Cycle Period (V

DDINT

=0.9 V5%)

3.20

CCLK

Core Cycle Period (V

DDINT

=0.8 V)

4.00

Table 12. Phase-Locked Loop Operating Conditions

Parameter

Minimum

Maximum

Unit

Voltage Controlled Oscillator (VCO) Frequency

Maximum CCLK

MHz

ADSP-BF561

Preliminary Technical Data

Rev. PrC

Page 23 of 52

April 2004

Clock and Reset Timing

Table 13

and

Figure 7

describe clock and reset operations. Per

Figure 7

, combinations of CLKIN and clock multipliers must

not select core/peripheral clocks in excess of 600/133 MHz.

Table 13. Clock and Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

CKIN

CLKIN Period

25.0

100.0

CKINL

CLKIN Low Pulse

10.0

CKINH

CLKIN High Pulse

10.0

WRST

RESET Asserted Pulsewidth Low

11 t

CKIN

Switching Characteristics

SCLK

CLKOUT Period

7.5

Applies to bypass mode and non-bypass mode.

Applies after power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,

assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).

The figure below shows a x2 ratio between t

CKIN

and t

SCLK

, but the ratio has many programmable options. For more information, see the System Design chapter of the ADSP-

BF561 Hardware Reference.

SCLK

must always also be larger than t

Figure 7. Clock and Reset Timing

SCLKD

CLKOUT

RESET

CLKIN

CKINH

CKIN

CKINL

SCLK

WRST

ADSP-BF561

Preliminary Technical Data

Rev. PrC

Page 27 of 52

April 2004

External Port Bus Request and Grant Cycle Timing

Table 17

and

Figure 11

describe external port bus request and

bus grant operations.

Table 17. External Port Bus Request and Grant Cycle Timing

Parameter

, 1, 2

Min

Max

Unit

Timing Requirements

BR asserted to CLKOUT high setup

4.6

CLKOUT high to BR de-asserted hold time

0.0

Switching Characteristics

CLKOUT low to SMS, address, and RD/WR disable

4.5

CLKOUT low to SMS, address, and RD/WR enable

4.5

DBG

CLKOUT high to BG asserted setup

3.6

EBG

CLKOUT high to BG de-asserted hold time

3.6

DBH

CLKOUT high to BGH asserted setup

3.6

EBH

CLKOUT high to BGH de-asserted hold time

3.6

These are preliminary timing parameters that are based on worst-case operating conditions.

The pad loads for these timing parameters are 20 pF.

Figure 11. External Port Bus Request and Grant Cycle Timing

B H

A D D R 2 5 -2

A M S x

C L K O U T

B S

S D

D B G

D B H

S E

E B G

E B H

B G

A W E

B G H

A R E

B R

A B E 3 -0

Rev. PrC

Page 28 of 52

April 2004

ADSP-BF561

Preliminary Technical Data

Parallel Peripheral Interface Timing

Table 18

Figure 12

, describes Parallel Peripheral Interface

operations.

Table 18. Parallel Peripheral Interface Timing

Parameter

Min

Max

Unit

Timing Requirements

PCLKW

PPIx_CLK Width

6.0

PCLK

PPI_CLK Period

15.0

Timing Requirements

SFSPE

External Frame Sync Setup Before PPI_CLK

3.0

HFSPE

External Frame Sync H old After PPI_CLK

3.0

SDRPE

Receive Data Setup Before PPI_CLK

TBD

HDRPE

Receive Data Hold After PPI_CLK

TBD

Switching Characteristics

DFSPE

Internal Frame Sync Delay After PPI_CLK

10.0

HOFSPE

Internal Frame Sync Hold After PPI_CLK

0.0

DDTPE

Transmit Data Delay After PPI_CLK

10.0

HDTPE

Transmit Data Hold After PPI_CLK

0.0

PPI_CLK frequency cannot exceed f

SCLK

Figure 12. Timing Diagram PPI

D D T P E

H D T P E

P P I_ C L K

P P I_ F S 1

P P Ix

D R IV E

E D G E

S A M P L E

E D G E

S F S P E

H F S P E

P C L K W

D F S P E

H O F S P E

P P I_ F S 2

S D R P E

H D R P E

ADSP-BF561

Preliminary Technical Data

Rev. PrC

Page 29 of 52

April 2004

Serial Ports

Table 19

through

Table 24 on Page 30

and

Figure 13 on Page 31

through

Figure 15 on Page 33

describe Serial Port operations.

Table 19. Serial Ports--External Clock

Parameter

Min

Max

Unit

Timing Requirements

SFSE

TFS/RFS Setup Before TSCLK/RSCLK

3.0

HFSE

TFS/RFS Hold After TSCLK/RSCLK

3.0

SDRE

Receive Data Setup Before RSCLK

3.0

HDRE

Receive Data Hold After RSCLK

3.0

SCLKW

TSCLK/RSCLK Width

4.5

SCLK

TSCLK/RSCLK Period

15.0

Referenced to sample edge.

Table 20. Serial Ports--Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

SFSI

TFS/RFS Setup Before TSCLK/RSCLK

TBD

HFSI

TFS/RFS Hold After TSCLK/RSCLK

TBD

SDRI

Receive Data Setup Before RSCLK

6.0

HDRI

Receive Data Hold After RSCLK

0.0

SCLKW

TSCLK/RSCLK Width

4.5

SCLK

TSCLK/RSCLK Period

15.0

Referenced to sample edge.

Table 21. Serial Ports--External Clock

Parameter

Min

Max

Unit

Switching Characteristics

DFSE

TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)

10.0

HOFSE

TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)

0.0

DDTE

Transmit Data Delay After TSCLK

10.0

HDTE

Transmit Data Hold After TSCLK

0.0

Referenced to drive edge.

Rev. PrC

Page 30 of 52

April 2004

ADSP-BF561

Preliminary Technical Data

Table 22. Serial Ports--Internal Clock

Parameter

Min

Max

Unit

Switching Characteristics

DFS

TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)

TBD

HOFS

TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)

TBD

DDT

Transmit Data Delay After TSCLK

TBD

HDT

Transmit Data Hold After TSCLK

TBD

SCLKIW

TSCLK/RSCLK Width

4.5

Referenced to drive edge.

Table 23. Serial Ports--Enable and Three-State

Parameter

Min

Max

Unit

Switching Characteristics

DTENE

Data Enable Delay from External TSCLK

TBD

DDTTE

Data Disable Delay from External TSCLK

TBD

DTENI

Data Enable Delay from Internal TSCLK

TBD

DDTTI

Data Disable Delay from Internal TSCLK

TBD

Referenced to drive edge.

Table 24. External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

DDTLFSE

Data Delay from Late External TFS or External RFS with MCE = 1, MFD
= 0

1,2

TBD

DTENLFSE

Data Enable from late FS or MCE = 1, MFD = 0

1,2

TBD

MCE = 1, TFS enable and TFS valid follow t

DDTENFS

and t

DDTLFSE

If external RFS/TFS setup to RSCLK/TSCLK > t

SCLK

/2 then t

DDTLSCK

and t

DTENLSCK

apply, otherwise t

DDTLFSE

and t

DTENLFS

apply.

ADSP-BF561

Preliminary Technical Data

Rev. PrC

Page 31 of 52

April 2004

Figure 13. Serial Ports

DRIVE EDGE

TCLK (INT)

DRIVE EDGE

TCLK/RCLK

DRIVE EDGE

TCLK/RCLK

TCLK (EXT)

DDTTE

DDTEN

DDTTI

DDTIN

RCLK

RFS

DRIVE EDGE

SAMPLE EDGE

DATA RECEIVE-- INTERNAL CLOCK

DATA RECEIVE-- EXTERNAL CLOCK

RCLK

RFS

DRIVE EDGE

SAMPLE EDGE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

SDRI

HD RI

SFSI

HFSI

DFSE

HOFSE

SCLKIW

SDRE

HDRE

SFSE

HFSE

DFSE

SCLKW

HO FSE

DDTI

TCLK

TFS

DRIVE EDGE

SAMPLE EDGE

DATA TRANSMIT -- INTERNAL CLOCK

SFSI

HFSI

DFSI

HOFSI

SCLKIW

HDTI

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DDTE

TCLK

TFS

DRIVE EDGE

SAMPLE EDGE

DATA TRANSMIT -- EXTERNAL CLOCK

SFSE

HFSE

DFSE

HO FSE

SCLKW

HDTE

TFS ("LATE", EXT)

TFS ("LATE", INT)

ADSP-BF561

Preliminary Technical Data

Rev. PrC

Page 41 of 52

April 2004

JTAG Test And Emulation Port Timing

Table 29

and

Figure 21

describe JTAG port operations.

Table 29. JTAG Port Timing

Parameter

Min

Max

Unit

Timing Parameters

TCK

TCK Period

STAP

TDI, TMS Setup Before TCK High

HTAP

TDI, TMS Hold After TCK High

SSYS

System Inputs Setup Before TCK High

HSYS

System Inputs Hold After TCK High

TRSTW

TRST Pulsewidth

TCK cycles

Switching Characteristics

DTDO

TDO Delay from TCK Low

DSYS

System Outputs Delay After TCK Low

System Inputs=DATA31-0, ARDY, TMR2-0, PF47-0, PPIx_CLK, RSCLK0-1, RFS0-1, DR0PRI, DR0SEC, TSCLK0-1, TFS0-1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,

RESET, NMI, BMODE1-0, BR, PPIxD7-0.

50 MHz max.

System Outputs=DATA31-0, ADDR25-2, ABE3-0, AOE, ARE, AWE, AMS3-0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS3-0, PF47-0, RSCLK0-1, RFS0-1, TSCLK0-

1, TFS0-1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPIxD7-0.

Figure 21. JTAG Port Timing

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

TCK

HTAP

STAP

DTDO

SSYS

HSYS

DSYS

Rev. PrC

Page 42 of 52

April 2004

ADSP-BF561

Preliminary Technical Data

POWER DISSIPATION

Total power dissipation has two components, one due to inter-
nal circuitry (P

INT

) and one due to the switching of external

output drivers (P

EXT

Table 30

shows the power dissipation for

internal circuitry (V

DDINT

). Internal power dissipation is depen-

dent on the instruction execution sequence and the data
operands involved.

The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on

· The number of output pins that switch during each cycle

(O)

· The maximum frequency at which they can switch (f)

· Their load capacitance (C)

· Their voltage swing (V

DDEXT

)

The external component is calculated using:

The frequency f includes driving the load high and then back
low. For example: DATA150 pins can drive high and low at a
maximum rate of 1/(23t

SCLK

) while in SDRAM burst mode.

A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation.

Note that the conditions causing a worst-case P

EXT

differ from

those causing a worst-case P

INT

. Maximum P

INT

cannot occur

while 100% of the output pins are switching from all ones (1s) to
all zeros (0s). Note also that it is not common for an application
to have 100%,or even 50%, of the outputs switching
simultaneously.

OUTPUT DRIVE CURRENTS

Figure 22

shows typical I-V characteristics for the output driv-

ers of the ADSP-BF561. The curves represent the current drive
capability of the output drivers as a function of output voltage.

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Tim-

ing Specifications on Page 22

. These include output disable

time, output enable time, and capacitive loading. The timing
specifications for the DSP apply for the voltage reference levels

Figure 23

Table 30. Internal Power Dissipation

Test Conditions

data is specified for typical process parameters. All data at 25ºC.

Parameter f

CCLK

50 MHz
V

DDINT

0.8 V

CCLK

400 MHz
V

DDINT

1.2 V

CCLK

600 MHz
V

DDINT

1.2 V

CCLK

600 MHz
V

DDINT

1.35 V

Unit

DDTYP

Processor executing 75% dual Mac, 25% ADD with moderate data bus

activity.

TBD

520

TBD

DDSLEEP

See the ADSP-BF53x Blackfin Processor Hardware Reference Manual for

definitions of Sleep and Deep Sleep operating modes.

TBD

DDDEEPSLEEP

TBD

DDHI-

BERNATE

Measured at V

DDEXT

= 3.65V with voltage regulator off (V

DDINT

= 0V).

TBD

Figure 22. ADSP-BF561 Typical Drive

EXT

Total

EXT

DDINT

(

)

SOURCE (VDDEXT) VOLTAGE - V

120

-20

-80

3.5

0.5

1.5

2.5

100

-40

-60

-100

-120

(
V

)

Figure 23. Voltage Reference Levels for AC Measurements (Except Output

Enable/Disable)

INPUT

OUTPUT

1.5V

ADSP-BF561

Preliminary Technical Data

Rev. PrC

Page 43 of 52

April 2004

Output Enable Time

Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time t

ENA

is the interval from

the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram (

Figure 24

). The time

ENA_MEASURED

is the interval from when the reference signal

switches to when the output voltage reaches 2.0V (output high)
or 1.0V (output low). Time t

TRIP

is the interval from when the

output starts driving to when the output reaches the 1.0V or
2.0V trip voltage. Time t

ENA

is calculated as

ENA_MEASURED

TRIP

. If multiple pins (such as the data bus) are

enabled, the measurement value is that of the first pin to start
driving.

Output Disable Time

Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, C

and the

load current, I

. This decay time can be approximated by the

following equation:

The output disable time t

DIS

is the difference between

DIS_MEASURED

and t

DECAY

as shown in

Figure 24

.The time

DIS_MEASURED

is the interval from when the reference signal

switches to when the output voltage decays V from the mea-
sured output high or output low voltage. t

DECAY

is calculated

with test loads C

and I

, and with V equal to 0.5 V.

EXAMPLE SYSTEM HOLD TIME CALCULATION

To determine the data output hold time in a particular system,
first calculate t

DECAY

using the equation given above. Choose

V to be the difference between the ADSP-BF561's output volt-

age and the input threshold for the device requiring the hold

time. A typical V will be 0.4 V. CL is the total bus capacitance
(per data line), and IL is the total leakage or three-state current
(per data line). The hold time will be t

DECAY

plus the minimum

disable time (i.e., t

DSDAT

for an SDRAM write cycle).

Figure 24. Output Enable/Disable

DECAY

(

) I

REFERENCE

SIGNAL

DIS

OUTPUT STARTS DRIVING

(MEASURED) -

(MEASURED) +

DIS-MEASURED

(MEASURED)

2.0V

1.0V

(MEASURED)

HIGH-IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS

VOLTAGE TO BE APPROXIMATELY 1.5V.

OUTPUT STOPS DRIVING

ENA

DECAY

ENA-MEASURED

TRIP

Figure 25. Typical Output Delay or Hold vs. Load Capacitance (at Max Case

Temperature)

LOAD CAPACITANCE - pF

-5

210

120

150

180

NOMINAL

Rev. PrC

Page 44 of 52

April 2004

ADSP-BF561

Preliminary Technical Data

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see

Figure 26 on Page 44

Figure 25

shows

graphically how output delays and holds vary with load capaci-
tance (Note that this graph or derating does not apply to output
disable delays; see

Output Disable Time on Page 43

). The graphs

Figure 25

Figure 27

and

Figure 28

may not be linear outside

the ranges shown, for Typical Output Delay vs. Load Capaci-
tance and Typical Output Rise Time (10%-90%, V=Min) vs.
Load Capacitance.

Figure 26. Equivalent Device Loading for AC Measurements (Includes All

Fixtures)

Figure 27. Typical Output Rise/Fall Time (10%-90%, Vddext = Max)

1.5V

20pF

OUTPUT

PIN

LOAD CAPACITANCE - pF

16.0

8.0

200

100

120

140

160

180

14.0

12.0

4.0

2.0

10.0

6.0

R
I
S
E

F
A

L
L

T
I
M

E
S

n
s

(
.
v

v
,
2
0
%

8
0
%

)

Figure 28. Typical Output Rise/Fall Time (10%-90%, Vddext = Min)

LOAD CAPACITANCE - pF

2.0

200

100

120

140

160

180

3.5

3.0

1.0

0.5

2.5

1.5

R
I
S
E

F
A

L
L

T
I
M

E
S

n
s

(
0
.
v

v
,
2
0
%

8
0
%

)

ADSP-BF561

Preliminary Technical Data

Rev. PrC

Page 45 of 52

April 2004

256-BALL MBGA PIN CONFIGURATIONS

Table 31. 256-Lead MBGA Pin Assignments

MBGA
Pin No.

Pin Name

MBGA
Pin No.

Pin Name

MBGA
Pin No.

Pin Name

MBGA
Pin No.

Pin Name

A01

VDDEXT

B01

PPI2CLK

C01

PPI1SYNC2/TMR9

D01

PPI1D13/PF45

A02

ADDR24

B02

ADDR22

C02

PPI1CLK

D02

PPI1D15/PF47

A03

ADDR20

B03

ADDR18

C03

ADDR25

D03

PPI1SYNC3

A04

VDDEXT

B04

ADDR16

C04

ADDR19

D04

ADDR23

A05

ADDR14

B05

ADDR12

C05

GND

D05

GND

A06

ADDR10

B06

VDDEXT

C06

ADDR11

D06

GND

A07

AMS3

B07

AMS1

C07

AOE

D07

ADDR09

A08

AWE

B08

ARE

C08

AMS0

D08

GND

A09

VDDEXT

B09

SMS1

C09

SMS2

D09

ARDY

A10

SMS3

B10

SCKE

C10

SRAS

D10

SCAS

A11

SCLK0/CLKOUT

B11

VDDEXT

C11

GND

D11

SA10

A12

SCLK1

B12

C12

BGH

D12

VDDEXT

A13

B13

ABE1/SDQM1

C13

GND

D13

ADDR02

A14

ABE2/SDQM2

B14

ADDR06

C14

ADDR07

D14

GND

A15

ABE3/SDQM3

B15

ADDR04

C15

DATA1

D15

DATA5

A16

VDDEXT

B16

DATA0

C16

DATA3

D16

DATA6

E01

GND

F01

CLKIN

G01

XTAL

H01

GND

E02

PPI1D11/PF43

F02

VDDEXT

G02

GND

H02

GND

E03

PPI1D12/PF44

F03

RESET

G03

VDDEXT

H03

PPI1D9/PF41

E04

PPI1SYNC1/TMR8

F04

PPI1D10/PF42

G04

BYPASS

H04

PPI1D7

E05

ADDR15

F05

ADDR21

G05

PPI1D14/PF46

H05

PPI1D5

E06

ADDR13

F06

ADDR17

G06

GND

H06

VDDINT

E07

AMS2

F07

VDDINT

G07

GND

H07

VDDINT

E08

VDDINT

F08

GND

G08

GND

H08

GND

E09

SMS0

F09

VDDINT

G09

VDDINT

H09

GND

E10

SWE

F10

GND

G10

ADDR05

H10

GND

E11

ABE0/SDQM0

F11

ADDR08

G11

ADDR03

H11

VDDINT

E12

DATA2

F12

DATA10

G12

DATA15

H12

DATA16

E13

GND

F13

DATA8

G13

DATA14

H13

DATA18

E14

DATA4

F14

DATA12

G14

GND

H14

DATA20

E15

DATA7

F15

DATA9

G15

DATA13

H15

DATA17

E16

VDDEXT

F16

DATA11

G16

VDDEXT

H16

DATA19

Rev. PrC

Page 46 of 52

April 2004

ADSP-BF561

Preliminary Technical Data

J01

VROUT0

K01

PPI1D6

L01

PPI1D0

M01

PPI2D15/PF39

J02

VROUT1

K02

PPI1D4

L02

PPI2SYNC2/TMR11

M02

PPI2D13/PF37

J03

PPI1D2

K03

PPI1D8/PF40

L03

GND

M03

PPI2D9/PF33

J04

PPI1D3

K04

PPI2SYNC1/TMR10

L04

PPI2SYNC3

M04

GND

J05

PPI1D1

K05

PPI2D14/PF38

L05

VDDEXT

M05

J06

VDDEXT

K06

VDDEXT

L06

PPI2D11/PF35

M06

PF3/SPISEL3/TMR3

J07

GND

K07

GND

L07

GND

M07

PF7/SPISEL7/TMR7

J08

VDDINT

K08

VDDINT

L08

VDDINT

M08

VDDINT

J09

VDDINT

K09

GND

L09

GND

M09

GND

J10

VDDINT

K10

GND

L10

VDDEXT

M10

BMODE0

J11

GND

K11

VDDINT

L11

GND

M11

SCK

J12

DATA30

K12

DATA28

L12

DR0PRI

M12

DR1PRI

J13

DATA22

K13

DATA26

L13

TFS0/PF16

M13

J14

GND

K14

DATA24

L14

GND

M14

VDDEXT

J15

DATA21

K15

DATA25

L15

DATA27

M15

DATA31

J16

DATA23

K16

VDDEXT

L16

DATA29

M16

DT0PRI/PF18

N01

PPI2D12/PF36

P01

PPI2D8/PF32

R01

PPI2D7

T01

VDDEXT

N02

PPI2D10/PF34

P02

GND

R02

PPI2D6

T02

PPI2D4

N03

PPI2D3

P03

PPI2D5

R03

PPI2D2

T03

VDDEXT

N04

PPI2D1

P04

PF0/SPISS/TMR0

R04

PPI2D0

T04

PF2/SPISEL2/TMR2

N05

PF1/SPISEL1/TMR1

P05

GND

R05

PF4/SPISEL4/TMR4

T05

PF6/SPISEL6/TMR6

N06

PF9

P06

PF5/SPISEL5/TMR5

R06

PF8

T06

VDDEXT

N07

GND

P07

PF11

R07

PF10

T07

PF12

N08

PF13

P08

PF15/EXTCLK

R08

PF14

T08

VDDEXT

N09

TDO

P09

GND

R09

NMI1

T09

TCK

N10

BMODE1

P10

TRST

R10

TDI

T10

TMS

N11

MOSI

P11

NMI0

R11

T11

SLEEP

N12

GND

P12

GND

R12

MISO

T12

VDDEXT

N13

RFS1/PF24

P13

RSCLK1/PF30

R13

TX/PF26

T13

RX/PF27

N14

GND

P14

TFS1/PF21

R14

TSCLK1/PF31

T14

DR1SEC/PF25

N15

DT0SEC/PF17

P15

RSCLK0/PF28

R15

DT1PRI/PF23

T15

DT1SEC/PF22

N16

TSCLK0/PF29

P16

DR0SEC/PF20

R16

RFS0/PF19

T16

VDDEXT

Table 31. 256-Lead MBGA Pin Assignments (Continued)

MBGA
Pin No.

Pin Name

MBGA
Pin No.

Pin Name

MBGA
Pin No.

Pin Name

MBGA
Pin No.

Pin Name

ADSP-BF561

Preliminary Technical Data

Rev. PrC

Page 47 of 52

April 2004

297-BALL PBGA PIN CONFIGURATIONS

Table 32. 297-Lead PBGA Pin Assignments

MBGA
Pin No.

Pin Name

MBGA
Pin No.

Pin Name

MBGA
Pin No.

Pin Name

MBGA
Pin No.

Pin Name

A01

GND

AB03

GND

AE11

PF12

AF17

SLEEP

A02

ADDR25

AB24

GND

AE12

PF14

AF18

NMI0

A03

ADDR23

AB25

TFS0/PF16

AE13

AF19

SCK

A04

ADDR21

AB26

DR0PRI

AE14

TDO

AF20

TX/PF26

A05

ADDR19

AC01

PPI2D9/PF33

AE15

TRST

AF21

RSCLK1/PF30

A06

ADDR17

AC02

PPI2D8/PF32

AE16

EMU

AF22

DR1PRI

A07

ADDR15

AC03

GND

AE17

BMODE1

AF23

TSCLK1/PF31

A08

ADDR13

AC04

GND

AE18

BMODE0

AF24

DT1SEC/PF22

A09

ADDR11

AC23

GND

AE19

MISO

AF25

DT1PRI/PF23

A10

ADDR09

AC24

GND

AE20

MOSI

AF26

GND

A11

AMS3

AC25

DR0SEC/PF20

AE21

RX/PF27

B01

PPI2CLK

A12

AMS1

AC26

RFS0/PF19

AE22

RFS1/PF24

B02

GND

A13

AWE

AD01

PPI2D7

AE23

DR1SEC/PF25

B03

ADDR24

A14

ARE

AD02

PPI2D6

AE24

TFS1/PF21

B04

ADDR22

A15

SMS0

AD03

GND

AE25

GND

B05

ADDR20

A16

SMS2

AD04

GND

AE26

B06

ADDR18

A17

SRAS

AD05

GND

AF01

GND

B07

ADDR16

A18

SCAS

AD22

GND

AF02

PPI2D4

B08

ADDR14

A19

SCLK0/CLKOUT

AD23

GND

AF03

PPI2D2

B09

ADDR12

A20

SCLK1

AD24

GND

AF04

PPI2D0

B10

ADDR10

A21

BGH

AD25

AF05

PF1/SPISEL1/TMR1

B11

AMS2

A22

ABE0/SDQM0

AD26

RSCLK0/PF28

AF06

PF3/SPISEL3/TMR3

B12

AMS0

A23

ABE2/SDQM2

AE01

PPI2D5

AF07

PF5/SPISEL5/TMR5

B13

AOE

A24

ADDR08

AE02

GND

AF08

PF7/SPISEL7/TMR7

B14

ARDY

A25

ADDR06

AE03

PPI2D3

AF09

PF9

B15

SMS1

A26

GND

AE04

PPI2D1

AF10

PF11

B16

SMS3

AA01

PPI2D13/PF37

AE05

PF0/SPISS/TMR0

AF11

PF13

B17

SCKE

AA02

PPI2D12/PF36

AE06

PF2/SPISEL2/TMR2

AF12

PF15/EXT CLK

B18

SWE

AA25

DT0SEC/PF17

AE07

PF4/SPISEL4/TMR4

AF13

NMI1

B19

SA10

AA26

TSCLK0/PF29

AE08

PF6/SPISEL6/TMR6

AF14

TCK

B20

AB01

PPI2D11/PF35

AE09

PF8

AF15

TDI

B21

AB02

PPI2D10/PF34

AE10

PF10

AF16

TMS

B22

ABE1/SDQM1

Rev. PrC

Page 48 of 52

April 2004

ADSP-BF561

Preliminary Technical Data

B23

ABE3/SDQM3

G01

PPI1D11/PF43

K25

DATA10

N12

GND

B24

ADDR07

G02

PPI1D10/PF42

K26

DATA13

N13

GND

B25

GND

G25

DATA4

L01

N14

GND

B26

ADDR05

G26

DATA7

L02

N15

GND

C01

PPI1SYNC3

H01

BYPASS

L10

VDDEXT

N16

GND

C02

PPI1CLK

H02

RESET

L11

GND

N17

GND

C03

GND

H25

DATA6

L12

GND

N18

VDDINT

C04

GND

H26

DATA9

L13

GND

N25

DATA16

C05

GND

J01

CLKIN

L14

GND

N26

DATA19

C22

GND

J02

GND

L15

GND

P01

PPI1D7

C23

GND

J10

VDDEXT

L16

GND

P02

PPI1D8/PF40

C24

GND

J11

VDDEXT

L17

GND

P10

VDDEXT

C25

ADDR04

J12

VDDEXT

L18

VDDINT

P11

GND

C26

ADDR03

J13

VDDEXT

L25

DATA12

P12

GND

D01

PPI1SYNC1/TMR8

J14

VDDEXT

L26

DATA15

P13

GND

D02

PPI1SYNC2/TMR9

J15

VDDEXT

M01

VROUT0

P14

GND

D03

GND

J16

VDDINT

M02

GND

P15

GND

D04

GND

J17

VDDINT

M10

VDDEXT

P16

GND

D23

GND

J18

VDDINT

M11

GND

P17

GND

D24

GND

J25

DATA8

M12

GND

P18

VDDINT

D25

ADDR02

J26

DATA11

M13

GND

P25

DATA18

D26

DATA1

K01

XTAL

M14

GND

P26

DATA21

E01

PPI1D15/PF47

K02

M15

GND

R01

PPI1D5

E02

PPI1D14/PF46

K10

VDDEXT

M16

GND

R02

PPI1D6

E03

GND

K11

VDDEXT

M17

GND

R10

VDDEXT

E24

GND

K12

VDDEXT

M18

VDDINT

R11

GND

E25

DATA0

K13

VDDEXT

M25

DATA14

R12

GND

E26

DATA3

K14

VDDEXT

M26

DATA17

R13

GND

F01

PPI1D13/PF45

K15

VDDEXT

N01

VROUT1

R14

GND

F02

PPI1D12/PF44

K16

VDDINT

N02

PPI1D9/PF41

R15

GND

F25

DATA2

K17

VDDINT

N10

VDDEXT

R16

GND

F26

DATA5

K18

VDDINT

N11

GND

R17

GND

Table 32. 297-Lead PBGA Pin Assignments (Continued)

MBGA
Pin No.

Pin Name

MBGA
Pin No.

Pin Name

MBGA
Pin No.

Pin Name

MBGA
Pin No.

Pin Name

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADSP-BF561

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADSP-BF561