ADuM3100 Digital Isolator, Enhanced System-Level ESD Reliability Data Sheet (Rev. A)
Digital Isolator, Enhanced
System-Level ESD Reliability
ADuM3100
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
FEATURES
Enhanced system-level ESD performance per IEC 61000-4-x
High data rate: dc to 100 Mbps (NRZ)
Compatible with 3.3 V and 5.0 V operation/level translation
105C maximum operating temperature
Low power operation
5 V operation
2.0 mA maximum @ 1 Mbps
5.6 mA maximum @ 25 Mbps
18 mA maximum @ 100 Mbps
3.3 V operation
1.1 mA maximum @ 1 Mbps
4.2 mA maximum @ 25 Mbps
8.3 mA maximum @ 50 Mbps
8-lead SOIC, Pb-free package
High common-mode transient immunity: >25 kV/s
Safety and regulatory information
UL recognized: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN EN 60747-5-2 (VDE 0884 Part 2): 200301
DIN EN 60950 (VDE 0805): 200112; EN 60950: 2000
V
IORM
= 560 V
PEAK
APPLICATIONS
Digital fieldbus isolation
Opto-isolator replacement
Computer-peripheral interface
Microprocessor system interface
General instrumentation and data acquisition
FUNCTIONAL BLOCK DIAGRAM
WATCHDOG
E
N
C
O
D
E
D
E
C
O
D
E
UPDATE
V
DD1
V
I
(DATA IN)
V
DD1
GND
1
V
DD2
GND
2
V
O
(DATA OUT)
GND
2
ADuM3100
NOTES
1. FOR PRINCIPLES OF OPERATION, SEE METHOD OF OPERATION,
DC CORRECTNESS, AND MAGNETIC FIELD IMMUNITY SECTION.
8
7
6
5
1
2
3
4
05637-
001
Figure 1.
GENERAL DESCRIPTION
The ADuM3100
1
is a digital isolator based on Analog Devices
iCoupler technology. Combining high speed CMOS and
monolithic transformer technology, this isolation component
provides outstanding performance characteristics superior to
alternatives, such as optocoupler devices.
Configured as a pin-compatible replacement for existing high
speed optocouplers, the ADuM3100 supports data rates as high
as 25 Mbps and 100 Mbps.
The ADuM3100 operates with a voltage supply ranging from
3.0 V to 5.5 V, boasts a propagation delay of <18 ns and an edge
asymmetry of <2 ns, and is compatible with temperatures up to
105C. It operates at very low power, less than 2.0 mA of
quiescent current (sum of both sides), and a dynamic
current of less than 160 A per Mbps of data rate. Unlike
other optocoupler alternatives, the ADuM3100 provides dc
correctness with a patented refresh feature that continuously
updates the output signal.
The ADuM3100 is offered in two grades. The ADuM3100AR
and ADuM3100BR can operate up to a maximum temperature
of 105C and support data rates up to 25 Mbps and 100 Mbps,
respectively.
In comparison to the ADuM1100 digital isolator, the
ADuM3100 contains various circuit and layout changes to
provide increased capability relative to system-level IEC 61000-
4- testing (ESD/burst/surge). The precise capability in these
tests for either the
ADuM1100
or ADuM3100 is strongly
determined by the design and layout of the user's board or
module. For more information, see
Application Note AN-793,
ESD/Latch-Up Considerations with iCoupler Isolation
Products
.
1
Protected by U.S. Patents 5,952,849; 6,525,566; 6,922,080; 6,903,578;
6,873,065; and other pending patents.
ADuM3100
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Electrical Specifications, 5 V Operation........................................ 3
Electrical Specifications, 3.3 V Operation..................................... 4
Electrical Specifications, Mixed 5 V/3 V or
3 V/5 V Operation............................................................................ 5
Package Characteristics ............................................................... 7
Regulatory Information............................................................... 7
Insulation and Safety-Related Specifications............................ 7
DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation
Characteristics .............................................................................. 8
Recommended Operating Conditions ...................................... 8
Absolute Maximum Ratings ............................................................9
ESD Caution...................................................................................9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
Applications..................................................................................... 13
PC Board Layout ........................................................................ 13
System-Level ESD Considerations and Enhancements ........ 13
Propagation Delay-Related Parameters................................... 13
Method of Operation, DC Correctness, and Magnetic Field
Immunity..................................................................................... 14
Power Consumption .................................................................. 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
3/06--Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Product Title, Features, General Description,
and Note 1.......................................................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Added System-Level ESD Considerations and
Enhancements Section................................................................... 13
Added Power Consumption Section............................................ 15
10/05--Revision 0: Initial Version
ADuM3100
Rev. A | Page 3 of 16
ELECTRICAL SPECIFICATIONS, 5 V OPERATION
1
4.5 V V
DD1
5.5 V, 4.5 V V
DD2
5.5 V. All minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at T
A
= 25C, V
DD1
= V
DD2
= 5 V.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, Quiescent
I
DD1 (Q)
1.3
1.8
mA
V
I
= 0 V or V
DD1
Output Supply Current, Quiescent
I
DD2 (Q)
0.15
0.25
mA
V
I
= 0 V or V
DD1
Input Supply Current (25 Mbps)
(See Figure 4)
I
DD1 (25)
3.2
4.5
mA
12.5 MHz logic signal freq.
Output Supply Current
2
(25 Mbps)
(See Figure 5)
I
DD2 (25)
0.6
1.1
mA
12.5 MHz logic signal freq.
Input Supply Current (100 Mbps)
(See Figure 4)
I
DD1 (100)
10
15
mA
50 MHz logic signal freq.
Output Supply Current
2
(100 Mbps)
(See Figure 5)
I
DD2 (100)
2.1
2.9
mA
50 MHz logic signal freq.,
ADuM3100BR only
Input Current
I
I
-10
+0.01
+10
A
0 V
IN
V
DD1
Logic High Output Voltage
V
OH
V
DD2
- 0.1
5.0
V
I
O
= -20 A, V
I
= V
IH
V
DD2
- 0.8
4.6
V
I
O
= 4 mA, V
I
= V
IH
Logic Low Output Voltage
V
OL
0.0
0.1
V
I
O
= 20 A, V
I
= V
IL
0.03
0.1
V
I
O
= 400 A, V
I
= V
IL
0.3
0.8
V
I
O
= 4 mA, V
I
= V
IL
SWITCHING SPECIFICATIONS
For ADuM3100AR
Minimum Pulse Width
3
PW
40
ns
C
L
= 15 pF, CMOS signal
levels
Maximum Data Rate
4
25
Mbps
C
L
= 15 pF, CMOS signal
levels
For ADuM3100BR
Minimum Pulse Width
4
PW
6.7
10
ns
C
L
= 15 pF, CMOS signal
levels
Maximum Data Rate
4
100
150
Mbps
C
L
= 15 pF, CMOS signal
levels
For All Grades
Propagation Delay Time to Logic Low
Output
5 ,
6
(See Figure 6)
t
PHL
10.5
18
ns
C
L
= 15 pF, CMOS signal
levels
Propagation Delay Time to Logic High
Output
5, 6
(See Figure 6)
t
PLH
10.5
18
ns
C
L
= 15 pF, CMOS signal
levels
Pulse-Width Distortion |t
PLH
- t
PHL
|
6
PWD
0.5
2
ns
C
L
= 15 pF, CMOS signal
levels
Change vs. Temperature
7
3
ps/C
C
L
= 15 pF, CMOS signal
levels
Propagation Delay Skew (Equal Temperature)
6, 8
t
PSK1
8
ns
C
L
= 15 pF, CMOS signal
levels
Propagation Delay Skew (Equal Temperature,
Supplies)
6, 8
t
PSK2
6
ns
C
L
= 15 pF, CMOS signal
levels
Output Rise/Fall Time
t
R
, t
F
3
ns
C
L
= 15 pF, CMOS signal
levels
Common-Mode Transient Immunity at
Logic Low/High Output
9
|CM
L
|,
|CM
H
|
25
35
kV/s
V
I
= 0 or V
DD1
, V
CM
= 1000 V
Input Dynamic Supply Current
10
I
DDI (D)
0.09
mA/Mbps
Output Dynamic Supply Current
10
I
DDO (D)
0.02
mA/Mbps
See notes on Page 6
.
ADuM3100
Rev. A | Page 4 of 16
ELECTRICAL SPECIFICATIONS, 3.3 V OPERATION
1
3.0 V V
DD1
3.6 V, 3.0 V V
DD2
3.6 V. All minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at T
A
= 25C, V
DD1
= V
DD2
= 3.3 V.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, Quiescent
I
DD1 (Q)
0.7
0.9
mA
V
I
= 0 V or V
DD1
Output Supply Current, Quiescent
I
DD2 (Q)
0.1
0.2
mA
V
I
= 0 V or V
DD1
Input Supply Current (25 Mbps)
(See Figure 4)
I
DD1 (25)
2.6
3.4
mA
12.5 MHz logic signal freq.
Output Supply Current
2
(25 Mbps)
(See Figure 5)
I
DD2 (25)
0.4
0.8
mA
12.5 MHz logic signal freq.
Input Supply Current (50 Mbps)
(See Figure 4)
I
DD1 (50)
4.6
6.6
mA
25 MHz logic signal freq.,
ADuM3100BR only
Output Supply Current
2
(50 Mbps)
(See Figure 5)
I
DD2 (50)
0.7
1.7
mA
25 MHz logic signal freq.,
ADuM3100BR only
Input Current
I
I
10
+0.01
+10
A
0 V
IN
V
DD1
Logic High Output Voltage
V
OH
V
DD2
0.1
3.3
V
I
O
= 20 A, V
I
= V
IH
V
DD2
0.5
3.0
V
I
O
= 2.5 mA, V
I
= V
IH
Logic Low Output Voltage
V
OL
0.0
0.1
V
I
O
= 20 A, V
I
= V
IL
0.04
0.1
V
I
O
= 400 A, V
I
= V
IL
0.3
0.4
V
I
O
= 2.5 mA, V
I
= V
IL
SWITCHING SPECIFICATIONS
For ADuM3100AR
Minimum Pulse Width
3
PW
40
ns
C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
4
25
Mbps
C
L
= 15 pF, CMOS signal levels
For ADuM3100BR
Minimum Pulse Width
3
PW
10
20
ns
C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
4
50
100
Mbps
C
L
= 15 pF, CMOS signal levels
For All Grades
Propagation Delay Time to Logic Low
Output
5, 6
(See Figure 7)
t
PHL
14.5
28
ns
C
L
= 15 pF, CMOS signal levels
Propagation Delay Time to Logic High
Output
5, 6
(See Figure 7)
t
PLH
15.0
28
ns
C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion |t
PLH
- t
PHL
|
6
PWD
0.5
3
ns
C
L
= 15 pF, CMOS signal levels
Change vs. Temperature
7
10
ps/C
C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew (Equal Temperature)
6, 8
t
PSK1
15
ns
C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew (Equal Temperature,
Supplies)
6, 8
t
PSK2
12
ns
C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time
t
R
, t
F
3
ns
C
L
= 15 pF, CMOS signal levels
Common-Mode Transient Immunity at
Logic Low/High Output
9
|CM
L
|, |CM
H
|
25
35
kV/s
V
I
= 0 or V
DD1
, V
CM
= 1000 V,
transient magnitude = 800 V
Input Dynamic Supply Current
10
I
DDI (D)
0.08
mA/Mbps
Output Dynamic Supply Current
10
I
DDO (D)
0.01
mA/Mbps
See notes on Page 6.
ADuM3100
Rev. A | Page 5 of 16
ELECTRICAL SPECIFICATIONS, MIXED 5 V/3 V OR 3 V/5 V OPERATION
1
5 V/3 V operation: 4.5 V V
DD1
5.5 V, 3.0 V V
DD2
3.6 V. 3 V/5 V operation: 3.0 V V
DD1
3.6 V, 4.5 V V
DD2
5.5 V. All
minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications
are at T
A
= 25C, V
DD1
= 3.3 V, V
DD2
= 5 V or V
DD1
= 5 V, V
DD2
= 3.3 V.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, Quiescent
I
DDI (Q)
5 V/3 V Operation
1.3
1.8
mA
3 V/5 V Operation
0.7
0.9
mA
Output Supply Current
2
, Quiescent
I
DDO (Q)
5 V/3 V Operation
0.1
0.2
mA
3 V/5 V Operation
0.15
0.25
mA
Input Supply Current, 25 Mbps
I
DDI (25)
5 V/3 V Operation
3.2
4.5
mA
12.5 MHz logic signal freq.
3 V/5 V Operation
2.6
3.4
mA
12.5 MHz logic signal freq.
Output Supply Current
2
, 25 Mbps
I
DDO (25)
5 V/3 V Operation
0.4
0.8
mA
12.5 MHz logic signal freq.
3 V/5 V Operation
0.6
1.1
mA
12.5 MHz logic signal freq.
Input Supply Current, 50 Mbps
I
DDI (50)
5 V/3 V Operation
5.5
8.0
mA
25 MHz logic signal freq.
3 V/5 V Operation
4.6
6.6
mA
25 MHz logic signal freq.
Output Supply Current
2
, 50 Mbps
I
DDO (50)
5 V/3 V Operation
0.7
1.7
mA
25 MHz logic signal freq.
3 V/5 V Operation
1.1
1.6
mA
25 MHz logic signal freq.
Input Currents
I
IA
10
+0.01
+10
A
0 V
IA
, V
IB
, V
IC
, V
ID
V
DD1
or V
DD2
Logic High Output Voltage, 5 V/3 V Operation
V
OH
V
DD2
0.1
3.3
V
I
O
= 20 A, V
I
= V
IH
V
DD2
0.5
3.0
V
I
O
= 2.5 mA, V
I
= V
IH
Logic Low Output Voltage, 5 V/3 V Operation
V
OL
0.0
0.1
V
I
O
= 20 A, V
I
= V
IL
0.04
0.1
V
I
O
= 400 A, V
I
= V
IL
0.3
0.4
V
I
O
= 2.5 mA, V
I
= V
IL
Logic High Output Voltage, 3 V/5 V Operation
V
OH
V
DD2
0.1
5.0
V
I
O
= 20 A, V
I
= V
IH
V
DD2
0.8
4.6
V
I
O
= 4 mA, V
I
= V
IH
Logic Low Output Voltage, 3 V/5 V Operation
V
OL
0.0
0.1
V
I
O
= 20 A, V
I
= V
IL
0.03
0.1
V
I
O
= 400 A, V
I
= V
IL
0.3
0.8
V
I
O
= 4 mA, V
I
= V
IL
SWITCHING SPECIFICATIONS
For ADuM3100AR
Minimum Pulse Width
3
PW
40
ns
C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
4
25
Mbps
C
L
= 15 pF, CMOS signal levels
For ADuM3100BR
Minimum Pulse Width
3
PW
20
ns
C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
4
50
Mbps
C
L
= 15 pF, CMOS signal levels
For All Grades
Propagation Delay Time to Logic Low/
High Output
5, 6
t
PHL,
t
PLH
5 V/3 V Operation (See Figure 8)
13
21
ns
C
L
= 15 pF, CMOS signal levels
3 V/5 V Operation (See Figure 9)
16
26
ns
C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
- t
PHL
|
6
PWD
5 V/3 V Operation
0.5
2
ns
C
L
= 15 pF, CMOS signal levels
3 V/5 V Operation
0.5
3
ns
C
L
= 15 pF, CMOS signal levels
ADuM3100
Rev. A | Page 6 of 16
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Change vs. Temperature
7
5 V/3 V Operation
3
ps/C
C
L
= 15 pF, CMOS signal levels
3 V/5 V Operation
10
ps/C
C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew (Equal Temperature)
6, 8
t
PSK1
5 V/3 V Operation
12
ns
C
L
= 15 pF, CMOS signal levels
3 V/5 V Operation
15
ns
C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew (Equal Temperature,
Supplies)
6, 8
t
PSK2
5 V/3 V Operation
9
ns
C
L
= 15 pF, CMOS signal levels
3 V/5 V Operation
12
ns
C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
t
R
, t
f
3
ns
C
L
= 15 pF, CMOS signal levels
Common-Mode Transient Immunity at
Logic Low/High Output
9
|CM
L
|, |CM
H
|
25
35
kV/s
V
I
= 0 or V
DD1
, V
CM
= 1000 V,
transient magnitude = 800 V
Input Dynamic Supply Current per Channel
10
I
DDI (D)
5 V/3 V Operation
0.09
mA/Mbps
3 V/5 V Operation
0.08
mA/Mbps
Output Dynamic Supply Current per Channel
10
I
DDO (D)
5 V/3 V Operation
0.01
mA/Mbps
3 V/5 V Operation
0.02
mA/Mbps
1
All voltages are relative to their respective ground.
2
Output supply current values are with no output load present. See Figure 4 and Figure 5 for information on supply current variation with logic signal frequency. See
the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.
3
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
5
t
PHL
is measured from the 50% level of the falling edge of the V
I
signal to the 50% level of the falling edge of the V
O
signal. t
PLH
is measured from the 50% level of the
rising edge of the V
I
signal to the 50% level of the rising edge of the V
O
signal.
6
Because the input thresholds of the ADuM3100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse-width
distortion can be affected by slow input rise/fall times. See the System-Level ESD Considerations and Enhancements section and Figure 13 to Figure 17 for information
on the impact of given input rise/fall times on these parameters.
7
Pulse-width distortion change vs. temperature is the absolute value of the change in pulse-width distortion for a 1C change in operating temperature.
8
t
PSK1
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating temperature and output load within the
recommended operating conditions. t
PSK2
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
9
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range
over which the common-mode is slewed.
10
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 4 and Figure 5 for information on
supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given
data rate and output load.
ADuM3100
Rev. A | Page 7 of 16
PACKAGE CHARACTERISTICS
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Resistance (Input-to-Output)
1
R
I-O
10
12
Capacitance (Input-to-Output)
1
C
I-O
1
pF
f = 1 MHz
Input Capacitance
2
C
I
4.0
pF
Input IC Junction-to-Case
JCI
46
C/W
Thermal Resistance
Thermocouple located at center
underside of package
Output IC Junction-to-Case
JCO
41
C/W
Thermal Resistance
Package Power Dissipation
PPD
240
mW
1
Device considered a 2-terminal device: Pin 1, Pin 2, Pin 3, and Pin 4 shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 shorted together.
2
Input capacitance is measured at Pin 2 (V
I
).
REGULATORY INFORMATION
The ADuM3100 is approved by the organizations listed in Table 5.
Table 5.
UL
CSA
VDE
Recognized under 1577
Approved under CSA Component
Certified according to
Component Recognition Program
1
Acceptance Notice No. 5A, C22.2 No. 1-98,
DIN EN 60747-5-2 (VDE 0884 Part 2): 200301
2
C22.2 No. 14-95, and C22.2 No. 950-95
DIN EN 60950 (VDE 0805): 200112; EN 60950: 2000
File E214100
File 205078
File 2471900-4880-0002
1
In accordance with UL 1577, each ADuM3100 is proof tested by applying an insulation test voltage 3000 V rms for 1 second (leakage detection current limit,
I
IO
5 A).
2
In accordance with DIN EN 60747-5-2, each ADuM3100 is proof tested by applying an insulation test voltage 1050 V
PEAK
for 1 second (partial discharge detection limit
5 pC). An asterisk (*) branded on the component designates DIN EN 60747-5-2 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter
Symbol
Value
Unit
Conditions
Minimum External Air Gap (Clearance)
L(I01)
4.90 min
mm
Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage)
L(I02)
4.01 min
mm
Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance)
0.017 min
mm
Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index)
CTI
>175
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
.
ADuM3100
Rev. A | Page 8 of 16
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
Table 7.
Description
Symbol
Characteristic
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage 150 V rms
I to IV
For Rated Mains Voltage 300 V rms
I to III
For Rated Mains Voltage 400 V rms
I to II
Climatic Classification
40/105/21
Pollution Degree (DIN VDE 0110, Table 5)
2
Maximum Working Insulation Voltage
V
IORM
560
V
PEAK
Input-to-Output Test Voltage, Method b1
V
IORM
1.875 = V
PR
, 100% Production Test, t
M
= 1 sec, Partial Discharge <5 pC
V
PR
1050
V
PEAK
Input-to-Output Test Voltage, Method a
V
PR
672
V
PEAK
After Environmental Tests Subgroup 1
V
IORM
1.6 = V
PR
, t
M
= 10 sec, Partial Discharge <5 pC
V
PR
896
V
PEAK
After Input and/or Output Safety Test Subgroup 2/3
V
IORM
1.2 = V
PR
, t
M
= 10 sec, Partial Discharge <5 pC
V
PR
672
V
PEAK
Highest Allowable Overvoltage (Transient Overvoltage, t
INI
= 60 sec)
V
TR
4000
V
PEAK
Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure, See Figure 2)
Case Temperature
T
S
150
C
Input Current
I
S
,
INPUT
160
mA
Output Current
I
S
,
OUTPUT
170
mA
Insulation Resistance at T
S
, V
IO
= 500 V
R
S
>10
9
This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by means of
protective circuits. The asterisk (*) on the package denotes DIN EN 60747-5-2 approval for 560 V
PEAK
working voltage.
CASE TEMPERATURE (C)
180
0
S
AF
E
T
Y
-
L
I
M
I
T
I
NG
CURRE
NT
(
m
A)
100
80
0
50
100
150
200
120
160
140
20
40
60
INPUT CURRENT
OUTPUT CURRENT
05
63
7-
0
02
Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 8.
Parameter
Symbol
Min
Max
Unit
Operating Temperature
T
A
-40
+105
C
Supply Voltages
1
V
DD1
,
V
DD2
3.0
5.5
V
Logic High Input Voltage,
5 V Operation
(See Figure 10 and Figure 11)
V
IH
2.0 V
DD1
V
Logic Low Input Voltage,
5 V Operation
1, 2
(See Figure 10 and Figure 11)
V
IL
0.0
0.8
V
Logic High Input Voltage,
3.3 V Operation
1, 2
(See Figure 10 and Figure 11)
V
IH
1.5
V
DD1
V
Logic Low Input Voltage,
3.3 V Operation
1, 2
(See Figure 10 and Figure 11)
V
IL
0.0
0.5
V
Input Signal Rise and Fall Times
1.0
ms
1
All voltages are relative to their respective ground.
2
Input switching thresholds have 300 mV of hysteresis. See the Method of
Operation, DC Correctness, and Magnetic Field Immunity section, Figure 18,
and Figure 19 for information on immunity to external magnetic fields.
ADuM3100
Rev. A | Page 9 of 16
ABSOLUTE MAXIMUM RATINGS
Table 9.
Parameter
Min
Max
Unit
Storage Temperature ,T
ST
-55
+150
C
Ambient Operating Temperature, T
A
-40
+125
C
Supply Voltages
1
, V
DD1
, V
DD2
-0.5
+6.5
V
Input Voltage
1
, V
I
-0.5
V
DD1
+ 0.5
V
Output Voltage
1
, V
O
-0.5
V
DD2
+ 0.5
V
Average Current, per Pin
2
Temperature 105C
-25
+25
mA
Common-Mode Transients
3
-100 +100
kV/s
1
All voltages are relative to their respective ground.
2
See Figure 2 for information on maximum allowable current for various
temperatures.
3
Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the Absolute Maximum Rating can cause latch-
up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Ambient temperature = 25C, unless otherwise noted.
Table 10. Truth Table (Positive Logic)
V
I
Input
V
DD1
State
V
DD2
State
V
O
Output
H
Powered
Powered
H
L
Powered
Powered
L
X
Unpowered
Powered
H
1
X
Powered
Unpowered
X
X
1
1
V
O
returns to V
I
state within 1 s of power restoration.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADuM3100
Rev. A | Page 10 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
DD1
1
1
V
I
2
V
DD1
1
3
GND
1
4
V
DD2
8
GND
2
2
7
V
O
6
GND
2
2
5
ADuM3100
TOP VIEW
(Not to Scale)
0
56
37-
003
1
PIN 1 AND PIN 3 ARE INTERNALLY CONNECTED. IT IS STRONGLY
RECOMMENDED THAT BOTH BE CONNECTED TO V
DD1
.
2
PIN 5 AND PIN 7 ARE INTERNALLY CONNECTED. IT IS STRONGLY
RECOMMENDED THAT BOTH BE CONNECTED TO GND
2
.
Figure 3. Pin Configuration
Table 11. Pin Function Descriptions
Pin
No. Mnemonic Description
1 V
DD1
Input Supply Voltage, 3.0 V to 5.5 V
2 V
I
Logic Input
3 V
DD1
Input Supply Voltage, 3.0 V to 5.5 V
4 GND
1
Input Ground
5 GND
2
Output Ground
6 V
O
Logic Output
7 GND
2
Output Ground
8 VDD
2
Output Supply Voltage, 3.0 V to 5.5 V
ADuM3100
Rev. A | Page 11 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
DATA RATE (Mbps)
20
0
CUR
RE
NT
(
m
A)
18
16
2
0
25
50
75
100
125
150
14
12
10
8
6
4
5V
3.3V
05
63
7-
00
4
Figure 4. Typical Input Supply Current vs.
Logic Signal Frequency for 5 V and 3.3 V Operation
DATA RATE (Mbps)
5
0
CURRE
NT
(
m
A)
3
2
1
0
25
50
75
100
125
150
5V
3.3V
4
0
56
37-
005
Figure 5. Typical Output Supply Current vs.
Logic Signal Frequency for 5 V and 3.3 V Operation
TEMPERATURE (C)
13
50
P
R
O
P
AG
AT
I
O
N DE
L
A
Y
(
n
s)
11
9
0
50
75
100
125
12
t
PHL
25
25
t
PLH
10
05
63
7-
0
06
Figure 6. Typical Propagation Delays vs. Temperature, 5 V Operation
18
50
14
13
12
25
25
50
100
125
15
17
16
0
75
t
PHL
t
PLH
TEMPERATURE (C)
P
R
O
P
AG
AT
I
O
N DE
L
A
Y
(
n
s)
05
637
-
00
7
Figure 7. Typical Propagation Delays vs. Temperature, 3.3 V Operation
TEMPERATURE (C)
P
R
O
P
AG
AT
I
O
N DE
L
A
Y
(
n
s)
14
50
11
10
9
25
25
50
100
125
12
13
0
75
t
PHL
t
PLH
05
63
7-
0
08
Figure 8. Typical Propagation Delays vs. Temperature, 5 V/3 V Operation
18
50
14
13
12
25
25
50
100
125
15
17
16
0
75
t
PHL
t
PLH
TEMPERATURE (C)
P
R
O
P
AG
AT
I
O
N DE
L
A
Y
(
n
s)
05
637
-
00
9
Figure 9. Typical Propagation Delays vs. Temperature, 3 V/5 V Operation
ADuM3100
Rev. A | Page 12 of 16
1.7
3.0
1.3
1.2
1.1
3.5
4.0
4.5
5.0
5.5
1.4
1.6
1.5
40C
+25C
+125C
INPUT SUPPLY VOLTAGE, V
DD1
(V)
I
N
P
UT
T
HRE
S
HO
L
D,
V
IT
H
(V
)
05
63
7-
0
10
Figure 10. Typical Input Voltage Switching Threshold,
Low-to-High Transition
INPUT SUPPLY VOLTAGE, V
DD1
(V)
1.4
3.0
I
NP
UT
T
HRE
S
HO
L
D
,
V
IT
H
(V
)
1.0
0.9
0.8
3.5
4.0
4.5
5.0
5.5
1.1
1.3
1.2
40C
+25C
+125C
05
637
-
01
1
Figure 11. Typical Input Voltage Switching Threshold,
High-to-Low Transition
ADuM3100
Rev. A | Page 13 of 16
APPLICATIONS
PC BOARD LAYOUT
The ADuM3100 digital isolator requires no external interface
circuitry for the logic interfaces. A bypass capacitor is
recommended at the input and output supply pins. The input
bypass capacitor can conveniently connect between Pin 3 and
Pin 4 (see Figure 12). Alternatively, the bypass capacitor can be
located between Pin 1 and Pin 4. The output bypass capacitor
can be connected between Pin 7 and Pin 8 or Pin 5 and Pin 8.
The capacitor value should be between 0.01 F and 0.1 F. The
total lead length between both ends of the capacitor and the
power supply pins should not exceed 20 mm.
V
DD1
V
1
(DATA)
GND
1
V
DD2
V
O
(DATA OUT)
GND
2
(OPTIONAL)
0563
7-
01
2
Figure 12. Recommended Printed Circuit Board Layout
SYSTEM-LEVEL ESD CONSIDERATIONS AND
ENHANCEMENTS
System-level ESD reliability (for example, per IEC 61000-4-x)
is highly dependent on system design which varies widely by
application. The ADuM3100 incorporates many enhancements
to make ESD reliability less dependent on system design. The
enhancements include:
ESD protection cells added to all input/output interfaces.
Key metal trace resistances reduced using wider geometry
and paralleling of lines with vias.
The SCR effect inherent in CMOS devices minimized by use
of guarding and isolation technique between PMOS and
NMOS devices.
Areas of high electric field concentration eliminated using
45 corners on metal traces.
Supply pin overvoltage prevented with larger ESD clamps
between each supply pin and its respective ground.
While the ADuM3100 improves system-level ESD reliability, it
is no substitute for a robust system-level design. See
Application
Note AN-793, ESD/Latch-Up Considerations with iCoupler
Isolation Products
for detailed recommendations on board
layout and system-level design.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay time describes the length of time it takes for a
logic signal to propagate through a component. Propagation
delay time to logic low output and propagation delay time to
logic high output refer to the duration between an input signal
transition and the respective output signal transition
(see Figure 13).
INPUT (V
I
)
OUTPUT (V
O
)
t
PLH
t
PHL
50%
50%
05
637
-
01
3
Figure 13. Propagation Delay Parameters
Pulse-width distortion is the maximum difference between t
PLH
and t
PHL
and provides an indication of how accurately the input
signal timing is preserved in the component output signal.
Propagation delay skew is the difference between the minimum
and maximum propagation delay values among multiple
ADuM3100 components operated at the same operating
temperature and having the same output load.
Depending on the input signal rise/fall time, the measured
propagation delay based on the input 50% level can vary from
the true propagation delay of the component (as measured from
its input switching threshold). This is due to the fact that the
input threshold, as is the case with commonly used optocouplers,
is at a different voltage level than the 50% point of typical input
signals. This propagation delay difference is:
LH
= t
PLH
- t
PLH
= (t
r
/0.8 V
I
)(0.5 V
1
- V
ITH (L-H)
)
HL
= t
PHL
- t
PHL
= (t
f
/0.8 V
I
)(0.5 V
1
- V
ITH (H-L)
)
where:
t
PLH
, t
PHL
= propagation delays as measured from the input
50%.
t
PLH
, t
PHL
= propagation delays as measured from the input
switching thresholds.
t
r
, t
f
= input 10% to 90% rise/fall time.
V
I
= amplitude of input signal (0 to V
I
levels assumed).
V
ITH (LH)
, V
ITH (HL)
= input switching thresholds.
LH
V
ITH(HL)
INPUT (V
I
)
V
ITH(LH)
V
I
HL
t
PHL
t'
PHL
t
PLH
t'
PLH
OUTPUT (V
O
)
50%
50%
05
637
-
01
4
Figure 14. Impact of Input Rise/Fall Time on Propagation Delay
ADuM3100
Rev. A | Page 14 of 16
INPUT RISE TIME (10%90%, ns)
4
1
P
RO
P
AG
AT
I
O
N DE
L
AY
C
HANG
E
,
LH
(n
s
)
2
0
3
4
8
9
10
3
1
5V INPUT SIGNAL
2
5
6
7
3.3V INPUT SIGNAL
05
63
7-
0
15
Figure 15. Typical Propagation Delay Change due to
Input Rise Time Variation (for V
DD1
= 3.3 V and 5 V)
INPUT RISE TIME (10%90%, ns)
0
1
P
RO
P
AG
AT
I
O
N DE
L
AY
C
HANG
E
,
HL
(n
s
)
2
4
3
4
8
9
10
1
3
2
5
6
7
05
63
7-
0
16
5V INPUT SIGNAL
3.3V INPUT SIGNAL
Figure 16. Typical Propagation Delay Change due to
Input Fall Time Variation (for V
DD1
= 3.3 V and 5 V)
The impact of the slower input edge rates can also affect the
measured pulse-width distortion as based on the input 50%
level. This impact can either increase or decrease the apparent
pulse-width distortion depending on the relative magnitudes of
t
PHL
, t
PLH
, and PWD. The case of interest here is the condition
that leads to the largest increase in pulse-width distortion. The
change in this case is given by
PWD
= PWD - PWD =
LH
-
HL
=
(t/0.8 V
1
)(V - V
ITH (L-H)
- V
ITH (H-L)
),(for t = t
r
= t
f
)
where:
PWD =
|t
PLH
- t
PHL
|
PWD =
|t
PLH
- t
PHL
|
This adjustment in pulse-width distortion is plotted as a
function of input rise/fall time in Figure 17.
INPUT RISE/FALL TIME (10%90%, ns)
6
1
P
UL
S
E
-
W
I
DT
H DI
S
T
O
RT
I
O
N ADJUS
T
M
E
NT
,
PW
D
(ns
)
0
3
4
8
9
10
2
5
6
7
5
4
3
2
1
05
63
7-
0
17
3.3V INPUT SIGNAL
5V INPUT SIGNAL
Figure 17. Typical Pulse-Width Distortion Adjustment due to
Input Rise/Fall Time Variation (at V
DD1
= 3.3 V and 5 V)
METHOD OF OPERATION, DC CORRECTNESS, AND
MAGNETIC FIELD IMMUNITY
Referring to Figure 1, the two coils act as a pulse transformer.
Positive and negative logic transitions at the isolator input
cause narrow (2 ns) pulses to be sent via the transformer to the
decoder. The decoder is bistable and therefore either set or reset
by the pulses indicating input logic transitions. In the absence
of logic transitions at the input for more than 2 s, a periodic
update pulse of the appropriate polarity is sent to ensure dc
correctness at the output. If the decoder does not receive any of
these update pulses for more than approximately 5 s, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a logic high state by the
watchdog timer circuit.
The limitation on the ADuM3100 magnetic field immunity
is set by the condition in which induced voltage in the
transformer receiving coil is sufficiently large to either falsely
set or reset the decoder. The analysis that follows defines the
conditions under which this can occur. The ADuM3100 3.3 V
operating condition is examined because it represents the most
susceptible mode of operation.
The pulses at the transformer output are greater than 1.0 V in
amplitude. The decoder has sensing thresholds at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (-d/dt) r
n
2
, n = 1, 2, . . . , N
where:
= magnetic flux density (gauss).
N = number of turns in receiving coil.
r
n
= radius of nth turn in receiving coil (cm).
ADuM3100
Rev. A | Page 15 of 16
Given the geometry of the receiving coil in the ADuM3100 and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 18.
MAGNETIC FIELD FREQUENCY (Hz)
100
MA
XI
MU
M A
L
L
O
W
A
B
L
E
MA
G
N
ET
I
C
F
L
U
X
DE
NS
I
T
Y
(
k
g
a
u
ss)
0.001
10
0.01
0.1
1
1k
10k
100k
1M
10M
100M
05
63
7-
01
8
Figure 18. Maximum Allowable External Magnetic Field
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it reduces the
received pulse from >1.0 V to 0.75 V--still well above the
0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from
the ADuM3100 transformers. Figure 19 shows the allowable
current magnitudes as a function of frequency for selected
distances. As can be seen, the ADuM3100 is extremely immune
and can be affected only by extremely large currents operated at
high frequency and very close to the component. For the 1 MHz
example noted, one would have to place a current of 0.5 kA
5 mm away from the ADuM3100 to affect the component's
operation.
MAGNETIC FIELD FREQUENCY (Hz)
1000
M
AX
I
M
UM
A
L
L
O
W
ABL
E
CURRE
NT
(
k
A)
0.01
100
0.1
1
10
1k
10k
100k
1M
10M
100M
05
63
7-
0
19
DISTANCE = 1m
DISTANCE = 100mm
DISTANCE = 5mm
Figure 19. Maximum Allowable Current for Current-to-ADuM3100 Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce sufficiently large error voltages to trigger the
thresholds of succeeding circuitry. Care should be taken in
the layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current of the ADuM3100 isolator is a function of
the supply voltage, the input data rate, and the output load.
The input supply current is given by
I
DDI
= I
DDI (Q)
f 0.5f
r
I
DDI
= I
DDI (D)
(2f f
r
) + I
DDI (Q)
f > 0.5f
r
The output supply current is given by
I
DDO
= I
DDO (Q)
f 0.5f
r
I
DDO
= (I
DDO (D)
+ (0.5 10
-3
) C
L
V
DDO
) (2f f
r
) + I
DDO (Q)
f > 0.5f
r
where:
I
DDI (D)
, I
DDO (D)
are the input and output dynamic supply currents
per channel (mA/Mbps).
C
L
is output load capacitance (pF).
V
DDO
is the output supply voltage (V).
f is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
f
r
is the input stage refresh rate (Mbps).
I
DDI (Q)
, I
DDO (Q)
are the specified input and output quiescent
supply currents (mA).
ADuM3100
Rev. A | Page 16 of 16
OUTLINE DIMENSIONS
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45
8
0
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8
5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
Figure 20. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
Temperature Range
Max Data
Rate (Mbps)
Minimum
Pulse Width (ns)
Package Description
Package
Option
ADuM3100ARZ
1
-40C to +105C
25
40
8-Lead SOIC_N
R-8
ADuM3100ARZ-RL7
1
-40C to +105C
25
40
8-Lead SOIC_N, 1,000 Piece Reel
R-8
ADuM3100BRZ
1
-40C to +105C
100
10
8-Lead SOIC_N
R-8
ADuM3100BRZ-RL7
1
-40C to +105C
100
10
8-Lead SOIC_N, 1,000 Piece Reel
R-8
1
Z = Pb-free part.
2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05637-0-3/06(A)
Document Outline
-
- APPLICATIONS
-
-
-
-
- ELECTRICAL SPECIFICATIONS, 5 V OPERATION
- ELECTRICAL SPECIFICATIONS, 3.3 V OPERATION
-
-
-
-
- DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
- RECOMMENDED OPERATING CONDITIONS
-
-
-
-
-
PDF 
ZIP