ASAHI KASEI
[AK2500B]
MS0005-E-00
- 1 -
1999/12
AK2500B
DS3/STS-1 Analog Line Receiver
GENERAL DESCRIPTION
The AK2500B is a DSP based line receiver. It
provides the analog receive line interface
functions for a 44.736 MHz DS3 or 51.84 MHz
STS-1 interface. The device operates from a
single +3.3 Volt supply and is transparent to the
framing format.
PACKAGE
-
24 pin SOP
FEATURE
-
"Robust" DSP based line receiver
-
AK2500B Provides Complete Analog Line
Receiver for DS3 and STS-1 Applications
-
Provides Line Equalization, and Clock and Data
Recovery Functions
APPLICATIONS
-
Interfacing network transmission equipment
such as SONET multiplexor and M13 to a DSX-
3 cross connect.
-
Interfacing customer premises equipment to a
line.
BLOCK DIAGRAM
GAIN and LINE
EQUALIZATION
DATA
RECOVERY
LOS
LOGIC
CLOCK
RECOVERY
RPDATA
RNDATA
RCLK
RLOS
RIN
RLOL
VDDA
VDDD
VDDC
VSSC
VSSD
VSSA
TREF
BREF
EXCLK
LOSTHR
IREF
MODE2
MODE1 RESET
ASAHI KASEI
[AK2500B]
MS0005-E-00
- 4 -
1999/12
PIN DESCRIPTION
No.
Pin Name
I/O
Function
1
IREF
O
Current reference output determined by the external resister.
External resistance 4.9 kohm(+/-1%) should be connected between this pin and
VSSA.
2
LOSTHR
I
Loss of Signal Threshold Control
The voltage forced on this pin controls the input loss-of-signal threshold. Three
settings are provided by forcing GND, VDD/2, or VDD at LOSTHR (see
Table
6
).
3
RLOL
O
Receive PLL Loss-of-Lock
Active High alarm. If the recovered clock frequency is larger than approximately
0.5% of EXCLK, RLOL alarm goes High.
4
RIN
I
Receive Input
Unbalanced analog receive input. The B3ZS receive signal is input to this pins.
Data and clock are recovered and output on RPDATA, RNDATA and RCLK.
5
VDDA
-
6
VDDA
-
Power Supply for the analog part. +3.3 volts.
7
RESET
I
Active low RESET. Pulled up to VDD with internal resister.
8
BREF
O
Bottom voltage reference level output.
An external capacitor (0.1
uF20%) should be connected between this pin and
VSSA.
9
TREF
O
Top voltage reference level output.
An external capacitor (0.1
uF20%) should be connected between this pin and
VSSA.
10
VSSA
-
Ground for the analog part. 0 volts.
11
VSSD
-
Ground for the digital part. 0 volts.
12
RLOS
O
Receive Loss-of-Signal.
This pin is set high on loss of the incoming signal at RIN.
13
EXCLK
I
External Reference Clock.
A valid DS3 or STS-1 clock must be provided at this input. The duty cycle of
EXCLK, referenced to VDD/2 levels, must be 40% - 60%. The EXCLK
frequency determines the operating frequency of the device.
14
VDDD
-
Power Supply for the digital part. +3.3 volts
15
VDDA
-
Power Supply for the analog part. +3.3 volts.
16
VDDC
-
Power Supply for the output buffer. +3.3 volts.
17
RCLK
O
Recovered Clock.
18
RNDATA
O
Receive Negative Data.
19
RPDATA
O
Receive Positive Data.
20
VSSC
-
Ground for the output buffer. 0 volts.
21
VSSA
-
22
VSSA
-
Ground for the analog part. 0 volts.
23
MODE1
I
24
MODE2
I
Mode Control.
Equalizer enable/bypass mode, Test mode are selectable as shown in
Table 4.
ASAHI KASEI
[AK2500B]
MS0005-E-00
- 5 -
1999/12
FUNCTIONAL DESCRIPTION
The AK2500B provides the basic receiver functions of a high-speed line card as shown in Fig.7.
The receiver extracts data and clock from a B3ZS coded signal and outputs clock and synchronized data.
Signal Requirements
Pulse characteristics are specified at the DSX-3.
Table 1. DS3 Interface Specification
Parameter
Specification
Line Rate
44.736Mbps20ppm
Line Code
B3ZS
Test Load
75
5%
Standards
GR-499-CORE , ANSI T1-102 , T1.404
Table 2. STS-1 Interface Specification
Parameter
Specification
Line Rate
51.840Mbps20ppm
Line Code
B3ZS
Test Load
75
5%
Standards
GR-253-CORE , ANSI T1-102
Equalization
The incoming data may have the loss of cable and/or flat. Cable type and length from the cross-connect are
specified as shown in Table 3. Equalizer compensates appropriately for a nominal DSX-3/STS-1 pulse as
attenuated by 0 - 450 feet of 728A cable.
Table 3. DS3/STS-1 Cable Specification
Parameter
Specification
Cable Type
Type 728A coaxial cable (or equivalent)
Cable Length
0 450 feet (from DSX-3 point)
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