Document Outline
- MACH 111-5/7/10/12/15
- DISTINCTIVE CHARACTERISTICS
- GENERAL DESCRIPTION
- BLOCK DIAGRAM
- CONNECTION DIAGRAM
- PIN DESIGNATIONS
- ORDERING INFORMATION
- FUNCTIONAL DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- OPERATING RANGES
- DC CHARACTERISTICS over COMMERCIAL operating ranges
- CAPACITANCE
- SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
- ABSOLUTE MAXIMUM RATINGS
- OPERATING RANGES
- DC CHARACTERISTICS over INDUSTRIAL operating ranges
- CAPACITANCE
- SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges
- TYPICAL CURRENT vs. VOLTAGE (I-V) CHARACTERISTICS
- TYPICAL I CC CHARACTERISTICS
- TYPICAL THERMAL CHARACTERISTICS
- SWITCHING WAVEFORMS
- KEY TO SWITCHING WAVEFORMS
- SWITCHING TEST CIRCUIT*
- f MAX PARAMETERS
- ENDURANCE CHARACTERISTICS
- INPUT/OUTPUT EQUIVALENT SCHEMATICS
- POWER-UP RESET
- DEVELOPMENT SYSTEMS
- APPROVED PROGRAMMERS
- APPROVED ADAPTER MANUFACTURERS
- APPROVED ON-BOARD ISP PROGRAMMING TOOLS
- PHYSICAL DIMENSIONS
- PHYSICAL DIMENSIONS
FINAL
Publication# 20420
Rev: B
Amendment/+1
Issue Date: June 1998
COM'L: -5/7/10/12/15
IND: -7/10/12/14/18
MACH
111-5/7/10/12/15
High-Performance EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
x
44 Pins in PLCC and TQFP
x
32 Macrocells
x
5 ns t
PD
Commercial, 7.5 ns t
PD
Industrial
x
182 MHz f
CNT
x
32 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs
x
32 Flip-flops; 4 clock choices
x
2 "PALCE26V16" blocks
x
SpeedLockingTM for guaranteed fixed timing
x
Bus-FriendlyTM Inputs and I/Os
x
Peripheral Component Interconnect (PCI) compliant (-5/-7/-10/-12)
x
Programmable power-down mode
x
Safe for mixed supply voltage system designs
x
Pin-compatible with the MACH211
GENERAL DESCRIPTION
The MACH111 is a member of Vantis' high-performance EE CMOS MACH 1 & 2 families. This
device has approximately three times the logic macrocell capability of the popular PALCE22V10
without loss of speed.
The MACH111 consists of two PAL
blocks interconnected by a programmable switch matrix.
The two PAL blocks are essentially "PALCE26V16" structures complete with product-term arrays
and programmable macrocells, which can be programmed as high speed or low power. The
switch matrix connects the PAL blocks to each other and to all input pins, providing a high
degree of connectivity between the fully connected PAL blocks. This allows designs to be placed
and routed efficiently.
The MACH111 macrocell provides either registered or combinatorial outputs with programmable
polarity. If a registered configuration is chosen, the register can be configured as D-type or T-
type to help reduce the number of product terms. The register type decision can be made by
the designer or by the software. All macrocells can be connected to an I/O cell. If a buried
macrocell is desired, the internal feedback path from the macrocell can be used, which frees up
the I/O pin for use as an input.
Vantis offers software design support for MACH devices through its own development system
and device fitters integrated into third-party CAE tools. Platform support extends across PCs,
Sun and HP workstations under advanced operating systems such as Windows 3.1, Windows 95
and NT, SunOS and Solaris, and HPUX.
2
MACH111-5/7/10/12/15
MACHXL
software is a complete development system for the PC, supporting Vantis' MACH
devices. It supports design entry with Boolean and behavioral syntax, state machine syntax and
truth tables. Functional simulation and static timing analysis are also included in this easy-to-
use system. This development system includes high-performance device fitters for all MACH
devices.
The same fitter technology included in MACHXL software is seamlessly incorporated into third-party
tools from leading CAE vendors such as Synario, Viewlogic, Mentor Graphics, Cadence and MINC.
Interface kits and MACHXL configurations are also available to support design entry and verification
with other leading vendors such as Synopsys, Exemplar, OrCAD, Synplicity and Model Technology.
These MACHXL configurations and interfaces accept EDIF 2.0.0 netlists, generate JEDEC files for
MACH devices, and create industry-standard SDF, VITAL-compliant VHDL and Verilog output files for
design simulation.
Vantis offers in-system programming support for MACH devices through its MACHPRO
software enabling MACH device programmability through JTAG compliant ports and easy-to-use
PC interface. Additionally, MACHPRO generated vectors work seamlessly with HP3070, GenRad
and Teradyne testers to program MACH devices or test them for connectivity.
All MACH devices are supported by industry standard programmers available from a number of
vendors. These programmer vendors include Advin Systems, BP Microsystems, Data I/O
Corporation, Hi-Lo Systems, SMS GmbH, Stag House, and System General.
MACH111-5/7/10/12/15
3
BLOCK DIAGRAM
52 x 70
AND Logic Array
and
Logic Allocator
I/O
0
I/O
15
I/O Cells
Macrocells
Switch Matrix
16
OE
20420B-1
16
16
16
26
2
52 x 70
AND Logic Array
and
Logic Allocator
I/O
16
I/O
31
CLK
3
/I
5
CLK
1
/I
2
I/O Cells
Macrocells
OE
26
2
16
16
16
16
4
2
4
4
I
0
-I
1
/CLK
0
I
3
-I
4
/CLK
2
Block A
Block B
4
4
4
MACH111-5/7/10/12/15
CONNECTION DIAGRAM
Top View
44-Pin PLCC
Note:
Pin-compatible with the MACH211SP and MACH211.
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I
= Input
I/O
= Input/Output
V
CC
= Supply Voltage
Block A
Block B
1 44 43 42
5
4
3
2
6
41 40
7
8
9
10
11
12
13
14
15
16
17
23 24 25 26
19 20 21 22
18
27 28
39
38
37
36
35
34
33
32
31
30
29
I/O5
I/O6
I/O7
I0
CLK0/I1
GND
CLK1/I2
I/O8
I/O9
I/O10
I/O11
I/O27
I/O26
I/O25
I/O24
CLK3/I5
GND
CLK2/I4
I3
I/O23
I/O22
I/O21
I/O12
I/O13
I/O14
I/O15
V
CC
GND
I/O16
I/O17
I/O18
I/O19
I/O20
I/O4
I/O3
I/O2
I/O1
I/O0
GND
V
CC
I/O31
I/O30
I/O29
I/O28
20420B-2
MACH111-5/7/10/12/15
5
CONNECTION DIAGRAM
Top View
44-Pin TQFP
Note:
Pin-compatible with the MACH211SP.
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I
= Input
I/O
= Input/Output
V
CC
= Supply Voltage
Block B
Block A
I/O12
I/O13
I/O14
I/O15
V
CC
GND
I/O16
I/O17
I/O18
I/O19
I/O20
I/O4
I/O3
I/O2
I/O1
I/O0
GND
V
CC
I/O31
I/O30
I/O29
I/O28
I/O27
I/O26
I/O25
I/O24
CLK3/I5
GND
CLK2/I4
I3
I/O23
I/O22
I/O21
I/O5
I/O6
I/O7
I0
CLK0/I1
GND
CLK1/I2
I/O8
I/O9
I/O10
I/O11
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
20420B-3
6
MACH111-5/7/10/12/15 (Com'l)
ORDERING INFORMATION
Commercial Products
Vantis programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
Valid Combinations
The Valid Combinations table lists configurations planned to
be supported in volume for this device. Consult the local
Vantis sales office to confirm availability of specific valid
combinations and to check on newly released combinations.
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
MACH
111
-5
J
C
DEVICE NUMBER
111
= 32 Macrocells, 44 Pins,
Power-Down option,
Bus-Friendly Inputs
OPERATING CONDITIONS
C = Commercial (0
C to +70
C)
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
V = 44-Pin Thin Quad Flat Pack
(PQT044)
SPEED
-5 = 5 ns t
PD
-7 = 7.5 ns t
PD
-10 = 10 ns t
PD
-12 = 12 ns t
PD
-15 = 15 ns t
PD
Valid Combinations
MACH111-5
JC, VC
MACH111-7
MACH111-10
MACH111-12
MACH111-15
MACH111-7/10/12/14/18 (Ind)
7
ORDERING INFORMATION
Industrial Products
Vantis programmable logic products for industrial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
Valid Combinations
The Valid Combinations table lists configurations planned to
be supported in volume for this device. Consult the local
Vantis sales office to confirm availability of specific valid
combinations and to check on newly released combinations.
DEVICE NUMBER
111
= 32 Macrocells, 44 Pins,
Power-Down option,
Bus-Friendly Inputs
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
MACH
111
-7
J
I
OPERATING CONDITIONS
I = Industrial (40
C to +85
C)
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
SPEED
-7 = 7.5 ns t
PD
-10 = 10 ns t
PD
-12 = 12 ns t
PD
-14 = 14 ns t
PD
-18 = 18 ns t
PD
Valid Combinations
MACH111-7
JI
MACH111-10
MACH111-12
MACH111-14
MACH111-18
8
MACH111-5/7/10/12/15
FUNCTIONAL DESCRIPTION
The MACH111 consists of two PAL blocks connected by a switch matrix. There are 32 I/O pins
and 2 dedicated input pins feeding the switch matrix. These signals are distributed to the two
PAL blocks for efficient design implementation. There are four clock pins that can also be used
as dedicated inputs.
The PAL Blocks
Each PAL block in the MACH111 (Figure 1) contains a 64-product-term logic array, a logic
allocator, 16 macrocells, and 16 I/O cells. The switch matrix feeds each PAL block with 26 inputs.
This makes the PAL block look effectively like an independent "PALCE26V16."
There are four additional output enable product terms in each PAL block. For purposes of output
enable, the 16 I/O cells are divided into 2 banks of 8 macrocells. Each bank is allocated two of
the output enable product terms.
An asynchronous reset product term and an asynchronous preset product term are provided for
flip-flop initialization. All flip-flops within the PAL block are initialized together.
The Switch Matrix
The MACH111 switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each
PAL block provides 16 internal feedback signals and 16 I/O feedback signals. The switch matrix
distributes these signals back to the PAL blocks in an efficient manner that also provides for high
performance. The design software automatically configures the switch matrix when fitting a
design into the device.
The Product-term Array
The MACH111 product-term array consists of 64 product terms for logic use, and 6
special-purpose product terms. Four of the special-purpose product terms provide
programmable output enable; one provides asynchronous reset, and one provides asynchronous
preset. Two of the output enable product terms are used for the first eight I/O cells; the other
two control the last eight macrocells.
The Logic Allocator
The logic allocator in the MACH111 takes the 64 logic product terms and allocates them to the
16 macrocells as needed. Each macrocell can be driven by up to 12 product terms. The design
software automatically configures the logic allocator when fitting the design into the device.
Table 1 illustrates which product term clusters are available to each macrocell within a PAL
block. Refer to Figure 1 for cluster and macrocell numbers.
Table 1.
Logic Allocation
Output Macrocell
Available Clusters
Output Macrocell
Available Clusters
M
0
C
0
, C
1
M
8
C
8
, C
9
M
1
C
0
, C
1
, C
2
M
9
C
8
, C
9
, C
10
M
2
C
1
, C
2
, C
3
M
10
C
9
, C
10
, C
11
M
3
C
2
, C
3
, C
4
M
11
C
10
, C
11
, C
12
M
4
C
3
, C
4
, C
5
M
12
C
11
, C
12
, C
13
M
5
C
4
, C
5
, C
6
M
13
C
12
, C
13
, C
14
M
6
C
5
, C
6
, C
7
M
14
C
13
, C
14
, C
15
M
7
C
6
, C
7
M
15
C
14
, C
15
MACH111-5/7/10/12/15
9
The Macrocell
The MACH111 macrocells can be configured as either registered or combinatorial, with
programmable polarity. The macrocell provides internal feedback whether configured as
registered or combinatorial. The flip-flops can be configured as D-type or T-type, allowing for
product-term optimization.
The flip-flops can individually select one of four clock pins, which are also available as data inputs.
The registers are clocked on the LOW-to-HIGH transition of the clock signal. The flip-flops can also
be asynchronously initialized with the common asynchronous reset and preset product terms.
The I/O Cell
The I/O cell in the MACH111 consists of a three-state output buffer. The three-state buffer can
be configured in one of three ways: always enabled, always disabled, or controlled by a product
term. If product term control is chosen, one of two product terms may be used to provide the
control. The two product terms that are available are common to eight I/O cells. Within each
PAL block, two product terms are available for selection by the first eight three-state outputs;
two other product terms are available for selection by the last eight three-state outputs.
SpeedLocking for Guaranteed Fixed Timing
The unique MACH 1 & 2 architecture is designed for high performance--a metric that is met in
both raw speed, but even more importantly, guaranteed fixed speed. Using the design of the
central switch matrix, the MACH111 product offers the SpeedLocking feature, which allows a
stable fixed pin-to-pin delay, independent of logic paths, routing resources and design refits for
up to 12 product terms per output. Other non-Vantis CPLDs incur serious timing delays as
product terms expand beyond their typical 4 or 5 product-term limits. Speed and SpeedLocking
combine for continuous, high performance required in today's demanding designs.
Bus-Friendly Inputs and I/Os
The MACH111 inputs and I/Os include two inverters in series which loop back to the input. This
double inversion reinforces the state of the input and pulls the voltage away from the input
threshold voltage. Unlike a pull-up, this configuration cannot cause contention on a bus. For an
illustration of this configuration, please turn to the Input/Output Equivalent Schematics section.
PCI Compliant
The MACH111-5/7/10/12 is fully compliant with the PCI Local Bus Specification published by
the PCI Special Interest Group. The MACH111-5/7/10/12's predictable timing ensures
compliance with the PCI AC specifications independent of the design.
Power-Down Mode
The MACH111 features a programmable low-power mode in which individual signal paths can be
programmed as low power. These low-power speed paths will be slightly slower than the
non-low-power paths. This feature allows speed critical paths to run at maximum frequency while
the rest of the paths operate in the low-power mode, resulting in power savings of up to 50%.
Safe for Mixed Supply Voltage System Designs
The MACH111 is safe for mixed supply voltage system designs. The 5-V device will not overdrive
3.3-V devices above the output voltage of 3.3 V, while it accepts inputs from other 3.3-V devices.
Thus, the MACH111 provides easy-to-use mixed-voltage design compatibility.
10
MACH111-5/7/10/12/15
0
4
8
12
16
20
24
28
40
32
43
36
0
4
8
12
16
20
24
28
40
32
43
36
I/O
Cell
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Switch
Matrix
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
Output Enable
Output Enable
CLK
16
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
16
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
2
47
51
47
51
0
Logic Allocator
63
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
8
C
9
C
10
C
11
C
12
C
13
C
14
C
15
M
3
M
6
M
5
M
4
M
2
M
1
M
0
M
9
M
8
M
7
M
10
M
11
M
12
M
13
M
14
M
15
20420B-4
Figure 1.
MACH111 PAL Block
MACH111-5/7/10/12/15 (Com'l)
11
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . 65
C to +150
C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . 55
C to +125
C
Device Junction Temperature . . . . . . . . . . . . . +150
C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . . 0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . .0.5 V to V
CC
+ 0.5 V
DC Output or
I/O Pin Voltage . . . . . . . . . . . . . 0.5 V to V
CC
+ 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (T
A
= 0
C to 70
C) . . . . . . . . . 200 mA
Str esses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T
A
)
Operating in Free Air . . . . . . . . . . . . . . . 0
C to +70
C
Supply Voltage (V
CC
)
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of I
IL
and I
OZL
(or I
IH
and I
OZH
).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
V
OUT
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 16-bit up/down counter program in low-power mode. This pattern is programmed in each PAL block and is
capable of being enabled and reset.
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
V
OH
Output HIGH Voltage
I
OH
= 3.2 mA, V
CC
= Min, V
IN
= V
IH
or V
IL
2.4
V
V
OL
Output LOW Voltage
I
OL
= 16 mA, V
CC
= Min, V
IN
= V
IH
or V
IL
0.5
V
V
IH
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage
for all Inputs (Note 1)
2.0
V
V
IL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for
all Inputs (Note 1)
0.8
V
I
IH
Input HIGH Current
V
IN
= 5.25 V, V
CC
= Max (Note 2)
10
A
I
IL
Input LOW Current
V
IN
= 0 V, V
CC
= Max (Note 2)
10
A
I
OZH
Off-State Output Leakage Current
HIGH
V
OUT
= 5.25 V, V
CC
= Max
V
IN
= V
IH
or V
IL
(Note 2)
10
A
I
OZL
Off-State Output Leakage Current
LOW
V
OUT
= 0 V, V
CC
= Max
V
IN
= V
IH
or V
IL
(Note 2)
10
A
I
SC
Output Short-Circuit Current
V
OUT
= 0.5 V, V
CC
= Max (Note 3)
30
160
mA
I
CC
Supply Current (Static)
V
CC
= 5 V, T
A
= 25
C, f = 0 MHz (Note 4)
40
mA
Supply Current (Active)
V
CC
= 5 V, T
A
= 25
C, f = 1 MHz (Note 4)
45
mA
12
MACH111-5/7/10/12/15 (Com'l)
CAPACITANCE (Note 1)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
frequency may be affected.
2. See Switching Test Circuit for test conditions.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
C
IN
Input Capacitance
V
IN
= V
CC
0.5 V
V
CC
= 5.0 V, T
A
= 25
C
f = 1 MHz
6
pF
C
OUT
Output Capacitance
V
OUT
= 2.0 V
8
pF
Paramete
r Symbol
Parameter Description
-5
-7
-10
-12
-15
Unit
Min
Max
Min
Max Min Max
Min
Max Min Max
t
PD
Input, I/O, or Feedback to Combinatorial
Output
5
7.5
10
12
15
ns
t
S
Setup Time from Input, I/O, or
Feedback to Clock
D-type
3.5
5.5
6.5
7
10
ns
T-type
4
6.5
7.5
8
11
ns
t
H
Register Data Hold Time
0
0
0
0
0
ns
t
CO
Clock to Output
3.5
5
6
8
10
ns
t
WL
Clock Width
LOW
2.5
3
5
6
6
ns
t
WH
HIGH
2.5
3
5
6
6
ns
f
MAX
Maximum
Frequency
(Note 1)
External
Feedback
1/(t
S
+ t
CO
)
D-type
143
95
80
66.7
50
MHz
T-type
133
87
74
62.5
47.6
MHz
Internal Feedback
(f
CNT
)
D-type
182
133
100
76.9
66.6
MHz
T-type
167
125
91
71.4
55.5
MHz
No
Feedback
1/(t
WL
+ t
WH
)
200
166.7
100
83.3
83.3
MHz
t
AR
Asynchronous Reset to Registered Output
7.5
9.5
11
16
20
ns
t
ARW
Asynchronous Reset Width (Note 1)
4.5
5
7.5
12
15
ns
t
ARR
Asynchronous Reset Recovery Time
4.5
5
7.5
8
10
ns
t
AP
Asynchronous Preset to Registered Output
7.5
9.5
11
16
20
ns
t
APW
Asynchronous Preset Width (Note 1)
4.5
5
7.5
12
15
ns
t
APR
Asynchronous Preset Recovery Time
(Note 1)
4.5
5
7.5
8
10
ns
t
EA
Input, I/O, or Feedback to Output Enable
7.5
9.5
10
12
15
ns
t
ER
Input, I/O, or Feedback to Output Disable
7.5
9.5
10
12
15
ns
t
LP
t
PD
Increase for Powered-down Macrocell
(Note 3)
10
10
10
10
10
ns
t
LPS
t
S
Increase for Powered-down Macrocell
(Note 3)
7
7
7
7
7
ns
t
LPCO
t
CO
Increase for Powered-down Macrocell
(Note 3)
3
3
3
3
3
ns
t
LPEA
t
EA
Increase for Powered-down Macrocell
(Note 3)
10
10
10
10
10
ns
MACH111-7/10/12/14/18 (Ind)
13
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . 65
C to +150
C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . 55
C to +125
C
Device Junction Temperature . . . . . . . . . . . . . +150
C
Supply Voltage
with Respect to Ground . . . . . . . . . . 0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . .0.5 V to V
CC
+ 0.5 V
DC Output
or I/O Pin Voltage. . . . . . . . . . . 0.5 V to V
CC
+ 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (T
A
= 40
C to +85
C) . . . . . . 200 mA
Str esses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Temperature (T
A
)
Operating in Free Air . . . . . . . . . . . . . . 40
C to +85
C
Supply Voltage (V
CC
)
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC CHARACTERISTICS over INDUSTRIAL operating ranges
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of I
IL
and I
OZL
(or I
IH
and I
OZH
).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
V
OUT
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 16-bit up/down counter program in low-power mode. This pattern is programmed in each PAL block and is
capable of being enabled and reset.
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
V
OH
Output HIGH Voltage
I
OH
= 3.2 mA, V
CC
= Min, V
IN
= V
IH
or V
IL
2.4
V
V
OL
Output LOW Voltage
I
OL
= 16 mA, V
CC
= Min, V
IN
= V
IH
or V
IL
0.5
V
V
IH
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for all
Inputs (Note 1)
2.0
V
V
IL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for all
Inputs (Note 1)
0.8
V
I
IH
Input HIGH Current
V
IN
= 5.25 V, V
CC
= Max (Note 2)
10
A
I
IL
Input LOW Current
V
IN
= 0 V, V
CC
= Max (Note 2)
10
A
I
OZH
Off-State Output Leakage
Current HIGH
V
OUT
= 5.25 V, V
CC
= Max
V
IN
= V
IH
or V
IL
(Note 2)
10
A
I
OZL
Off-State Output Leakage
Current LOW
V
OUT
= 0 V, V
CC
= Max
V
IN
= V
IH
or V
IL
(Note 2)
10
A
I
SC
Output Short-Circuit
Current
V
OUT
= 0.5 V, V
CC
= Max (Note 3)
30
160
mA
I
CC
Supply Current (Static)
V
CC
= 5 V, T
A
= 25
C, f = 0 MHz (Note 4)
40
mA
Supply Current (Active)
V
CC
= 5 V, T
A
= 25
C, f = 1 MHz (Note 4)
45
mA
14
MACH111-7/10/12/14/18 (Ind)
CAPACITANCE (Note 1)
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
frequency may be affected.
2. See Switching Test Circuit for test conditions.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
C
IN
Input Capacitance
V
IN
= V
CC
0.5 V
V
CC
= 5.0 V, T
A
= 25
C
f = 1 MHz
6
pF
C
OUT
Output Capacitance
V
OUT
= 2.0 V
8
pF
Parameter
Symbol
Parameter Description
-7
-10
-12
-14
-18
Unit
Min
Max Min
Max
Min Max Min
Max
Min Max
t
PD
Input, I/O, or Feedback to Combinatorial
Output
7.5
10
12
14
18
ns
t
S
Setup Time from Input, I/O, or
Feedback to Clock
D-type
5.5
6.5
7
8.5
12
ns
T-type
6.5
7.5
8
10
13.5
ns
t
H
Register Data Hold Time
0
0
0
0
0
ns
t
CO
Clock to Output
5
6
8
10
12
ns
t
WL
Clock Width
LOW
3
5
6
6
7.5
ns
t
WH
HIGH
3
5
6
6
7.5
ns
f
MAX
Maximum
Frequency
(Note 1)
External
Feedback
1/(t
S
+ t
CO
)
D-type
95
80
66.7
54
40
MHz
T-type
87
74
62.5
50
38
MHz
Internal Feedback
(f
CNT
)
D-type
133
100
76.9
61.5
53
MHz
T-type
125
91
71.4
57
44
MHz
No
Feedback
1/(t
WL
+ t
WH
)
166.7
100
83.3
83.3
61.5
MHz
t
AR
Asynchronous Reset to Registered Output
9.5
11
16
19.5
24
ns
t
ARW
Asynchronous Reset Width (Note 1)
5
7.5
12
14.5
18
ns
t
ARR
Asynchronous Reset Recovery Time
5
7.5
8
10
12
ns
t
AP
Asynchronous Preset to Registered Output
9.5
11
16
19.5
24
ns
t
APW
Asynchronous Preset Width (Note 1)
5
7.5
12
14.5
18
ns
t
APR
Asynchronous Preset Recovery Time
5
7.5
8
10
12
ns
t
EA
Input, I/O, or Feedback to Output Enable
(Note 1)
9.5
10
12
14.5
18
ns
t
ER
Input, I/O, or Feedback to Output Disable
(Note 1)
9.5
10
12
14.5
18
ns
t
LP
t
PD
Increase for Powered-down Macrocell
(Note 3)
10
10
10
10
10
ns
t
LPS
t
S
Increase for Powered-down Macrocell
(Note 3)
7
7
7
7
7
ns
t
LPCO
t
CO
Increase for Powered-down Macrocell
(Note 3)
3
3
3
3
3
ns
t
LPEA
t
EA
Increase for Powered-down Macrocell
(Note 3)
10
10
10
10
10
ns
MACH111-5/7/10/12/15
15
TYPICAL CURRENT vs. VOLTAGE (I-V) CHARACTERISTICS
V
CC
= 5.0 V, T
A
= 25
C
-0.8 -0.6 -0.4
.2
-0.2
-1.0
.4
.6
1.0
.8
60
40
20
-20
-40
80
-60
-80
20420B-5
Output, LOW
V
OL
(V)
I
OL
(mA)
20420B-7
Input
I
I
(mA)
V
I
(V)
20
-40
-60
-80
-2
-1
1
2
3
-20
4
5
-100
20420B-6
I
OH
(mA)
V
OH
(V)
25
-50
-75
-100
-3
-2
-1
1
2
3
-25
-125
-150
4
5
Output, HIGH
16
MACH111-5/7/10/12/15
TYPICAL I
CC
CHARACTERISTICS
V
CC
= 5 V, T
A
= 25
C
The selected "typical" pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.
Maximum frequency shown uses internal feedback and a D-type register.
High Speed
150
125
100
75
50
25
0
0
10
20
30
40
50
60
70
80
90
I
CC
(mA)
Frequency (MHz)
Low Power
100
110 120 130 140 150
20420B-6
MACH111-5/7/10/12/15
17
TYPICAL THERMAL CHARACTERISTICS
Measured at 25
C ambient. These parameters are not tested.
Plastic
jc
Considerations
The data listed for plastic
jc
are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the
jc
measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the
package. Furthermore,
jc
tests on packages are performed in a constant-temperature bath, keeping the package surface at a
constant temperature. Therefore, the measurements can only be used in a similar environment. The thermal measurements are
taken with components on a six-layer printed circuit board.
SWITCHING WAVEFORMS
Notes:
1. V
T
= 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns4 ns typical.
Parameter
Symbol
Parameter Description
Typ
Unit
TQFP
PLCC
jc
Thermal impedance, junction to case
11
15
C/W
ja
Thermal impedance, junction to ambient
40
24
C/W
jma
Thermal impedance, junction to ambient with air flow
200 lfpm air
35
18
C/W
400 lfpm air
33
17
C/W
600 lfpm air
32
16
C/W
800 lfpm air
31
15
C/W
20420B-7
Combinatorial Output
t
PD
Input, I/O, or
Feedback
Combinatorial
Output
V
T
V
T
20420B-8
20420B-9
Registered Output
Clock Width
V
T
Input, I/O, or
Feedback
Registered
Output
t
S
t
CO
V
T
t
H
V
T
Clock
t
WH
Clock
t
WL
18
MACH111-5/7/10/12/15
SWITCHING WAVEFORMS
Notes:
1. V
T
= 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns4 ns typical.
V
T
V
T
t
ARW
V
T
t
AR
Input, I/O, or
Feedback
Registered
Output
Clock
t
ARR
20420B-10
Asynchronous Reset
Input, I/O,
or Feedback
V
T
V
T
t
APW
V
T
t
AP
t
APR
Registered
Output
Clock
20420B-11
Asynchronous Preset
20420B-12
Output Disable/Enable
V
T
V
T
Outputs
t
ER
t
EA
V
OH
0.5 V
V
OL
+ 0.5 V
Input, I/O, or
Feedback
MACH111-5/7/10/12/15
19
KEY TO SWITCHING WAVEFORMS
SWITCHING TEST CIRCUIT*
* Switching several outputs simultaneously should be avoided for accurate measurement.
Specification
S
1
C
L
Commercial
Measured Output Value
R
1
R
2
t
PD
, t
CO
Closed
35 pF
300
390
1.5 V
t
EA
Z
H: Open
Z
L: Closed
t
ER
H
Z: Open
L
Z: Closed
5 pF
H
Z: V
OH
0.5 V
L
Z: V
OL
+ 0.5 V
Must be
Steady
May
Change
from H to L
May
Change
from L to H
Does Not
Apply
Don't Care,
Any Change
Permitted
Will be
Steady
Will be
Changing
from H to L
Will be
Changing
from L to H
Changing,
State
Unknown
Center
Line is High-
Impedance
"Off" State
WAVEFORM
INPUTS
OUTPUTS
KS000010-PAL
20420B-13
C
L
Output
R
1
R
2
S
1
Test Point
5 V
20
MACH111-5/7/10/12/15
f
MAX
PARAMETERS
The parameter f
MAX
is the maximum clock rate at which the device is guaranteed to operate.
Because the flexibility inherent in programmable logic devices offers a choice of clocked
flip-flop designs, f
MAX
is specified for three types of synchronous designs.
The first type of design is a state machine with feedback signals sent off-chip. This external
feedback could go back to the device inputs, or to a second device in a multi-chip state machine.
The slowest path defining the period is the sum of the clock-to-output time and the input setup
time for the external signals (t
S
+ t
CO
). The reciprocal, f
MAX
, is the maximum frequency with
external feedback or in conjunction with an equivalent speed device. This f
MAX
is designated
"f
MAX
external."
The second type of design is a single-chip state machine with internal feedback only. In this
case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these
conditions, the period is limited by the internal delay from the flip-flop outputs through the
internal feedback and logic to the flip-flop inputs. This f
MAX
is designated "f
MAX
internal". A
simple internal counter is a good example of this type of design; therefore, this parameter is
sometimes called "f
CNT.
"
The third type of design is a simple data path application. In this case, input data is presented to the
flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited
by the sum of the data setup time and the data hold time (t
S
+ t
H
). However, a lower limit for the period
of each f
MAX
type is the minimum clock period (t
WH
+ t
WL
). Usually, this minimum clock period
determines the period for the third f
MAX
, designated "f
MAX
no feedback." All frequencies except f
MAX
internal are calculated from other measured AC parameters. f
MAX
internal is measured directly.
LOGIC
REGISTER
CLK
LOGIC
REGISTER
CLK
t
CO
t
S
t
S
f
MAX
Internal
(f
CNT
)
f
MAX
External
1/(t
s
+
t
CO
)
t
S
LOGIC
REGISTER
CLK
f
MAX
No Feedback; 1/(t
s
+
t
H
) or 1/(t
WH
+
t
WL
)
(SECOND
CHIP)
20420B-14
MACH111-5/7/10/12/15
21
ENDURANCE CHARACTERISTICS
The MACH families are manufactured using Vantis' advanced Electrically Erasable process. This
technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device
can be erased and reprogrammed, a feature which allows 100% testing at the factory.
Endurance Characteristics
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Parameter
Symbol
Parameter Description
Units
Test Conditions
t
DR
Min Pattern Data Retention Time
10
Years
Max Storage Temperature
20
Years
Max Operating Temperature
N
Max Reprogramming Cycles
100
Cycles
Normal Programming Conditions
V
CC
ESD
Protection
1 k
Input
V
CC
100 k
Preload
Circuitry
Feedback
Input
I/O
V
CC
V
CC
100 k
1 k
20420B-15
22
MACH111-5/7/10/12/15
POWER-UP RESET
The MACH devices have been designed with the capability to reset during system power-up.
Following power-up, all flip-flops will be reset to LOW. The output state will depend on the logic
polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying
state machine initialization. A timing diagram and parameter table are shown below. Due to the
synchronous operation of the power-up reset and the wide range of ways V
CC
can rise to its steady
state, two conditions are required to insure a valid power-up reset. These conditions are:
1. The V
CC
rise must be monotonic.
2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
Parameter Symbol
Parameter Descriptions
Max
Unit
t
PR
Power-Up Reset Time
10
s
t
S
Input or Feedback Setup Time
See Switching Characteristics
t
WL
Clock Width LOW
20420B-16
Power-Up Reset Waveform
t
PR
t
WL
t
S
4 V
V
CC
Power
Registered
Output
Clock
MACH111-5/7/10/12/15
23
DEVELOPMENT SYSTEMS (subject to change)
For more information on the products listed below, please consult the local Vantis sales office.
MANUFACTURER
SOFTWARE DEVELOPMENT SYSTEMS
Vantis Corporation
P.O. Box 3755
920 DeGuigne Drive
Sunnyvale, CA 94088
(408) 732-0555 or 1(888) 826-8472 (VANTIS2)
http://www.vantis.com
MACHXL Software
Vantis-ABEL Software
Vantis-Synario Software
Aldec, Inc.
3 Sunset Way, Suite F
Henderson, NV 89014
(702) 456-1222 or (800) 487-8743
ACTIVE-CAD
Cadence Design Systems
555 River Oaks Pkwy
San Jose, CA 95134
(408) 943-1234 or (800) 746-6223
PIC Designer
Concept/Composer
Synergy
Leapfrog/Verilog-XL
Exemplar Logic, Inc.
815 Atlantic Avenue, Suite 105
Alameda, CA 94501
(510) 337-3700
LeonardoTM
GalileoTM
Logic Modeling
19500 NW Gibbs Dr.
P.O. Box 310
Beaverton, OR 97075
(800) 346-6335
SmartModel
Library
Mentor Graphics Corp.
8005 S.W. Boeckman Rd.
Wilsonville, OR 97070-7777
(800) 547-3000 or (503) 685-7000
Design Architect, PLDSynthesisTM II
Autologic II Synthesizer, QuickSim Simulator, QuickHDL Simulator
MicroSim Corp.
20 Fairbanks
Irvine, CA 92718
(714) 770-3022
MicroSim Design Lab
PLogic, PLSyn
MINC Inc.
6755 Earl Drive, Suite 200
Colorado Springs, CO 80918
(800) 755-FPGA or (719) 590-1155
PLDesigner-XLTM Software
Model Technology
8905 S.W. Nimbus Avenue, Suite 150
Beaverton, OR 97008
(503) 641-1340
V-System/VHDL
OrCAD, Inc.
9300 S.W. Nimbus Avenue
Beaverton, OR 97008
(503) 671-9500 or (800) 671-9505
OrCAD Express
Synario
Design Automation
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
(800) 332-8246 or (206) 881-6444
ABELTM
SynarioTM Software
24
MACH111-5/7/10/12/15
Vantis is not responsible for any information relating to the products of third parties. The inclusion of such information is not a
representation nor an endorsement by Vantis of these products.
Synopsys
700 E. Middlefield Rd.
Mountain View, CA 94040
(415) 962-5000 or (800) 388-9125
FPGA or Design Compiler
(Requires MINC PLDesigner-XLTM)
VSS Simulator
Synplicity, Inc.
624 East Evelyn Ave.
Sunnyvale, CA 94086
(408) 617-6000
Synplify
Teradyne EDA
321 Harrison Ave.
Boston, MA 02118
(800) 777-2432 or (617) 422-2793
MultiSIM Interactive Simulator
LASAR
VeriBest, Inc.
6101 Lookout Road, Suite A
Boulder, CO 80301
(800) 837-4237
VeriBest PLD
Viewlogic Systems, Inc.
293 Boston Post Road West
Marlboro, MA 01752
(800) 873-8439 or (508) 480-0881
Viewdraw, ViewPLD, Viewsynthesis
Speedwave Simulator, ViewSim Simulator, VCS Simulator
MANUFACTURER
TEST GENERATION SYSTEM
Acugen Software, Inc.
427-3 Amherst St., Suite 391
Nashua, NH 03063
(603) 881-8821
ATGENTM Test Generation Software
iNt GmbH
Busenstrasse 6
D-8033 Martinsried, Munich, Germany
(87) 857-6667
PLDCheck 90
MANUFACTURER
SOFTWARE DEVELOPMENT SYSTEMS
MACH111-5/7/10/12/15
25
APPROVED PROGRAMMERS (SUBJECT TO CHANGE)
For more information on the products listed below, please consult the local Vantis sales office.
MANUFACTURER
PROGRAMMER CONFIGURATION
Advin Systems, Inc.
1050-L East Duane Ave.
Sunnyvale, CA 940 86
(408) 243-7000 or (800) 627-2456
BBS (408) 737-9200
Fax (408) 736-2503
Pilot-U40
Pilot-U84
MVP
BP Microsystems
1000 N. Post Oak Rd., Suite 225
Houston, TX 77055-7237
(800) 225-2102 or (713) 688-4600
BBS (713) 688-9283
Fax (713) 688-0920
BP1200
BP1400
BP2100
BP2200
Data I/O Corporation
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
(800) 426-1045 or (206) 881-6444
BBS (206) 882-3211
Fax (206) 882-1043
UniSiteTM
Model 2900
Model 3900
AutoSite
Hi-Lo Systems
4F, No. 2, Sec. 5, Ming Shoh E. Road
Taipei, Taiwan
(886) 2-764-0215
Fax (886) 2-756-6403
or
Tribal Microsystems / Hi-Lo Systems
44388 South Grimmer Blvd.
Fremont, CA 94538
(510) 623-8859
BBS (510) 623-0430
Fax (510) 623-9925
ALL-07
FLEX-700
SMS GmbH
Im Grund 15
88239 Wangen
Germany
(49) 7522-97280
Fax (49) 7522-972850
or
SMS USA
544 Weddell Dr. Suite 12
Sunnyvale, CA 94089
(408) 542-0388
Sprint Expert
Sprint Optima
Multisite
Stag House
Silver Court Watchmead, Welwyn Garden City
Herfordshire UK AL7 1LT
44-1-707-332148
Fax 44-1-707-371503
Stag Quazar
26
MACH111-5/7/10/12/15
APPROVED ADAPTER MANUFACTURERS
APPROVED ON-BOARD ISP PROGRAMMING TOOLS
System General
1603A South Main Street
Milpitas, CA 95035
(408) 263-6667
BBS (408) 262-6438
Fax (408) 262-9220
or
3F, No. 1, Alley 8, Lane 45
Bao Shing Road, Shin Diau
Taipei, Taiwan
(886) 2-917-3005
Fax (886) 2-911-1283
Turpro-1
Turpro-1/FX
Turpro-1/TX
MANUFACTURER
PROGRAMMER CONFIGURATION
California Integration Coordinators, Inc.
656 Main Street
Placerville, CA 95667
(916) 626-6168
Fax (916) 626-7740
MACH/PAL Programming Adapters
Emulation Technology, Inc.
2344 Walsh Ave., Bldg. F
Santa Clara, CA 95051
(408) 982-0660
Fax (408) 982-0664
Adapt-A-Socket
Programming Adapters
MANUFACTURER
PROGRAMMER CONFIGURATION
Corelis, Inc.
12607 Hidden Creek Way, Suite H
Cerritos, California 70703
(310) 926-6727
JTAGPROGTM
Vantis Corporation
P.O. Box 3755
920 DeGuigne Drive
Sunnyvale, CA 94088
(408) 732-0555 or 1(888) 826-8472 (VANTIS2)
http://www.vantis.com
MACHPRO
MANUFACTURER
PROGRAMMER CONFIGURATION
MACH111-5/7/10/12/15
27
PHYSICAL DIMENSIONS
PL 044
44-Pin Plastic Leaded Chip Carrier (measured in inches)
TOP VIEW
SEATING PLANE
.685
.695
.650
.656
Pin 1 I.D.
.685
.695
.650
.656
.026
.032
.050 REF
.042
.056
.062
.083
.013
.021
.590
.630
.500
REF
.009
.015
.165
.180
.090
.120
16-038-SQ
PL 044
DA78
6-28-94 ae
SIDE VIEW
28
MACH111-5/7/10/12/15
PHYSICAL DIMENSIONS
PQT044
44-Pin Thin Quad Flat Pack (measured in millimeters)
Trademarks
Copyright
1998 Vantis Corporation. All rights reserved.
AMD is a registered trademark of Advanced Micro Devices, Inc.
Vantis, the Vantis logo and combinations thereof, SpeedLocking and Bus-Friendly are trademarks, and MACH, MACHXL, MACHPRO and PAL are
registered trademarks of Vantis Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
1.00 REF.
1.20 MAX
11
13
11
13
0.80 BSC
44
1
0.95
1.05
11.80
12.20
9.80
10.20
11.80
12.20
9.80
10.20
0.30
0.45
16-038-PQT-2
PQT 44
7-11-95 ae
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