AT76C001
CBIC
Programmable
FIR Filter
AT76C001
Features
4 Multiplier-Accumulators
40 Bits Accuracy
16 Bit Data and Coefficients
4-tap Filter With 27 MHz Sample Rate
Programmable to Give up to 256 Taps With Sampling
Reducing Proportionally to 421,875 kHz
Programmable Rounding and Truncation to 16 Bit
8 Bit Standard Microprocessor Interface
64-pin PQFP, 68-pin PGA68 or 68-pin LCC68 Packaging
Description
The AT76C001 Programmable Finite Impulse Response (FIR) Filter implements a
4th order FIR cell built around 4 multiplier-accumulators. It contains a dual-port
RAM and a RAM which are used to implement FIR filters of up to 256 taps. High or-
der filters are achieved by multiplexing the 4th order cell and accumulating the inter-
mediate results up to 40 bits, so that there is no loss of accuracy.
The maximum frequency of the AT76C001 is 27 MHz. For 4-tap FIR filter, the in-
coming sample rate can be as high as 27 MHz. For higher order FIR filters, the
sample rate can be as high as the circuit frequency divided by the 4th order cell mul-
tiplexing factor.
A programmable normalization block allows the choice of the 16 significant bits from
the 40 bit internal result which can be previously rounded by adding 0.5 LSB accord-
ing to the 16 significant bit locations. The AT76C001 has a microprocessor inter-
face which can be configured to be Intel or Motorola compatible.
Applications
Digital Filters (video, audio, etc.)
Correlation
Image Processing
Name
Pin Number
Type
Function
QFP64 Packaging LCC68 Packaging PGA68 Packaging
IN<15:0>
34-40, 42, 44-51
27-33, 35, 37-44
K10-11, J10-11, H10-
11, G10, F10, E10-11,
D10-11, C10-11, B11-10
I
Input sample
DIV
33
26
L10
I
Input sample valid. Active low
RST_X1
32
24
K9
I
Force input sample to 0. Useful for interpolation
implementation
OUT<15:0>
18-12, 10, 8-1
9-3, 1, 67-60
K1, J1-2, H1-2, G1-2,
F2, E2, D1-2, C1-2, B1-
2, A2
O
Output filtered sample
DOV
19
10
K2
O
Output filtered sample valid. Active low
DATA<7:0>
21-24, 26, 28-30
13-16, 18, 20-22
L3, K4, L4, K5-7, L7, K8
I/O
Microprocessor interface data bus. Used for accessing
internal registers and to write the coefficients of the filter
CS
52
46
B9
I
Chip select. Active low
DS/WR
53
47
A9
I
Microprocessor interface data strobe (Motorola mode) or
Write signal (Intel mode). Active low
RDWR/RD
54
48
B8
I
Microprocessor interface Read/Write signal (Motorola
mode) or Read signal (Intel mode). Active low
ADD<1:0>
63-64
57-58
A4, B3
I
Microprocessor interface address bus
RESET
31
23
L8
I
Circuit master reset. Active low
CLOCK
56
50
B7
I
Circuit clock (27 MHz max)
CLOCK_BIST 61
55
A5
I
For internal use. Connect to ground
TEST_BIST
20
12
K3
I
For internal use. Connect to ground
VCC
11, 27, 43, 58, 60,
62
2, 19, 36, 52, 54,
56
B4-6, F1, F11, L6
Power supply (+5V)
GND
9, 25, 41, 55, 57,
59
17, 34, 49, 51, 53
A6-8, E1, G11, L5
Ground
NC
11, 25, 45, 59
A3, A10, L2, L9
No connection
Pin Description
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CS
DS/WR
RDWR/RD
GND
CLOCK
GND
VCC
GND
VCC
CLOCK_BIST(0)
VCC
ADD1
ADD
0
RST-XI
RESET
DATA0
DATA1
DATA2
VCC
DATA3
GND
DATA4
DATA5
DATA6
DATA7
TEST_
BIST
(0)
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
VC
C
IN8
GN
D
IN9
IN10
IN11
IN12
IN
1
3
IN14
IN15
DIV
OU
T0
OU
T
1
OU
T2
OU
T3
OU
T4
OU
T5
OU
T
6
OU
T7
GN
D
OU
T8
VC
C
OU
T9
OU
T
1
0
OU
T1
1
OU
T1
2
OU
T1
3
OU
T1
4
OU
T1
5
DO
V
AT76C001
QFP64
(0): Connect to GND
Plan View of AT76C001 in QFP64 Package
2
AT76C001
28
29
30
31
32
33
34
35
36
37
38
39
40
8
7
6
5
4
3
2
1
68
67
66
65
64
45
46
47
48
49
50
51
52
53
54
55
56
57
5 8
59
60
25
24
23
22
21
20
19
18
17
16
15
14
13
1 2
11
10
IN14
IN 13
IN 12
IN 11
IN10
IN 9
G N D
IN 8
VCC
IN 7
IN 6
IN5
IN 4
OUT14
O U T 13
O U T 12
O U T 11
O U T 10
O U T 9
VC C
O U T 8
G N D
O U T 7
O U T 6
OU T5
O U T 4
NC*
RS
T
_
X
I
R
ESET
DA
T
A
0
DA
T
A
1
DA
T
A
2
VC
C
DA
T
A
3
GN
D
DA
T
A
4
DA
T
A
5
DA
T
A
6
DA
T
A
7
T
E
S
T
_B
IS
T
(
0)
NC*
DO
V
NC*
CS
DS
/
W
R
RDW
R/RD
GN
D
CLO
C
K
GN
D
VC
C
GN
D
VC
C
C
L
O
C
K_
BI
ST
(
0
)
VC
C
A
DD1
A
DD0
NC*
OU
T0
AT76C001
LCC 68
(0): Connect to GND
26
DIV
44
IN0
9
OUT15
27
IN15
41
42
43
IN3
IN2
IN1
63
62
61
OUT3
OUT2
OUT1
* No Connection
Plan view of AT76C001 in LCC68 package
L
NC*
DATA7 DATA5
GND
VCC
DATA1 RESET
NC*
OUT15
DOV
TC(0)
DATA6 DATA4 DATA3 DATA2 DATA0 RST_XI
OUT2
OUT1
ADD0
VCC
VCC
VCC
CLOCK
RDWR/
RD
CS
OUT0
NC*
ADD1
CB(0)
GND
GND
GND
DS/WR
DIV
IN15
IN14
OUT14 OUT13
OUT12 OUT11
OUT10
OUT9
VCC
OUT8
GND
OUT7
OUT6
OUT5
IN13
IN12
IN11
IN10
IN9
GND
IN8
VCC
IN7
IN6
IN5
IN4
IN0
IN1
NC*
OUT4
OUT3
IN3
IN2
1
2
3
4
5
6
7
8
9
10
11
K
J
H
G
F
E
D
C
B
A
AT76C001
PGA68
(0): Connect to GND
* No Connection
Plan view of AT76C001 in PGA68 package
AT76C001
3
Block Diagram
C ontrol
U nit
Coefficient
R A M
Sam ple
R A M
Fourth Order
FIR Cell
Regi
s
t
er
Regi
s
t
er
Regi
s
t
er
Regi
s
t
er
N
o
r
m
a
lis
a
t
io
n
M
u
lt
ip
le
x
e
r
ADD < 1 :0 >
C S
D S/ W R
R D W R /R D
R ST -XI
D I V
C L OC K
R E S E T
D AT A
< 7 :0 >
IN <15:0>
Internal
Control
Signals
D O V
OU T
<1 5:0>
Fourth Order FIR Cell
Mu x
Mul t
Register
Add
Register
Mu x
Mul t
Register
Add
Register
Mu x
Mul t
Register
Add
Register
Mu x
Mul t
Register
Add
Register
Fro m
IN<1 5 :0 >
Fro m
D A TA < 7 :0 >
Fro m
Control
U ni t
To Normalisation
4
AT76C001
Functional Description
The AT76C001 has an architecture built around a 4-tap
non-recursive filter cell. This allows a 4-tap filter to be im-
plemented, e.g.
y(n) = a(0)x(n) + a(1)x(n-1) + a(2)x(n-2) + a(3)x(n-3)
where x = 16 bit incoming sample
y = 16 bit filtered sample
a = 16 bit coefficient
This operating mode is called `single mode'.
The AT76C001 can implement up to 256-tap filters by
multiplexing the 4th order structure, using internal
RAMs. Nth order FIR filters can be divided into P 4th-or-
der FIR sub-filters where P is the integer part of (N+3)/4.
Thus the complete filter is evaluated by accumulating
the contributions of each elementary 4th order sub-filter:
y(n) = y(n,0) + y(n,1) + ....... + y(n,P-1)
where y(n,j) = a(4j)x(n-4j) + a(4j+1)x(n-4j-1)
+ a(4j+2)x(n-4j-2) + a(4j+3)x(n-4j-3)
j = number of the sub-filter
This operating mode is called `sequential mode'.
If (N+3)/4 is greater than P, then some coefficients of
the last sub-filter will be set to zero automatically by the
circuit.
In single mode, the incoming sample rate can be as high
as the circuit frequency (27 MHz). A new incoming sam-
ple is notified by a low level on DIV input signal and
clocked by the rising edge of the circuit clock CLOCK.
If there is a low level set on DIV and then a low level is
set on RST_XI input, then a `zero' sample is fed inter-
nally into the circuit.
For each new sample, a filtered sample is calculated.
Valid output filtered samples are notified by a low level
on DOV output signal. The timing diagram below illus-
trates the single mode operation.
In sequential mode, an N-tap filter is divided into P 4-tap
filters. Consequently, the incoming sample rate must be
at least P times slower than the circuit rate. As in single
mode, a new incoming sample is notified by a low level
on DIV input signal and clocked by the rising edge
CLOCK. But here, DIV defines a temporal window
where XIN is valid and whose width must be at least one
CLOCK period and at most P-1 clock periods. The tim-
ing diagrams below illustrate the case for an N-tap filter,
where N is greater than 4 but less than 9, i.e., DIV must
go to high level between two incoming signals.
CLOCK
DIV
RST_XI
IN
OUT
DOV
X0
X1
X2=0
X3=0
X4
X5
X6
X7=0
X8
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Output valid
Input valid
Input forced
to 0
Timing Diagram for Single Mode Operation
AT76C001
5
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