Features
Contactless Read/Write Data Transmission
Radio Frequency f
RF
:
100 kHz to 200 kHz
User Memory (1024 Bits): 32 Write Protectable 32-bit Blocks of Data
Deterministic Anticollision: Detection Rate ~ 20 Tags/s with 40-bit Tag ID, RF/32
On-chip CRC Generator:
16-bit CRC-CCITT Compliant to ISO/IEC 11785
Downlink Transmission:
Enhanced 1 out of 4 Pulse Interval Encoding (~ 5 kbps)
Uplink Transmission:
ASK Modulated, NRZ, Manchester or Bi-phase Encoding
Integrated Tuning Capacitor: 75 pF 10% as Mask Option
System Memory (320 bits):
10 Write and Password Protectable 32 Bit Blocks of Data
Tag ID (96 Bits Maximum)
Traceability Data with Inherent Manufacturer Serial Number
Write Password (32 Bits) and Read Password (32 Bits),
with Page Orientated Memory Protection Areas
Configuration Register for Setup of:
Selectable Data Bit Rate: RF/2 .. RF/64
Selectable Tag ID Length to Optimize Anticollision Detection Rate
Start of Frame with Variable Preamble Length to Simplify Interrogator Design
Public Mode (PM) for Read Only Tag Emulation
Electrical Article Surveillance (EAS) Mode
Direct Data (NRZ), Bi-phase (FDX-B) or Manchester Data Encoding
1.
General Description
The ATA5558 is a contactless, two-terminal R/W-Identification IC (IDIC
) for multi- or
single tag applications in the low frequency (
125 kHz) range. The passive tag uses
the external RF signal to generate it's own power supply and internal clock reference.
Figure 1-1.
RFID System Using an ATA5558 Tag
It contains an EEPROM which is subdivided into 1024 bits of user memory and
320 bits of system memory. Both memory sections are organized in data blocks of
32 bits, each equipped with an associated lock bit for block write protection. The user
memory, which is intended for storage of recallable user data, is made of 32 such
blocks. The 10 block system memory section is reserved for system parameter and
configuration settings. Two of these blocks include a 32 bit read and a 32 bit write
password to prevent unauthorized read and/or write access to protected user defin-
able memory pages.
Base station
Data
Power
Transponder
Reader or
Interrogator
ATA5558
* Mask option
*
Cont
roller
C
o
il
in
ter
f
ace
Memory
1 kbit R/W IDIC
with
Deterministic
Anticollision
ATA5558
Preliminary
Rev. 4681CRFID09/05
2
4681CRFID09/05
ATA5558 [Preliminary]
The ATA5558 receives commands from the interrogator (downlink) as a 1 out of 4 pulse interval
encoded, amplitude modulated signal. Return data transmission from the tag to the interrogator
(uplink) utilizes either Manchester, Bi-phase or NRZ encoded amplitude modulation. This is
achieved by controlled damping of the interrogator's RF field with an on-chip resistive load
between the two tag terminals, Coil 1 and Coil 2. Multi-Tag identification is implemented using a
deterministic anticollision algorithm which requires unique tag identification information (Tag
ID's). Three blocks within the system memory are reserved for storage of the Tag ID, the length
of which is user configurable up to a maximum of 96 bits.
Figure 1-2.
System Block Diagram
2.
Functional Blocks
2.1
Analog Front End
The analog front end (AFE) includes all circuitry directly associated with the coil interface. It gen-
erates the internal power supply and handles the data communication with the interrogator. It
consists of the following blocks:
Rectifier to generate a DC supply voltage from the AC coil voltage
Low-voltage regulator to provide an on-chip stabilized DC voltage
Charge pump to generate the high voltage required for EEPROM programming
On-chip tuning capacitor (mask option)
Field clock extractor
Field gap detector for data transmission from interrogator to tag
Load switching between Coil 1/Coil 2 for data transmission from tag to interrogator
Electrostatic discharge protection (ESD)
Ana
l
og fr
ont end
Binary bitrate
generator
PPM
s
i
gnal
decoder
System memory
User memory
(1kbit EEPROM)
Modulator
HV generator
Input register
*
Coil 1
Coil 2
* mask option
Mode register
Anticollision logic
Controller
POR
3
4681CRFID09/05
ATA5558 [Preliminary]
2.2
Power-On Reset (POR) and Initialization
The Power-On-Reset circuit (POR) maintains the circuit in a reset state until an adequate inter-
nal operating voltage threshold level has been reached, whereupon a default start-up delay
sequence is started. During this period of 200 field clock cycles, the configuration and security
setup is initialized from the System Configuration and Page Security blocks.
2.3
Control Logic
The control logic is responsible for the following functions:
Initialization and reloading of the configuration from EEPROM
Control of read and write memory access operations
Data transmission and command decoding
CRC check, error detection and error handling
2.4
Modulator
The modulator output circuitry controls the switching of a resistive load between the Coil 1 and
Coil 2 pads to transmit data from the tag to the interrogator (uplink). The ASK load modulator is
driven from the Manchester, Bi-phase encoder or directly from the EEPROM memory data
stream (NRZ) according to the uplink encoding configuration.
Figure 2-1.
Manchester Timing Diagram
Table 2-1.
Types of Modulation
Uplink Mode
Manchester Encoding
Bi-phase Encoding
(1)
NRZ Direct Data
ASK-coded
modulation
0 = falling edge on mid bit
1 = rising edge on mid bit
0 = rising or falling edge
1 = no edge on mid bit
1 = modulation off
0 = modulation on
Note:
1. Since Bi-phase encoding is data dependent the following definitions apply to the ATA5558
implementation.
- The tag modulates the first (half) bit period after SOF.
- If the last bit of a data stream is a logical 1 it is possible that this bit period is non-modu-
lated and therefore is not detectable directly by the reader.
1
Data rate = F
RF
/16
0
0
1
NRZ data stream
Manchester coded
RF field
Manchester
coded Modulator
signal
4
4681CRFID09/05
ATA5558 [Preliminary]
Figure 2-2.
Bi-phase Timing Diagram
2.5
Binary Bit Rate Generator
The tag's data rate is binary programmable in the configuration register to operate at any bit rate
between RF/2 and RF/64.
2.6
Memory Section
2.6.1
Memory Map
The physical memory is subdivided into two logical sections (see
Figure 2-3
). The first logical
memory section contains the 1024 bits of user data. The second logical memory section con-
tains 320 bits of system/configuration data. Both memories are organized in 32-bit data blocks,
each block being equipped with a single lock bit, with which the associated block can be write
protected. Command controlled programming and reading always takes place on a serial MSB
first block basis so that a block constitutes the smallest directly accessible data unit. The user
memory is further subdivided into 8 pages, each of 4 blocks in size. This provides the basis of
the page security scheme (
"Password Protection" on page 6
).
Figure 2-3.
Memory Map Structure
1
Data rate = F
RF
/8
0
NRZ data stream
Biphase coded
RF field
Bi-phase coded
Modulator signal
0
1
1
1
0
1
Data rate
RF
2 n
1
+
(
)
---------------------
=
31
:
4
3
2
1
0
30
29
7
6
5
28
27
31
36h
37h
3Eh
3Fh
3Dh
3Ch
3Bh
3Ah
39h
38h
1Eh
1Fh
1Dh
1Ch
00h
01h
03h
02h
1Bh
04h
05h
06h
07h
L
L
L
L
L
L
L
L
Configuration
Password/Page Security
Traceability 3
Traceability 2
Traceability 1
Tag ID 3
Tag ID 2
Tag ID 1
System memory
User memory
L
62
63
61
60
59
58
57
56
55
54
L
Password - Write
Password - Read
31 30 29
0
1
2
30 29
0
1
2
31
bit position
bit position
User data block0/page0
User data block1/page0
User data block2/page0
User data block3/page0
User data block4/page1
User data block5/page1
User data block6/page1
User data block7/page1
User data block31/page7
User data block30/page7
User data block29/page7
:
L
L
L
L
L
L
:
L
L
L
L
L
User data block28/page7
User data block27/page6
L
L
L
L
Lock bits
5
4681CRFID09/05
ATA5558 [Preliminary]
A valid Write command can be used for programming a data block of 33 bits including the
associated lock bit into an addressed location of either memory section. Once locked
(lock bit = 1), the entire block including the lock bit itself can no longer be reprogrammed
selectively.
The system memory section is situated at the upper end of the (6-bit) memory address range
and contains all system parameters and configuration settings. This area has restricted access
(see
Figure 2-5 on page 7
) and the majority of blocks can only be read or written after the suc-
cessful execution of the appropriate Password Login command (see
Table 7-1 on page 24
).
All the configuration settings are allocated in block 63 (see
Figure 2-7 on page 9
) and the pass-
word protection security information in block 62 (see
Figure 2-6 on page 7
).
2.6.2
Traceability Data
The traceability information is programmed and locked into the traceability blocks (59-61) by
Atmel during the production test.
Figure 2-4.
Tag ID and Traceability Structure
IC code
4-digit Atmel IC reference number, e.g. '5558'
ACL
Allocation class as defined in ISO/IEC TDR 15963-1 = E0h
MFC
Manufacturer code of Atmel Corp. as defined in ISO/IEC 7816-6/AM1 = 15h
ICR
4-bit Atmel IC revision code
DPW
18-bit binary encoded die on wafer
Wafer#
5-bit binary wafer number
Lot ID
9-digit lot number
RFU
Reserved for Future Use
7 ............. 0
15 ......... 8
31 ................................. 16
7... 4
30 .............. 26
3 ... 0
25 ........................ 8
15 ..................... 0
31 ................... 16
TagID
TagID(msb)...........TagID(msb-16)
TagID(msb-17)........TagID(msb-31)
Block 57
Block 56
Anticollison detection starts with this bit
Block 58
Traceability
MFC
ICR
Block 60
Block 59
ACL
LotID
die on wafer 18 bit
wafer # 5bit
TagID(msb-49)........TagID(msb-63)
TagID(msb-32).......TagID(msb-48)
TagID(msb-80)........TagID(msb-95)
TagID(msb-64).......TagID(msb-79)
IC code
RF
U
Block 61
LotID
31
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