ChipFind - документация

Электронный компонент: ATA5823

Скачать:  PDF   ZIP

Document Outline

Features
Full-duplex Operation Mode without Duplex Frequency Offset to Prevent the Relay
Attack against Passive Entry Go (PEG) Systems
High FSK Sensitivity: 105.5 dBm at 20 kBaud/109 dBm at 2.4 kBaud (433.92 MHz)
High ASK Sensitivity: 111.5 dBm at 10 kBaud/116 dBm at 2.4 kBaud (100% ASK,
Carrier Level 433.92 MHz)
Low Supply Current: 10.5 mA in RX and TX Mode (3V/TX with 5 dBm/433.92 MHz)
Data Rate 1 to 20 kBaud Manchester FSK, 1 to 10 kBaud Manchester
ASK
ASK/FSK Receiver Uses a Low IF Architecture with High Selectivity,
Blocking and Low Intermodulation (Typical 3 dB Blocking
55.5 dBC at 750 kHz/60.5 dBC at 1.5 MHz and 67 dBC at 10 MHz,
System I1dBCP = 30 dBm/System IIP3 = 20 dBm)
Wide Bandwidth AGC to Handle Large Outband Blockers above the System I1dBCP
226 kHz IF (Intermediate Frequency) with 30 dB Image Rejection and 220 kHz System
Bandwidth to Support TPM Transmitters using ATA5756/ATA5757 Transmitters with
Standard Crystals
Transmitter Uses Closed Loop FSK Modulation with Fractional-N Synthesizer with
High PLL Bandwidth and an Excellent Isolation between PLL and PA
Tolerances of XTAL Compensated by Fractional-N Synthesizer with 800 Hz RF
Resolution
Integrated RX/TX-Switch, Single-ended RF Input and Output
RSSI (Received Signal Strength Indicator)
Communication to Microcontroller with SPI Interface Working at 500 kBit/s Maximum
Configurable Self Polling and RX/TX Protocol Handling with FIFO-RAM Buffering of
Received and Transmitted Data
1 Push Button Input and 1 Wake-up Input are Active in Power-down Mode
Integrated XTAL Capacitors
PA Efficiency: up to 38% (433.92 MHz/10 dBm/3V)
Low In-band Sensitivity Change of Typically 2.0 dB within 75 kHz Center Frequency
Change in the Complete Temperature and Supply Voltage Range
Fully Integrated PLL with Low Phase Noise VCO, PLL Loop Filter and full support of
multi-channel operation with arbitrary Channel distance due to Fractional-N
Synthesizer
Sophisticated Threshold Control and Quasi-peak Detector Circuit in the Data Slicer
433.92 MHz, 868.3 MHz and 315 MHz without External VCO and PLL Components
Efficient XTO Start-up Circuit (> 1.5 k
Worst Case Start Impedance)
Changing of Modulation Type ASK/FSK and Data Rate without Component Changes to
Allow Different Modulation Schemes in TPM and RKE
Minimal External Circuitry Requirements for Complete System Solution
Adjustable Output Power: 0 to 10 dBm Adjusted and Stabilized with External Resistor,
Programmable Output Power with 0.5dB Steps with Internal Resistor
Clock and Interrupt Generation for Microcontroller
ESD Protection at all Pins (2.5 kV HBM, 200V MM, 500V FCDM)
Supply Voltage Range: 2.15V to 3.6V or 4.4V to 5.25V
Typical Power-down Current < 10 nA
Temperature Range: 40C to +105C
Small 7 mm
7 mm QFN48 Package
UHF ASK/FSK
Transceiver
ATA5823
ATA5824
Rev. 4829CRKE09/05
2
4829CRKE09/05
ATA5823/ATA5824
Applications
Automotive Keyless Entry and Passive Entry Go (Handsfree Car Access)
Tire Pressure Monitoring Systems
Remote Control Systems
Alarm and Telemetering Systems
Energy Metering
Home Automation
Benefits
No SAW Device Needed in Key Fob Designs to Meet Automotive Specifications
Low System Cost Due to Very High System Integration Level
Only One Crystal Needed in System
Less Demanding Specification for the Microcontroller Due to Handling of Power-down Mode,
Delivering of Clock and Complete Handling of Receive/Transmit Protocol and Polling
Single-ended Design with High Isolation of PLL/VCO from PA and the Power Supply Allows a
Loop Antenna in the Key Fob to Surround the Whole Application
Prevention against Relay Attack with Full-duplex Operation Mode
Integration of Tire Pressure Monitoring, Passive Entry and Remote Keyless Entry
1.
General Description
The ATA5823/ATA5824 is a highly integrated UHF ASK/FSK multi-channel half-duplex and
full-duplex transceiver with low power consumption supplied in a small
7 mm
7 mm
QFN48
package. The receive part is built as a fully integrated low-IF receiver, whereas direct PLL mod-
ulation with the fractional-N synthesizer is used for FSK transmission and switching of the power
amplifier for ASK transmission. The additional full-duplex mode makes relay attacks much more
difficult, since the attacker has to receive and transmit signals on the same frequency at the
same time.
The device supports data rates of 1 kBaud to 20 kBaud (FSK) and 1 kBaud to 10 kBaud (ASK)
in Manchester, Bi-phase and other codes in transparent mode. The ATA5824 can be used in the
433 MHz to 435 MHz band and the 867 MHz to 870 MHz band, the ATA5823 in the 313 MHz to
316 MHz band. The very high system integration level results in few numbers of external compo-
nents needed.
Due to its blocking and selectivity performance, together with a typical narrow-band key-fob loop
antenna with 15 dB to 20 dB loss, a bulky blocking SAW is not needed in the key fob application.
Additionally, the building blocks needed for a typical RKE and access control system on both
sides, the base and the mobile stations, are fully integrated.
Its digital control logic with self polling and protocol generation provides a fast challenge
response system without using a high-performance microcontroller. Therefore, the
ATA5823/ATA5824 contains a FIFO buffer RAM and can compose and receive the physical
messages themselves. This provides more time for the microcontroller to carry out other func-
tions such as calculating crypto algorithms, composing the logical messages and controlling
other devices. Due to that, a standard 4-/8-bit microcontroller without special periphery and
clocked with the delivered CLK output of about 4.5 MHz is sufficient to control the communica-
tion link. This is especially valid for passive entry go and access control systems, where within
less than 100 ms several communication responses with arbitration of the communication part-
ner have to be handled. It is hence possible to design bi-directional RKE and passive entry go
systems with a fast challenge response crypto function and prevention against relay attacks.
3
4829CRKE09/05
ATA5823/ATA5824
Figure 1-1.
System Block Diagram
2.
Pin Configuration
Figure 2-1.
Pinning QFN48
RF Transceiver
Digital Control
Logic
C_Interface
Power
Supply
XTO
Micro-
controller
ATA5823/ATA5824
Antenna
4 ... 8
Matching/
RF Switch
NC
NC
NC
RF_IN
NC
433_N868
NC
R_PWR
PWR_H
RF_OUT
NC
NC
RSSI
CS
TEST3
SCK
SDI_TMDI
SDO_TMDO
CLK
IRQ
POUT
VSINT
NC
XTAL2
NC
NC
RX
_A
C
T
I
V
E
N_P
W
R_ON
SC
K_
P
H
A
SC
K_
P
O
L
NC
NC
PW
R
_
O
N
RX
_T
X1
RX
_T
X2
CDE
M
NC
NC
NC
AVC
C
VS
2
VS
1
SETPW
R
TEST
1
DV
C
C
CS
_P
OL
TEST
2
XTAL
1
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
ATA5823/ATA5824
4
4829CRKE09/05
ATA5823/ATA5824
Table 2-1.
Pin Description
Pin
Symbol
Function
1
NC
Not connected
2
NC
Not connected
3
NC
Not connected
4
RF_IN
RF input
5
NC
Not connected
6
433_N868
Selects RF input/output frequency range
7
NC
Not connected
8
R_PWR
Resistor to adjust output power
9
PWR_H
Pin to select output power
10
RF_OUT
RF output
11
NC
Not connected
12
NC
Not connected
13
NC
Not connected
14
NC
Not connected
15
NC
Not connected
16
AVCC
Blocking of the analog voltage supply
17
VS2
Power supply input for voltage range 4.4V to 5.6V
18
VS1
Power supply input for voltage range 2.15V to 3.6V
19
SETPWR
Internal Programmable Resistor to adjust output power
20
TEST1
Test input, at GND during operation
21
DVCC
Blocking of the digital voltage supply
22
CS_POL
Select polarity of pin CS
23
TEST2
Test input, at GND during operation
24
XTAL1
Reference crystal
25
XTAL2
Reference crystal
26
NC
Not connected
27
VSINT
Microcontroller interface supply voltage
28
POUT
Programmable output
29
IRQ
Interrupt request
30
CLK
Clock output to connect a microcontroller
31
SDO_TMDO
Serial data out/transparent mode data out
32
SDI_TMDI
Serial data in/transparent mode data in
33
SCK
Serial clock
34
TEST3
Test output open during operation
35
CS
Chip select for serial interface
36
RSSI
Output of the RSSI amplifier
37
CDEM
Capacitor to adjust the lower cut-off frequency data filter
38
RX_TX2
Has to be connected GND
39
RX_TX1
Switch pin to decouple LNA in TX mode (RKE mode)
40
PWR_ON
Input to switch on the system (active high)
41
NC
Not connected
5
4829CRKE09/05
ATA5823/ATA5824
Figure 2-2.
Block Diagram
42
NC
Not connected
43
SCK_POL
Polarity of the serial clock
44
SCK_PHA
Phase of the serial clock
45
N_PWR_ON
Keyboard input (can also be used to switch on the system, active low)
46
RX_ACTIVE
Indicates RX operation mode
47
NC
Not connected
48
NC
Not connected
GND
Ground/Backplane (exposed die pad)
Table 2-1.
Pin Description (Continued)
Pin
Symbol
Function
R_PWR
RF_OUT
RX_TX2
RF_IN
AV
C
C
GN
D
Signal
processing
(Mixer
IF-filter
IF-amplifier
FSK/ASK
demodulator
Data filter
Data slicer)
RF transceiver
Digital control logic
DV
CC
PA_Enable (ASK)
RX/TX
Frontend Enable
Demod_Out
XTAL1
XTAL2
CLK
POUT
CS
SCK
SDI_TMDI
SDO_TMDO
VS2
VS1
N_PWR_ON
PWR_ON
CDEM
SETPWR
RX_TX1
PWR_H
RSSI
IRQ
TEST3
C_Interface
VS
I
N
T
PA
Fract.-N-
Frequency
Synthesizer
LNA
SPI
XTO
FREF
TX/RX -
Data buffer
Control register
Status register
Polling circuit
Bit-check logic
Synchronous logic
(Full duplex
operation mode)
RX
_
A
CTI
V
E
TEST1
TEST2
FREQ
13
TX_DATA (FSK)
Power
Supply
Switches
Regulators
Wake-up
Reset
Reset
RX/TX
switch
CS_POL
SCK_POL
SCK_PHA
433_N868