2137CHIREL03/04

Features

Processor Bus Frequency up to 100 MHz

64- or 32-bit Data Bus and 32-bit Address Bus

Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst
SRAM

Compliant with PCI Specification, Revision 2.1

PCI Interface Operates up to 66 MHz/5.0V Compatible

IEEE 1149.1 Compliant, JTAG Boundary-scan Interface

PD Max = 1W (66 MHz), Full Operating Conditions

Nap, Doze and Sleep Modes for Power Savings

Two-channel Integrated DMA Controller

Message Unit

Intelligent Input/Output (Two-wire Interface) Message Controller
Two Door Bell Registers
Inbound and Outbound Messaging Registers

Inter-integrated Circuit (Two-wire Interface) Controller, Full Master/Slave Support

Embedded Programmable Interrupt Controller (EPIC)

Five Hardware Interrupts (IRQs) or 16 Serial Interrupts
Four Programmable Timers

Description

The PC107A PCI Bridge/Integrated Memory Controller provides a bridge between the
Peripheral Component Interconnect, (PCI) bus and PowerPC 603e

, PowerPC 740

PowerPC 750

or PC7400 microprocessors.

PCI support allows system designers to design systems quickly using peripherals
already designed for PCI and other standard interfaces available in the personal com-
puter hardware environment. The PC107A provides many other necessities for
embedded applications including a high-performance memory controller and dual pro-
cessor support, 2-channel flexible DMA controller, an interrupt controller, an I

O-ready

message unit, an inter-integrated circuit controller (

Two-wire Interface

), and low skew

clock drivers. The PC107A contains an Embedded Programmable Interrupt Controller
(EPIC) featuring five hardware interrupts (IRQ's) as well as sixteen serial interrupts
along with four timers. The PC107A uses an advanced, 2.5V HiP3 process technology
and is fully compatible with TTL devices.

Screening

This product is manufactured in full compliance with:

PBGA upscreenings based upon Atmel standards

Full military temperature range (Tj = -55

C, +125

Industrial temperature range (Tj = -40

C, +110

HiTCE (TBC)

PBGA 503

Flip-chip Plastic Ball Grid Array

GH suffix

HITCE 503

Ceramic Ball Grid Array

PCI Bridge
Memory
Controller

PC107A

Preliminary
Specification

-site

Rev. 2137CHIREL03/04

PC107A [Preliminary]

2137CHIREL03/04

General Description

Simplified Block Diagram

The PC107A integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt
controller/timers, a message unit with an Intelligent Input/Output (I

O) message control-

ler, and an Inter-integrated Circuit (two-wire interface) controller. The integration
reduces the overall packaging requirements and the number of discrete devices
required for an embedded system.

Figure 1 shows the major functional units within the PC107A. Note that this is a concep-
tual block diagram intended to show the basic features rather than an attempt to show
how these features are physically implemented.

Figure 1. PC107A Block Diagram

Data (64-Bit)

60x Bus Interface (64- or 32-Bit Data Bus)

Address

(32-Bit)

DLL

PLL

Fanout

Buffers

Additional features:
· Programmable I/O
· with Watchpoint
· JTAG/COP Interface
· Power Management

SDRAM_SYNC_IN

SDRAM Clocks
CPU Clocks

PCI_SYNC_IN

PCI Bus Clocks

Memory/ROM/
Port X Control/

Address

Data Bus
(64- or 32-bit)
with 8-bit Parity
or ECC

OSC_IN

Five
Request/Grant
Pairs

32-Bit

PCI Interface

I2C

5 IRQs/

16 Serial

Interrupts

EPIC

Interrupt

Controller

/Timers

Address

Translator

PCI

Arbiter

MPC107

I2C

Controller

DMA

Controller

Message

Unit

(with I2O)

Peripheral Logic Block

Central
Control

Unit

Data Path

ECC Controller

Memory

Controller

Configuration

Registers

PCI Bus

Interface Unit

PC107A [Preliminary]

2137CHIREL03/04

General Parameters

The following list provides a summary of the general parameters of the PC107A:

Technology

0.29 µm CMOS, five-layer metal

Die size

50 mm

Transistor count

0.96 million

Logic design

Fully-static

Package

Surface mount 503 Plastic Ball Grid Array (C4/PBGA)

Core power supply

2.5 ±5% V DC (nominal; see Table 3 on page 12 for
recommended operating conditions)

I/O power supply

3.0 to 3.6V DC

Features

The PC107A provides an integrated high-bandwidth, high-performance interface
between up to two 60x processors, the PCI bus, and main memory. This section sum-
marizes the features of the PC107A. Major features of the PC107A are as follows:

Memory Interface

64-/32-bit 100 MHz bus

Programmable timing supporting either FPM DRAM, EDO DRAM or SDRAM

High-bandwidth bus (32-/64-bit data bus) to DRAM

Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices,
and up to four banks of 256 Mbit SDRAM devices

Supports 1M byte to 1 Gbyte DRAM memory

144M bytes of ROM space

8-, 32-, or 64-bit ROM

Write buffering for PCI and processor accesses

Supports normal parity, read-modify-write (RMW), or ECC

Data-path buffering between memory interface and processor

Low-voltage TTL logic (LVTTL) interfaces

Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller
interface with programmable address strobe timing

32-bit PCI Interface Operating up to 66 MHz

PCI 2.1-compliant

PCI 5.0V tolerance

Support for PCI locked accesses to memory

Support for accesses to PCI memory, I/O, and configuration spaces

Selectable big- or little-endian operation

Store gathering of processor-to-PCI write and PCI-to-memory write
accesses

Memory prefetching of PCI read accesses

Selectable hardware-enforced coherency

PCI bus arbitration unit (five request/grant pairs)

PCI agent mode capability

Address translation unit

Some internal configuration registers accessible from PCI

Two-channel Integrated DMA Controller (Writes to ROM/Port

Not Supported)

PC107A [Preliminary]

2137CHIREL03/04

Supports direct mode or chaining mode (automatic linking of DMA transfers)

Supports scatter gathering-read or write discontinuous memory

Interrupt on completed segment, chain, and error

Local-to-local memory

PCI-to-PCI memory

PCI-to-local memory

PCI memory-to-local memory

Message Unit

Two doorbell registers

An extended doorbell register mechanism that facilitates interprocessor
communication through interrupts in a dual-local-processor system

Two inbound and two outbound messaging registers

O message controller

Two-wire Interface Controller with Full Master/Slave Support (Except Broadcast All)

Embedded Programmable Interrupt Controller (EPIC)

Five hardware interrupts (IRQs) or 16 serial interrupts

Four programmable timers

Integrated PCI Bus, CPU, and SDRAM Clock Generation

Programmable PCI Bus, 60x, and Memory Interface Output Drivers

Dynamic Power Management Supports 60x Nap, Doze, and Sleep Modes

Programmable Input and Output Signals with Watchpoint Capability

Built-in PCI Bus Performance Monitor Facility

Debug Features

Error injection/capture on data path

IEEE 1149.1 (JTAG)/test interface

Processor Interface

Supports up to two PowerPC

microprocessors with 60x bus interface

Supports various operating frequencies and bus divider ratios

32-bit address bus, 64/32-bit data bus supported at 100 MHz

Supports full memory coherency

Supports optional local bus slave

Decoupled address and data buses for pipelining of 60x accesses

Store gathering on 60x-to-PCI writes

Concurrent transactions on 60x and PCI buses supported

PC107A [Preliminary]

2137CHIREL03/04

Pin Assignments

Pinout Listings

Table 1 provides the pinout listing for the PC107A, 503 PBGA package.

Table 1. PC107A Pinout Listing

Signal Name

Package Pin Number

Pin Type

Supply
Voltage

Output Driver Type

Notes

60x Processor Interface Signals

A[031]

AE22, AE16, AA14, AE17, AD21,
AD14, AD20, AB16, AB20, AB15,
AA20, AD13, Y15, AE12, AD15, AB9,
AB14, AA8, AC13, Y12, Y11, AE15,
AE13, AA16, Y13, AB8, AD12, AE10,
AB13, Y9, Y8, AD9

I/O

DRV_CPU

(4)

AACK

AC7

Output

DRV_CPU

ARTRY

I/O

DRV_CPU

(15)

BG0

AE11

Output

DRV_CPU

BG1

AD11

Output

DRV_CPU

BR0

AB17

Input

BR1

Y14

Input

(10)

AD16

I/O

DRV_CPU

DBG0

AC10

Output

DRV_MEM_ADDR

DBG1

AD10

Output

DRV_MEM_ADDR

DBGLB

AB10

Output

DRV_MEM_ADDR

DH[031]

P1, R1, P2, T4, T1, T3, R4, P6, U6,
V5, V2, T5, U1, R6, W1, V4, W2, U4,
T2, V6, W3, W5, Y1, Y2, Y4, Y5, AA1,
AA2, AA4, AB1, AB3, AB4

I/O

DRV_CPU

(4)

DL[031]

AA7, W6, AB6, AA6, AB5, AC4, AD3,
AB7, AE1, W4, N6, M1, N3, N4, N5,
N1, M2, R2, V1, P5, P4, N2, U2, AE4,
AE6, AE2, AE3, AE7, AD5, AB2, AC2,
AC1

I/O

DRV_CPU

(4)

DP[07]

AE9, AD6, AD8, AD1, AE8, AD7, AD4,
AE5

I/O

DRV_CPU

(4)

GBL

AD17

I/O

DRV_CPU

LBCLAIM

Y17

Input

AE14

I/O

DRV_CPU

(15)

TBST

AE21

I/O

DRV_CPU

TEA

AB11

Output

DRV_CPU

AA10

I/O

DRV_CPU

(15)

TSIZ[02]

AE19, AD18, AB18

I/O

DRV_CPU

(4)

TT[04]

AD19, AC19, AB19, AA19, AA18

I/O

DRV_CPU

(4)

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