2141DHIREL02/04
Features
22.8 SPECint95 (estimated), 17SPECfp95 at 500 MHz (estimated)
917MIPS at 500 MHz
Selectable Bus Clock (14 CPU Bus Dividers Up To 9x)
Seven Selectable Core-to-L2 Frequency Divisors
Selectable 603 Interface Voltage Below 3.3V (1.8V, 2.5V)
Selectable L2 interface of 1.8V or 2.5V
P
D
Typical 5.3W at 500 MHz, Full Operating Conditions
Nap, Doze and Sleep Modes for Power Saving
Superscalar (Four Instructions fetched per Clock Cycle)
4 GB Direct Addressing Range
Virtual Memory: 4 hexabytes (2
52
)
64-bit Data and 32-bit Address Bus Interface
32 KB Instruction and Data Cache
Eight Independent Execution Units and Three Register Files
Write-back and Write-through Operations
f
INT
Max = 450 MHz 500 MHz
f
BUS
Max = 133 MHz
Description
The PC7410 is the second microprocessor that uses the fourth (G4) full implementa-
tion of the PowerPC
TM
Reduced Instruction Set Computer (RISC) architecture. It is
fully JTAG-compliant.
The PC7410 maintains some of the characteristics of G3 microprocessors:
The design is superscalar, capable of issuing three instructions per clock cycle
into eight independent execution units
The microprocessor provides four software controllable power-saving modes and
a thermal assist unit management
The microprocessor has separate 32-Kbyte, physically-addressed instruction and
data caches with dedicated L2 cache interface with on-chip L2 tags
In addition, the PC7410 integrates full hardware-based multiprocessing capability,
including a 5-state cache coherency protocol (4 MESI states plus a fifth state for
shared intervention) and an implementation of the new AltiVec
TM
technology instruc-
tion set.
New features have been developed to make latency equal for double-precision and
single-precision floating-point operations involving multiplication. Additionally, in mem-
ory subsystem (MSS) bandwidth, the PC7410 offers an optional, high-bandwidth MPX
bus interface.
Unlike the PC7400, the PC7410 does not support the 3.3V I/O on the L2 cache
interface.
PowerPC 7410
RISC
Microprocessor
Product
Specification
PC7410
Rev. 2141DHIREL02/04
2
PC7410
2141DHIREL02/04
Screening
CBGA Upscreenings Based on Atmel Standards
Full Military Temperature Range (T
j
= -55
C, +125
C),
Industrial Temperature Range (T
j
= -40
C, +110
C)
CI-CGA Package Version, HiTCE Package Version
G suffix
CBGA 360
Ceramic Ball Grid Array
GH suffix
HITCE 360
Ceramic Ball Grid Array
CICGA 360
Ceramic Ball Grid Array
with Solder Column Interposer (SCI)
GS suffix
3
PC7410
21
41DHI
R
EL
02/
04
Block Diagram
Figur
e 1.
PC7410 Microprocesso
r Bloc
k
D
i
ag
ra
m
Fetcher
Branch Processing Unit
Instruction
Queue
6-word
Dispatch Unit
Instruction Unit
Data MMU
SRs
(Original)
128-entry
DTLB
DBAT
Array
Instruction MMU
SRs
(Shadow)
128-entry
ITLB
IBAT
Array
Reservation
Station
Vector
Permute
Unit
Vector
ALU
Integer
Unit 1
Integer
Unit 2
System
Register
Unit
Reservation
Station
Reservation
Station
Reservation
Station
Reservation
Station
Reservation
Station
2-entry
Reservation
Station
VR File
6 Rename
Buffers
GPR File
6 Rename
Buffers
FPR File
6 Rename
Buffers
Load/Store
Unit
Floating
Point Unit
Completion Unit
8-entry
Reorder Buffer
VSIU
VCIU VFPU
Tags
32-Kbyte
iCache
Tags
32-Kbyte
DCache
64-entry BTIC/512-entry BHT
LR/CTR
Add-Multiply-
divide
- Add -
VSCR
- Add -
Add-Multiply-
divide
FPSCR
EA Calculation
Finished Stores
Completed
Stores
128-bit
32-bit
128-bit
2 Instructions
32-bit
64-bit
(2 Instructions)
32-bit Address Bus
64- or 32-bit L2 Data Bus
19-bit L2 Address Bus
64-bit Data Bus
32-bit
EA
PA
64-bit
64-bit
Data Reload
Buffer
Data Reload
Table
Instruction
Reload Buffer
Instruction
Reload Table
Memory Subsystem
L2 Miss
Data
Transaction
Queue
L2 Castout
Bus Interface Unit
L2 Data
Transaction
Queue
L2 Controller
L2 Tags
L2CR
L2PMCR
Additional features
Time Base
Counter/Decrementer
Clock Multiplier
JTAG/COP Interface
Thermal/Power Management
Performance Monitor
128 bits
128 bits
(4 instructions)
4
PC7410
2141DHIREL02/04
General Parameters
Table 1 provides a summary of the general parameters of the PC7410.
Note:
1. 3.3V I/O bus not supported for 1.5V core power supply processor version.
Features
This section summarizes features of the PC7410's implementation of the PowerPC
architecture. Major features of the PC7410 are as follows:
Branch Processing Unit
Four instructions fetched per clock
One branch processed per cycle (plus resolving two speculations)
Up to one speculative stream in execution, one additional speculative stream
in fetch
512-entry branch history table (BHT) for dynamic prediction
64-entry, 4-way set associative branch target instruction cache (BTIC) for
eliminating branch delay slots
Dispatch Unit
Full hardware detection of dependencies (resolved in the execution units)
Dispatch two instructions to eight independent units (system, branch,
load/store, fixed-point unit 1, fixed-point unit 2, floating-point, AltiVec
permute, AltiVec ALU)
Serialization control (predispatch, postdispatch, execution serialization)
Decode
Register file access
Forwarding control
Partial instruction decode
Completion
8-entry completion buffer
Instruction tracking and peak completion of two instructions per cycle
Table 1. Device Parameters
Parameter
Description
Technology
0.18 m CMOS, six-layer metal
Die size
6.32 mm 8.26 mm (52 mm
2
)
Transistor count
10.5 million
Logic design
Fully-static
Packages
Surface-mount 360 ceramic ball grid array (CBGA)
Surface mount 360 high coefficient of thermal expansion
ceramic ball grid array (HiTCE)
Surface mount 360-column Ci-CGA Package
Core power supply
1.8V 100 mV dc or 1.5V 50 mV dc (nominal; see Table 4 for
Recommended Operating Conditions)
I/O power supply
1.8V 100 mV dc or
2.5V 100 mV
3.3V 165 mV (603 bus only)
(1)
(input thresholds are configuration pin selectable) or
5
PC7410
2141DHIREL02/04
Completion of instructions in program order while supporting out-of-order
instruction execution, completion serialization and all instruction flow
changes
Fixed-point Units (FXUs) that Share 32 GPRs for Integer Operands
Fixed-point unit 1 (FXU1)--multiply, divide, shift, rotate, arithmetic, logical
Fixed-point unit 2 (FXU2)--shift, rotate, arithmetic, logical
Single-cycle arithmetic, shifts, rotates, logical
Multiply and divide support (multi-cycle)
Early out multiply
Three-stage Floating-point Unit and a 32-entry FPR File
Support for IEEE-754 standard single- and double-precision floating-point
arithmetic
Three-cycle latency, one-cycle throughput (single or double precision)
Hardware support for divide
Hardware support for denormalized numbers
Time deterministic non-IEEE mode
System Unit
Executes CR logical instructions and miscellaneous system instructions
Special register transfer instructions
AltiVec Unit
Full 128-bit data paths
Two dispatchable units: vector permute unit and vector ALU unit
Contains its own 32-entry 128-bit vector register file (VRF) with six renames
The vector ALU unit is further sub-divided into the vector simple integer unit
(VSIU), the vector complex integer unit (VCIU) and the vector floating-point
unit (VFPU).
Fully pipelined
Load/Store Unit
One-cycle load or store cache access (byte, half-word, word, double-word)
Two-cycle load latency with one-cycle throughput
Effective address generation
Hits under misses (multiple outstanding misses)
Single-cycle unaligned access within double-word boundary
Alignment, zero padding, sign extend for integer register file
Floating-point internal format conversion (alignment, normalization)
Sequencing for load/store multiples and string operations
Store gathering
Executes the cache and TLB instructions
Big- and little-endian byte addressing supported
Misaligned little-endian supported
Supports FXU, FPU, and AltiVec load/store traffic
Complete support for all four architecture AltiVec DST streams
Level 1 (L1) Cache Structure
32K 32-byte line, 8-way set associative instruction cache (iL1)
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