1
Features
PC755M8 RISC Miprocessor
Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72
21 mm x 25 mm, 255 Ceramic Ball Grid Array (CBGA)
Maximum Core Frequency = 300 MHz
Maximum L2 Cache Frequency = 150 MHz
Maximum 60x Bus Frequency = 66 MHz
Description
The PC755M8 multichip package is targeted for high-performance, space-sensitive,
low-power systems and supports the following power management features: doze,
nap, sleep and dynamic power management.
The PC755M8 is offered in industrial and military temperature ranges and is well
suited for embedded applications.
Screening
This product is manufactured in full compliance with:
CBGA up screenings based on Atmel standards
Full military temperature range (T
j
= -55
C, +125
C)
industrial temperature range (T
j
= -40
C, +110
C)
SSRAM
SSRAM
PC755M8
RISC
Microprocessor
Multichip
Package
Preliminary
Specification
-site
PC755M8
Rev. 2164AHIREL01/03
2
PC755M8
2164AHIREL01/03
Block Diagram
Figure 1. PC755M8 Microprocessor Block Diagram
Additional Features
- Time Base Counter/Decrementer
- Clock Multiplier
- JTAG/COP Interface
- Thermal/Power Management
- Performance Monitor
+
+
F
etcher
Branc
h
Pr
ocessing
BTIC
64-entr
y
+ x
FPSCR
CR
FPSCR
L2CR
CTR
LR
BHT
Data MMU
Instruction MMU
Not in the PC745
EA
PA
+ x
Instruction Unit
Unit
Instr
uction Queue
(6-w
ord)
2 Instructions
Reser
v
ation Station
Reser
v
ation Station
Reser
v
ation Station
Integ
er Unit 1
System Register
Unit
Dispatch Unit
64-bit
(2 Instr
uctions)
SRs
ITLB
(Shado
w
)
IBA
T
Arr
a
y
32-Kb
yte
I Cache
Ta
g
s
128-bit
(4 Instr
uctions)
Reser
v
ation Station
32-bit
Floating-P
oint
Unit
Rename Buff
ers
(6)
FPR File
32-bit
6
4-bit
6
4-bit
Reservation Station
(2-entry)
Load/Store Unit
(EA Calculation)
Store Queue
GPR File
Rename Buff
ers
(6)
32-bit
SRs
(Or
i
ginal)
DTLB
DBA
T
Arr
a
y
64-bit
Completion Unit
Reorder Buff
er
(6-entr
y)
T
ags
32-Kb
yte
D Cache
60x Bus Interface Unit
Instr
uction F
etch Queue
L1 Cast out Queue
Data Load Queue
L2 Contr
oller
L2 T
a
gs
L2 Bus Interface
Unit
L2 Cast out Queue
32-bit Address Bus
32-/64-bit Data Bus
17-bit L2 Address Bus
64-bit L2 Data Bus
Integ
er Unit 2
SSRAM
SSRAM
3
PC755M8
2164AHIREL01/03
Major Features
This section summarizes features of the PC755M8's implementation of the PowerPC
architecture. Major features of the PC755M8 are as follows:
Branch Processing Unit
Four instructions fetched per clock
One branch processed per cycle (plus resolving 2 speculations)
Up to 1 speculative stream in execution, 1 additional speculative stream in
fetch
512-entry branch history table (BHT) for dynamic prediction
64-entry, 4-way set associative Branch Target Instruction Cache (BTIC) for
eliminating branch delay slots
Dispatch Unit
Full hardware detection of dependencies (resolved in the execution units)
Dispatch two instructions to six independent units (system, branch,
load/store, fixed-point unit 1, fixed-point unit 2, floating-point)
Serialization control (predispatch, postdispatch, execution serialization)
Decode
Register file access
Forwarding control
Partial instruction decode
Completion
6-entry completion buffer
Instruction tracking and peak completion of two instructions per cycle
Completion of instructions in program order while supporting out-of-order
instruction execution, completion serialization and all instruction flow
changes
Fixed Point Units (FXUs) that share 32 GPRs for Integer Operands
Fixed Point Unit 1 (FXU1) multiply, divide, shift, rotate, arithmetic, logical
Fixed Point Unit 2 (FXU2) shift, rotate, arithmetic, logical
Single-cycle arithmetic, shifts, rotates, logical
Multiply and divide support (multi-cycle)
Early out multiply
Floating-point Unit and a 32-entry FPR File
Support for IEEE-754 standard single and double precision floating-point
arithmetic
Hardware support for divide
Hardware support for denormalized numbers
Single-entry reservation station
Supports non-IEEE mode for time-critical operations
System Unit
Executes CR logical instructions and miscellaneous system instructions
Special register transfer instructions
4
PC755M8
2164AHIREL01/03
Load/Store Unit
One cycle load or store cache access (byte, half-word, word, double-word)
Effective address generation
Hits under misses (one outstanding miss)
Single-cycle unaligned access within double word boundary
Alignment, zero padding, sign extend for integer register file
Floating-point internal format conversion (alignment, normalization)
Sequencing for load/store multiples and string operations
Store gathering
Cache and TLB instructions
Big and Little-endian byte addressing supported
Misaligned Little-endian supported
Level 1 Cache structure
32K, 32 bytes line, 8-way set associative instruction cache (iL1)
32K, 32 bytes line, 8-way set associative data cache (dL1)
Cache locking for both instruction and data caches, selectable by group of
ways
Single-cycle cache access
Pseudo least-recently used (PLRU) replacement
Copy-back or Write through data cache (on a page by page basis)
Supports all PowerPC memory coherency modes
Non-blocking instruction and data cache (one outstanding miss under hits)
No snooping of instruction cache
Memory Management Unit
128-entry, 2-way set associative instruction TLB
128-entry, 2-way set associative data TLB
Hardware reload for TLBs
Hardware or optional software tablewalk support
8-instruction BATs and 8-data BATs
8 SPRGs, for assistance with software tablewalks
Virtual memory support for up to 4 hexabytes (2
52
) of virtual memory
Real memory support for up to 4 gigabytes (2
32
) of physical memory
Bus Interface
Compatible with 60X processor interface
32-bit address bus
64-bit data bus, 32-bit mode selectable
Bus-to-core frequency multipliers of 2x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x,
7x, 7.5x, 8x, 10x supported
Selectable interface voltages of 2.5V and 3.3V.
Parity checking on both address and data buses
Power Management
Low-power design with thermal requirements very similar to PC740/750
Selectable interface voltage of 1.8V/2.0V can reduce power in output buffers
(compared to 3.3V)
5
PC755M8
2164AHIREL01/03
Three static power saving modes: doze, nap, and sleep
Dynamic power management
Testability
LSSD scan design
IEEE 1149.1 JTAG interface
Integrated Thermal Management Assist Unit
On-chip thermal sensor and control logic
Thermal Management Interrupt for software regulation of junction
temperature
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