2171DHIREL06/04
Features
300 MHz - 333 MHz To Be Confirmed-PC603e Processor Core Implementing the
PowerPC
Architecture
32-bit PCI Interface Operating at up to 66 MHz
Memory Controller Offering SDRAM Support up to 133 MHz Operation, Support up to
2 GB
General Purpose I/O and ROM Interface Support
Two Channel DMA Controller that Supports Chaining
Messaging Unit with I2O Messaging Support Capability
Industry-standard I
2
C Interface
Programmable Interrupt Controller with Multiple Timers and Counters
16550-compatible DUART
Description
The PC8245 combines a PC603e core microprocessor with a PCI bridge. The PCI
support on the PC8245 will allow system designers to rapidly design systems using
peripherals already designed for PCI and the other standard interfaces. The PC8245
also integrates a high-performance memory controller which supports various types of
ROM and SDRAM.
The PC8245 is the second of a family of products that provides system-level support
for industry standard interfaces with a PC603e processor core.
This document describes pertinent electrical and physical characteristics of the
PC8245. For functional characteristics of the processor, refer to the Motorola's docu-
mentation "MPC8245 Integrated Processor User's Manual" (MPC8245UM/D).
Screening/Quality/Packaging
This product is manufactured in full compliance with:
Upscreening based upon Atmel standards
Military temperature range (T
c
= -55
C, T
c
= +125
C)
Core power supply:
2.0 100 mV
I/O power supply: 3.3V
0.3V
352 Tape Ball Grid Array (TBGA)
TP suffix
TBGA352
Tape Ball Grid Array
Integrated
Processor
Family
PC8245
Product
Specification
Rev. 2171DHIREL06/04
2
PC8245
2171DHIREL06/04
General Description
Block Diagram
The PC8245 integrated processor is comprised of a peripheral logic block and a 32-bit
superscalar PowerPC 603e core, as shown in Figure 1.
Figure 1. Block Diagram
Peripheral Logic
Instruction Unit
Address
Translator
DLL
Fanout
Buffers
PCI
Arbiter
I
2
C
Controller
DMA
Controller
EPIC
Interrupt
Controller
/Timers
DUART
Watchpoint
Facility
PCI Bus
Interface Unit
Data Path
ECC Controller
Memory
Controller
Central
Control
Unit
Oscillator
Input
Five Request/
Grant Pairs
I
2
C
5 IRQs/
16 Serial
Interrupts
Processor Core Block
Peripheral Logic Block
Processor
PLL
Instruction
MMU
(64-bit) Two-instruction fetch
(64-bit) Two-instruction dispatch
Peripheral Logic
PLL
SDRAM Clocks
PCI_SYNC_IN
PCI Bus
Clocks
Data (64-bit)
Address
(32-bit)
Data Bus
(32- or 64-bit)
with 8-bit Parity
or ECC
Memory/ROM/PortX
Address and Control
64-bit
32-bit
PCI Interface
Branch
Processing
Unit
(BPU)
System
Register
Unit
(SRU)
Floating
Point
Unit
(FPU)
Integer
Unit
(IU)
Load/Store
Unit
(LSU)
Bus
Performance
Monitor
Data
MMU
16-Kbyte
Data
Cache
16-Kbyte
Instruction
Cache
Configuration
Registers
Additional features:
Prog I/O with Watchpoint
JTAG/COP Interface
Power Management
PC8245
SDRAM_SYNC_IN
Message
Unit
(with I
2
O)
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PC8245
2171DHIREL06/04
The peripheral logic integrates a PCI bridge, dual universal asynchronous
receiver/transmitter (DUART), memory controller, DMA controller, EPIC interrupt con-
troller, a message unit (and I
2
O interface), and a I
2
C inteface controller. The processor
core is a full-featured, high-performance processor with floating-point support, memory
management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power manage-
ment features. The integration reduces the overall packaging requirements and the
number of discrete devices required for an embedded system.
The PC8245 contains an internal peripheral logic bus that interfaces the processor core
to the peripheral logic. The core can operate at a variety of frequencies, allowing the
designer to trade-off performance for power consumption. The processor core is
clocked from a separate PLL, which is referenced to the peripheral logic PLL. This
allows the microprocessor and the peripheral logic block to operate at different frequen-
cies, while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit
data bus (depending on memory data bus width) and a 32-bit address bus along with
control signals that enable the interface between the processor and peripheral logic to
be optimized for performance. PCI accesses to the PC8245 memory space are passed
to the processor bus for snooping when snoop mode is enabled.
The processor core and peripheral logic are general-purpose in order to serve a variety
of embedded applications. The PC8245 can be used as either a PCI host or PCI agent
controller.
General Parameters
The following list provides a summary of the general parameters of the PC8245:
Technology0.25 m CMOS, five-layer metal
Die size
49.2 mm
2
Transistor count4.5 million
Logic designFully static
Packages Surface-mount 352 tape ball grid array (TBGA)
Core power supply:2.0V 100 mV DC
(nominal; see Table "Recommended Operating Conditions" on page 12
for details
I/O power supply3.0 to 3.6V DC
Features
Major features of the PC8245 are as follows:
Processor core
High-performance, superscalar processor core
Integer unit (IU), floating-point unit (FPU) (software enabled or disabled),
load/store unit (LSU), system register unit (SRU), and a branch processing
unit (BPU)
16-Kbyte instruction cache
16-Kbyte data cache
Lockable L1 caches
--
entire cache or on a per-way basis up to three of four
ways
Dynamic power management
--
supports 60x nap, doze, and sleep modes
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Peripheral logic
Peripheral Logic Bus
Supports various operating frequencies and bus divider ratios
32-bit address bus, 64-bit data bus
Supports full memory coherency
Decoupled address and data buses for pipelining of peripheral logic bus
accesses
Store gathering on peripheral logic bus-to-PCI writes
Memory interface
Supports up to 2 Gbytes of SDRAM memory
High-bandwidth data bus (32- or 64-bit) to SDRAM
Programmable timing supporting SDRAM
Supports 1 to 8 banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices
Write buffering for PCI and processor accesses
Supports normal parity, read-modify-write (RMW), or ECC
Data-path buffering between memory interface and processor
Low-voltage TTL logic (LVTTL) interfaces
272 Mbytes of base and extended ROM/Flash/PortX space
Base ROM space supports 8-bit data path or same size as the SDRAM data
path (32- or 64-bit)
Extended ROM space supports 8-, 16-, 32-bit gathering data path, 32- or 64-
bit (wide) data path
PortX: 8-, 16-, 32-, or 64-bit general-purpose I/O port using ROM controller
interface with programmable address strobe timing, data ready input signal
(DRDY), and 4 chip selects
32-bit PCI interface
Operates up to 66 MHz
PCI 2.2-compliant
PCI 5.0V tolerance
Support for dual address cycle (DAC) for 64-bit PCI addressing (master only)
Support for PCI locked accesses to memory
Support for accesses to PCI memory, I/O, and configuration spaces
Selectable big- or little-endian operation
Store gathering of processor-to-PCI write and PCI-to-memory write
accesses
Memory prefetching of PCI read accesses
Selectable hardware-enforced coherency
PCI bus arbitration unit (five request/grant pairs)
PCI agent mode capability
Address translation with two inbound and outbound units (ATU)
Some internal configuration registers accessible from PCI
Two-channel integrated DMA controller (writes to ROM/PortX not supported)
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Supports direct mode or chaining mode (automatic linking of DMA transfers)
Supports scatter gathering
--
read or write discontinuous memory
64-byte transfer queue per channel
Interrupt on completed segment, chain, and error
Local-to-local memory
PCI-to-PCI memory
Local-to-PCI memory
PCI memory-to-local memory
Message unit
Two doorbell registers
Two inbound and two outbound messaging registers
I
2
O message interface
Two-wire interface controller with full master/slave support that accepts broadcast
messages
Embedded programmable interrupt controller (EPIC)
Five hardware interrupts (IRQs) or 16 serial interrupts
Four programmable timers with cascade
Two (dual) universal asynchronous receiver/transmitters (UARTs)
Integrated PCI bus and SDRAM clock generation
Programmable PCI bus and memory interface output drivers
System level performance monitor facility
Debug features
Memory attribute and PCI attribute signals
Debug address signals
MIV signal: marks valid address and data bus cycles on the memory
bus
Programmable input and output signals with watchpoint capability
Error injection/capture on data path
IEEE 1149.1 (JTAG)/test interface
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