1
Features
PC603e
TM
Microprocessor (Embedded PowerPC
TM
Core) at 100 - 200 MHz
140 MIPS at 100 MHz (Dhrystone 2.1)
280 MIPS at 200 MHz (Dhrystone 2.1)
High-performance, Superscalar Microprocessor
Disable CPU Mode
Improved Low-power Core
16-Kbyte Data and 16-Kbyte Instruction Cache, Four-way Set Associative
Memory Management Unit
No Floating Point Unit
Common On-chip Processor (COP)
System Integration Unit (SIU)
Memory Controller, Including Two Dedicated SDRAM Machines
PCI up to 66 MHz (Available in Subsequent Versions)
Hardware Bus Monitor and Software Watchdog Timer
IEEE 1149.1 JTAG Test Access Port
High-performance Communications Processor Module (CPM) with Operating
Frequency up to 166 MHz
PowerPC and CPM May Run at Different Frequencies
Supports Serial Bit Rates up to 710 Mbps at 133 MHz
Parallel I/O Registers
On-board 24 KBytes of Dual-port RAM
Two Multi-channel Controllers (MCCs) Each Supporting 128 Full-duplex, 64-Kbps,
HDLC Lines
Virtual DMA Functionality
Two Bus Architectures: One 64-bit PowerPC and One 32-bit Local Bus (or PCI on
PC8265)
Two UTOPIA Level-2 Master/Slave Ports, Both with Multi-PHY Support. One Can
Support 8/16 bit Data
Three MIL Interfaces
Eight TDM Interfaces (T1/E1), Two TDM Ports Can Be Glueless to T3/E3
Power Consumption: 2.5W at 133 MHz
Description
The PC8260 PowerQUICC II
TM
is a versatile communications processor that inte-
grates on one chip, a high-performance PowerPC (PC603e) RISC microprocessor, a
highly flexible system integration unit, and many communications peripheral control-
lers that can be used in a variety of applications, particularly in communications and
networking systems.
The core is an embedded variant of the PC603e microprocessor, specifically referred
to later in this document as the EC603e, with 16 Kbytes of instruction cache and 16
Kbytes of data cache and no floating-point unit (FPU). The system interface unit (SIU)
consists of a flexible memory controller that interfaces to almost any user-defined
memory system, a 60x-to-PCI bus bridge (available in future revisions) and many
other peripherals, making this device a complete system on a chip.
The communications processor module (CPM) includes all the peripherals found in
the PC860, with the addition of three high-performance communication channels that
support new emerging protocols (for example, 155-Mbps ATM and Fast Ethernet).
Equipped with dedicated hardware, the PC8260 can handle up to 256 full-duplex,
time-division, multiplexed logical channels.
PowerPC-based
Communications
Processors
PC8260
PowerQUICC II
TM
Rev. 2131BHIREL02/03
2
PC8260 PowerQUICC II
2131BHIREL02/03
Screening Quality
Packaging
This product is manufactured in full compliance with:
Upscreening based upon Atmel standards.
Full military temperature range (T
J
= -55
C, T
J
= +125
C)
Industrial temperature range (T
J
= -40
C, T
J
= +110
C)
Core power supply:
2.5V 5% (L-Spec for 200 MHz)
2.50V to 2.75V (R-Spec for 250 MHz) (tbc)
I/O power supply: 3.0V to 3.6V
480-ball Tape Ball Grid Array package (TBGA 37.5 mm x 37.5 mm)
3
PC8260 PowerQUICC II
2131BHIREL02/03
PC8260 Architecture
General Overview
The PC8260 has two external buses to accommodate bandwidth requirements from the
highspeed system core and the very fast communications channels. The device is com-
posed of the following three major functional blocks:
A 64-bit PowerPC core derived from the EC603e with MMUs and caches.
A system interface unit (SIU).
A communications processor module (CPM). Both the system core and the CPM
have an internal PLL, which allows independent optimization of the frequencies at
which they run. The system core and CPM are both connected to the 60x bus.
Figure 1. PC8260 Block Diagram
MCC
MCC
FCC
FCC
FCC
SCC
SCC
SCC
SCC
SMC
SMC
SPI
Clock Counter
Memory Controller
Bus Interface Unit
System Functions
60x-to-Local Bus Bridge
60x-to-PCI Bus Bridge
(PC8265 only)
I C
2
PCI/
Local
Bus
Time Slot Assigner
Serial Interface
8 TDMs
2 UTOPIA
3 Mlls
Non-Multiplexed I/O
60x Bus
16-Kbyte
Instruction Cache
16-Kbyte
Data Cache
IMMU
DMMU
EC603e
PowerPC
Core
Timers
Parallel I/O
Baud Rate
Generator
Interrupt
Controller
24-Kbyte Dual-
Port RAM
32-Bit RISC Communications
Processor (CP) and
Program ROM
Serial DMAs
4 Virtual
IDMAs
4
PC8260 PowerQUICC II
2131BHIREL02/03
EC603e Core
The EC603e core is derived from the PowerPC603e microprocessor without the float-
ing-point unit and with power management modifications.The core is a high-
performance low-power implementation of the PowerPC family of reduced instruction
set computer (RISC) microprocessors. The EC603e core implements the 32-bit portion
of the PowerPC architecture, which provides 32-bit effective addresses, integer data
types of 8, 16 and 32 bits. The EC603e cache provides snooping to ensure data coher-
ency with other masters. This helps ensure coherency between the CPM and system
core.
The core includes 16 Kbytes of instruction cache and 16 Kbytes of data cache. It has a
64-bit split-transaction external data bus which is connected directly to the external
PC8260 pins.
The EC603e core has an internal common on-chip (COP) debug processor. This pro-
cessor allows access to internal scan chains for debugging purposes. It is also used as
a serial connection to the core for emulator support.
The EC603e core performance for the SPEC 95 benchmark for integer operations
ranges between 4.4 and 5.1 at 200 MHz. In Dhrystone 2.1 MIPS, the EC603e is 280
MIPS at 200 MHz (compared to 86 MIPS of the PC860 at 66 MHz).
The EC603e core can be disabled. In this mode, the PC8260 functions as a slave
peripheral to an external core or to another PC8260 device with its core enabled.
5
PC8260 PowerQUICC II
2131BHIREL02/03
System Interface Unit
(SIU)
The SIU consists of the following:
A 60x-compatible parallel system bus configurable to 64-bit data width. The PC8260
supports 64-, 32-, 16-, and 8-bit port sizes.The PC8260 internal arbiter arbitrates
between internal components that can access the bus (system core, PCI bridge,
CPM, and one external master). This arbiter can be disabled, and an external
arbiter can be used if necessary.
A local (32-bit data, 32-bit internal and 18-bit external address) bus. This bus is
used to enhance the operation of the very high-speed communication controllers.
Without requiring extensive manipulation by the core, the bus can be used to store
connection tables for ATM or buffer descriptors (BDs) for the communication
channels or raw data that is transmitted between channels. The local bus is
synchronous to the 60x bus and runs at the same frequency.
The local bus can be configured as a 32-bit data and up to 66 MHz PCI (version 2.1)
bus. In PCI mode the bus can be programmed as a host or as an agent. The PCI
bus can be configured to run synchronously or asynchronously to the 60x bus. The
PC8260 has an internal PCI bridge with an efficient 60x-to-PCI DMA for memory
block transfers.
Applications that require both the local bus and PCI bus need to connect an external
PCI bridge.
A memory controller supporting 12 memory banks that can be allocated for either
the system or the local bus. The memory controller is an enhanced version of the
PC8260 memory controller. It supports three user-programmable machines.
Besides supporting all PC8260 features, the memory controller also supports
SDRAM with page mode and address data pipeline
Supports JTAG controller IEEE 1149.1 test access port (TAP).
A bus monitor that prevents 60x bus lock-ups, a real-time clock, a periodic interrupt
timer, and other system functions useful in embedded applications.
Glueless interface to L2 cache and 4-/16-K-entry CAM.
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