1
Features
Low-power Operation Including Special STOP Mode
Frequency: 16.78 MHz at 5V 10% Supply and 20.97 MHz at 5V 5%, Software
Programmable
Technology: 1
High-density Complementary Metal-Oxide Semiconductor (HCMOS),
Static Design
Package: 132-pin Ceramic Leaded Chip Carrier (CERQUAD) and 132-pin Ceramic Pin
Grid Array (PGA)
Modular Architecture in a Single Chip
CPU: 32-bit 6800 Family (Upward Object-code Compatible With The 68010)
New Instructions For Controller Applications
Intelligent 16-bit Timer
16 Independent, Programmable Channels
Any Channel Can Perform Any Time Function (for Example Input Capture, Output
Compare, Pulse Width Modulation, etc.)
Two timer Count Registers with 2-bit Programmable Prescalers
Selectable Channel Priority Levels
Reduced CPU Intervention
RISC like CPU Within the TPU
Two Serial I/O Subsystems
Enhanced 68HC11-type Serial Communications Interface (SCI) Universal
Asynchronous Receiver Transmitter (UART) with Parity
Enhanced 68HC11-type Serial Peripheral Interface With I/O RAM Queue (QSPI)
On-chip Memory: 2-Kbytes Standby RAM
On-chip, Programmable, Chip-select Logic
Up to 12 Signals for Memory and Peripheral Interface with I/O Select
System Failure Protection
68HC11-type Computer Operating Properly (COP) Watchdog Timer
68HC11-type Periodic Interrupt Timer
68000 Family Spurious Interrupt, Halt, and Bus Time-out Monitors
Up to 48 Discrete I/O Pins
Description
The TS68332 is a 32-bit microcontroller, combining high-performance data manipula-
tion capabilities with powerful peripheral subsystems. The TS68332 is the first
member of the 68300 family of modular embedded controllers featuring fully static,
high-speed complementary metal-oxide semiconductor technology. Based on the
powerful TS68020, the CPU32 instruction processing module provides enhanced sys-
tem performance and utilizes the extensive software base of the 68000 family.
High-
performance
32-bit Integrated
Microcontroller
TS68332
Rev. 2118AHIREL03/02
2
TS68332
2118AHIREL03/02
Screening/Quality
This product is manufactured in full compliance with:
MIL-STD-883 (class B)
DSCC 5962-91501
Or according to Atmel-Grenoble standard
Introduction
Figure 1 is a block diagram of the TS68332 showing the major components. The pin
descriptions are provided in Table 1. The TS68332 contains intelligent peripheral mod-
ules such as the Time Processor Unit (TPU), which provides 16 microcoded channels
for performing time-related activities from simple input capture or output compare to
complicated motor control or pulse width modulation. High-speed serial communications
are provided by the Queued Serial Module (QSM) with synchronous and asynchronous
protocols available. 2-Kbytes of fully static standby RAM allow fast two-cycle access for
system and data stacks and variable storage with provision for battery back-up. There is
a System Integration Module (SIM) which includes twelve chip selects to enhance sys-
tem integration for fast external memory or peripheral access. The powerful 32-bit CPU
(CPU 32) is based on the industry-standard TS68020. These modules are connected on
chip via the Intermodule Bus (IMB) and provide reduced system part count, size, cost of
implementation and increased reliability.
R suffix
PGA 132
Ceramic Pin Grid Array
A suffix
CERQUAD 132
Ceramic Leaded Chip Carrier
4
TS68332
2118AHIREL03/02
Signal Description
Figure 1 illustrates the functional signal groups and Table 1 lists the signals and their
function.
Table 1. Signal Index
Signal Name
Mnemonic
Function
Address Bus
A23 - A0
24-bit address bus
Data Bus
D15 - D0
16-bit data bus used to transfer byte or word data per bus cycle
Data Bus Function Codes
FC2 - FC0
Identify the processor state and the address space of the current bus cycle
Boot Chip Select
CSBOOT
Chip-select boot stat up ROM containing user's reset vector and initialization
program
Chip Selects
CS10 - CSO
Enables peripherals at programmed addresses
Bus Request
BR
Indicates that an external device requires bus mastership
Bus Grant
BG
Indicates that current bus cycle is complete and the TS68332 has relinquished the
bus
Bus Grant Acknowledge
BGACK
Indicates that an external device has assumed bus mastership
Data and Size
Acknowledgement
DSACK1,
DSACK0
Provides asynchronous data transfers and dynamic bus sizing
Autovector
AVEC
Requests an automatic vector during an interrupt acknowledge cycle
Read-Modify-Write Cycle
RMC
Identifies the bus cycle as part of an indivisible read-modify-write cycle
Address Strobe
AS
Indicates that a valid address is on the address bus
Data Strobe
DS
During a read cycle, DS indicates that an external device should place valid data on
the data bus. During a write cycle, DS indicates that valid data is on the data bus.
Size
SIZ1 - SIZ0
Indicates the number of bytes remaining to be transferred for this cycle
Read/Write
R/W
Indicates the direction of data transfer on the bus
Interrupt Request Level
IRQ7 - IRQ0
Provides an interrupt priority level to the CPU
Reset
RESET
System reset
Halt
HALT
Suspend external bus activity
Bus Error
BERR
Indicates that an erroneous bus operation is being attempted
System Clockout
CLKOUT
Internal system clock
Crystal Oscillator
EXTAL,
XTAL
Connection for an external crystal to the internal oscillator circuit
External Filter Capacitor
XFC
Connection pin for an external capacitor to filter the circuit of the phase-locked loop
Clock Mode Select
MODCK
Selects the source of the internal system clock
Instruction Fetch
IFETCH
Indicates when the CPU is performing an instruction word pre-fetch and when the
instruction pipeline has been flushed
Instruction Pipe
IPIPE
Used to track movement of words through the instruction pipeline
Breakpoint
BKPT
Signals a hardware breakpoint to the CPU
Freeze
FREEZE
Indicates that the CPU has acknowledged a breakpoint
Quotient Out
QUOT
Serial I/O and clock for background debug mode
Test Mode Enable
TSTME
Hardware enable for test mode
Three-State Control
TSC
Places all output drivers in a high-impedance state
5
TS68332
2118AHIREL03/02
Development Serial In, Out,
Clock
DSI, DSO,
DSCLK
Serial I/O and clock for background debug mode
TPU Channels
TP15 - TP0
TPU channel input/output Serial I/O and clock for background debug mode
TPU Clock In
T2CLK
External clock source to the TPU
SCI Receive Data
RXD
Serial input to the SCI
SCI Transmit Data
TXD
Serial output from the SCI
Peripheral Chip Select
PCS3 - PCS0
QSPI peripheral chip selects
Slave Select
SS
Places the QSPI in slave mode
QSPI Serial Clock
SCK
Furnishes the clock from the QSPI in master mode or to the QSPI in slave mode
Master-in Slave-out
MISO
Furnishes serial input to the QSPI in master mode, and serial output from the QSPI in
slave mode
Master-out Slave-in
MOSI
Furnishes serial output from the QSPI in master mode, and serial input to the QSPI in
slave mode
Standby RAM
V
STBY
Power supply for RAM
Synchronizer Power
V
DDSYN
Power supply to VCO
System Power Supply and
Return
V
DD
, V
SS
Power supply and return to the MCU
Table 1. Signal Index (Continued)
Signal Name
Mnemonic
Function
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