1
2193ABDC06/03
Main Features
8-bit Resolution
500 Msps (min) Sampling Rate
Power Consumption: 3.8W Typ
500 mVpp Differential or Single-ended Analog Inputs
Differential or Single-ended 50
ECL Compatible Clock Inputs
ECL or LVDS/HSTL Output Compatibility
ADC Gain Adjust
Data Ready Output with Asynchronous Reset
Gray or Binary Selectable Output Data; NRZ Output Mode
Enhanced CBGA Package with Ceramic Lid
Evaluation Board: TSEV8308500GL (Detailed Specification on Request)
Demultiplexer TS81102G0: Companion Device Available
Performance
1.3 GHz Full Power Input Bandwidth
Band Flatness: 0.5 dB up to 500 MHz
SINAD = 45 dB (7.2 Effective Bits), SFDR = 54 dBc
at F
S
= 500 Msps, F
IN
= 20 MHz
SINAD = 43 dB (7.1 Effective Bits), SFDR = 53 dBc
at F
S
= 500 Msps, F
IN
= 250 MHz
SINAD = 42 dB (7.0 Effective Bits), SFDR = 52 dBc
at F
S
= 500 Msps, F
IN
= 500 MHz (-3 dB FS)
2-tone IMD: TBD (199.5 MHz, 200.5 MHz) at 500 Msps
DNL = 0.3 LSB INL = 0.7 LSB
Low Bit Error Rate (10
-13
) at 500 Msps, Tj = 90
C
Applications
Digital Sampling Oscilloscopes
Satellite Receiver
Electronic Countermeasures/Electronic Warfare
Direct RF Down-conversion
Screening
Atmel Standard Screening Level
Temperature Range:
0
C < Tc; Tj < +90
C
-40
C < Tc ; Tj < + 110
C
Description
The TS8308500 is a monolithic 8-bit analog-to-digital converter, designed for digitizing
wide bandwidth analog signals at very high sampling rates of up to 500 Msps.
The TS8308500 is using an innovative architecture, including an on-chip Sample and
Hold (S/H), and is fabricated with an advanced high-speed bipolar process.
The on-chip S/H has a 1.3 GHz full power input bandwidth, providing excellent
dynamic performance in undersampling applications (High IF digitizing).
ADC 8-bit
500 Msps
TS8308500
Rev. 2193ABDC04/03
2
TS8308500
2193ABDC04/03
Functional
Description
Block Diagram
Figure 1. Simplified Block Diagram
Functional
Description
The TS8308500 is an 8-bit 500 Msps ADC based on an advanced high-speed bipolar technol-
ogy featuring a cutoff frequency of 25 GHz.
The TS8308500 includes a front-end master/slave Track and Hold stage (S/H), followed by an
analog encoding stage and interpolation circuitry.
Successive banks of latches are regenerating the analog residues into logical data before
entering an error correction circuitry and a resynchronization stage followed by 75
differential
output buffers.
The TS8308500 works in fully differential mode from analog inputs up to digital outputs.
The TS8308500 features a full-power input bandwidth of 1.3 GHz.
Control pin GORB is provided to select either the Gray or Binary data output format.
The gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8308500.
The TS8308500 uses only vertical isolated NPN transistors together with oxide isolated poly-
silicon resistors, which allow enhanced radiation tolerance (no performance drift measured at
150 kRad total dose).
Master/Slave Track & Hold Amplifier
V
IN
, V
INB
Clock
Buffer
GAIN
GORB
DATA, DATAB OR, ORB
DRRB DR, DRB
CLK, CLKB
4
4
5
4
5
8
8
Resistor
Chain
Analog
Encoding
Block
Interpolation
Stages
Regeneration
Latches
Error Correction &
Decode Logic
Output Latches &
Buffers
3
TS8308500
2193ABDC04/03
Specifications
Absolute
Maximum Ratings
Note:
Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are
within specified operating conditions. Long exposure to maximum ratings may affect device reliability. The use of a thermal heat
sink is mandatory (see Thermal characteristics).
Recommended
Conditions of Use
Table 1. Absolute Maximum Ratings
Parameter
Symbol
Comments
Value
Unit
Positive supply voltage
V
CC
GND to 6
V
Digital negative supply voltage
DV
EE
GND to -5.7
V
Digital positive supply voltage
V
PLUSD
GND -0.3 to 2.8
V
Negative supply voltage
V
EE
GND to -6
V
Maximum difference between negative supply voltages
DV
EE
to V
EE
0.3
V
Analog input voltages
V
IN
or V
INB
-1 to 1
V
Maximum difference between V
IN
and V
INB
V
IN
- V
INB
-2 to 2
V
Digital input voltage
V
D
GORB
-0.3 to V
CC
0.3
V
Digital input voltage
V
D
DRRB
V
EE
-0.3 to 0.9
V
Digital output voltage
V
O
V
PLUSD
-3 to V
PLUSD
-0.5
V
Clock input voltage
V
CLK
or V
CLKB
-3 to 1.5
V
Maximum difference between V
CLK
and V
CLKB
V
CLK
- V
CLKB
-2 to 2
V
Maximum junction temperature
T
j
135
C
Storage temperature
T
stg
-65 to 150
C
Lead temperature (soldering 10s)
T
leads
300
C
Table 2. Recommended Conditions of Use
Parameter
Symbol
Comments
Recommended Value
Unit
Min
Typ
Max
Positive supply voltage
V
CC
4.75
5
5.25
V
Positive digital supply voltage
V
PLUSD
ECL output compatibility
GND
V
Positive digital supply voltage
V
PLUSD
LVDS output compatibility
1.4
2.4
2.6
V
Negative supply voltages
V
EE,
DV
EE
-5.25
-5
-4.75
V
Differential analog input voltage
(full-scale)
V
IN,
V
INB
V
IN
- V
INB
50
differential or single-ended
113
450
125
500
137
550
mV
mVpp
Clock input power level
P
CLK,
P
CLKB
50
single-ended clock input
3
4
10
dBm
Operating temperature range
T
J
Commercial grade: "C"
Industrial grade "V"
0 < Tc; Tj < 90
-40 < Tc; Tj < 110
C
4
TS8308500
2193ABDC04/03
Electrical
Operating
Characteristics
V
EE
= DV
EE
= -5V; V
CC
= +5V; V
IN
-V
INB
= 500 mVpp Full Scale differential input
50
differentially terminated digital outputs
Tj (typical) = 70
C
Table 3. Electrical Specifications
Parameter
Symbol
Test
Level
Value
Unit
Note
Min
Typ
Max
Power Requirements
Positive supply voltage
Analog
Digital (ECL)
Digital (LVDS)
V
CC
V
PLUSD
V
PLUSD
1
4
4
4.5
1.4
5
0
2.4
5.5
2.6
V
V
V
Positive supply current
Analog
Digital
I
CC
I
PLUSD
1
1
420
130
445
145
mA
mA
Negative supply voltage
V
EE
1
-5.5
-5
-4.5
V
Negative supply current
Analog
Digital
AI
EE
DI
EE
1
1
185
160
200
180
mA
mA
Nominal power dissipation
PD
1
3.9
4.1
W
Power supply rejection ratio
PSRR
4
0.5
2
mW
Resolution
8
bits
(2)
Analog Inputs
Full-scale input voltage range (differential mode)
(0V common mode voltage)
V
IN
V
INB
4
-125
-125
125
125
mV
mV
Full-scale input voltage range (single-ended input
option)
(14)
V
IN
V
INB
4
-250
0
250
mV
mV
Analog input capacitance
C
IN
4
3
3.5
pF
Input bias current
I
IN
4
10
20
A
Input Resistance
R
IN
4
0.5
1
M
Full Power input Bandwidth (-3 dB)
FPBW
4
1.8
GHz
Small signal input Bandwidth (10% full-scale)
SSBW
4
1.7
GHz
Clock Inputs
Logic compatibility for clock inputs
(14)
ECL or specified clock input
power level in dBm
(8)
ECL Clock inputs voltages (V
CLK
or V
CLKB
):
4
Logic 0 voltage
V
IL
-1.5
V
Logic 1 voltage
V
IH
-1.1
V
Logic 0 current
I
IL
5
50
A
Logic 1 current
I
IH
5
50
A
Clock input power level into 50
termination
dBm into 50
5
TS8308500
2193ABDC04/03
Clock input power level
4
-2
4
10
dBm
Clock input capacitance
C
CLK
4
3
3.5
pF
Digital Outputs
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), binary output data format,
Tj (typical) = 70
C. Full temperature range: 0
C < Tc; Tj < +90
C or -40
C < Tc ; Tj < 110
C
(1)(6)
Logic compatibility for digital outputs
(Depending on the value of V
PLUSD
)
(14)
ECL or LVDS
Differential output voltage swings
(assuming V
PLUSD
= 0V):
4
75
open transmission lines (ECL levels)
1.5
1.620
V
75
differentially terminated
0.70
0.825
V
50
differentially terminated
0.54
0.660
V
Output levels (assuming V
PLUSD
= 0V)
75
open transmission lines:
4
(6)
Logic 0 voltage
V
OL
-1.62
-1.54
V
Logic 1 voltage
V
OH
-0.88
-0.8
V
Output levels (assuming V
PLUSD
= 0V)
75
differentially terminated:
4
(6)
Logic 0 voltage
V
OL
-1.41
-1.34
V
Logic 1 voltage
V
OH
-1.07
-1
V
Output levels (assuming V
PLUSD
= 0V)
50
differentially terminated:
(6)
Logic 0 voltage
V
OL
1, 2
-1.40
-1.32
V
Logic 1 voltage
V
OH
1, 2
-1.16
-1.10
V
Differential Output Swing
DOS
4
270
300
mV
Output level drift with temperature
4
1.6
mV/
C
DC Accuracy
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format
Tj (typical) = 70
C
Differential non linearity
DNL-
1
-0.6
-0.4
lsb/V
(2)(3)
Differential non linearity
DNL+
1
0.4
0.6
lsb/V
Integral non linearity
INL-
1
-1.2
-0.7
lsb/V
(2)(3)
Integral non linearity
INL+
1
0.7
1.2
lsb/V
No missing codes
Guaranteed over specified temperature range
(3)
Gain
1, 2
90
98
110
%/V
Input offset voltage
1, 2
-26
-5
26
mV/V
Table 3. Electrical Specifications (Continued)
Parameter
Symbol
Test
Level
Value
Unit
Note
Min
Typ
Max
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