1
Features
Vcc = 5V 5%
Military Temperature Range
Fully Compatible with the TS68040
Five Low Skew Outputs
Five Outputs (Q0-Q4) with Output-to-Output Skew < 500 ps Each Being Phase End
Frequency Locked to the SYNC Input
Three Additional Outputs are Available:
The 2X_Q Output Runs Twice the System "Q" Frequency
The Q/2 Output Runs At 1/2 the System "Q" Frequency
The Q5 Output is Inverted (180
Phase Shift)
Two Selectable Clock Inputs
Two Selectable CLOCK Inputs are Available for Test or Redundancy Purposes
Test Mode Pin (PLL_EN) Provided for Low Frequency Testing
All Outputs Can Go Into High Impedance (3-state) for Board Test Purposes
Input Frequency Range From 5 MHz to 2X_Q FMAX
Three Input/Output Ratios
Input/Output Phase-locked Frequency Ratios of 1:2, 1:1 and 2:1 are Available
Low Part-to-part Skew
The Phase Variation from Part-to-part Between the SYNC and FEEDBACK Inputs is
Less than 550 ps (Derived From the tPD Specification, which Defines the
Part-to-part Skew)
CMOS and TTL Compatible
All Outputs Can Drive Either CMOS or TTL Inputs
All Inputs are TTL-level Compatible
LOCK Indicator (LOCK) Indicates a Phase-locked State
Description
The TS88915T Clock Driver utilizes a phazed-locked loop (PLL) technology to lock its
low skew outputs' frequency and phase onto an input reference clock. It is designed to
provide clock distribution for high performance microprocessors such as TS68040,
TSPC603E,TSPC603P,TSPC603R, PCI bridge, RAM's, MMU's.
Screening/Quality
This Product is Manufactured:
Based Upon the Generic Flow of MIL-STD-883
or According to Atmel-Grenoble Standard
R suffix
PGA 29
Ceramic Pin Grid Array
W suffix
LDCC 28
Leaded Ceramic Chip Carrier
Low Skew
CMOS PLL
Clock Driver
Tri-State 70 and
100 MHz
Versions
TS88915T
Rev. 2122AHIREL06/02
2
TS88915T
2122AHIREL06/02
Introduction
The TS88915T is a CMOS PLL Clock Driver using phase-locked loop (PLL) technology.
The PLL allows the high current and low skew outputs to lock onto a single input and
distribute it with essentially zero delay to multiple components on a board. The PLL also
allows the TS88915T to multiply a low frequency input clock and distribute it locally at a
higher (2X) system frequency. Multiple 88915's can lock onto a single reference clock,
which is ideal for applications when a central system clock must be distributed synchro-
nously to multiple boards (see Figure 12).
Figure 1. TS88915T Block Diagram (All Versions)
FEEDBACK
SYNC[0]
SYNC[1]
REF_SEL
PLL_EN
FREQ_SEL
OE/RST
DIVIDE
BY TWO
MUX
0
1
(1)
(2)
M
U
X
1
0
M
U
X
0
1
PHASE/FREQ.
DETECTOR
EXT. REC NETWORK
(RC1 pin)
VOLTAGE
CONTROLLED
OSCILLATOR
CHARGE PUMP/
LOOP FILTER
LOCK
2X_Q
Q0
Q1
Q2
Q3
Q4
Q5
Q/2
D
Q
Q
R
CP
D
Q
Q
R
CP
D
Q
Q
R
CP
D
Q
Q
R
CP
D
Q
Q
R
CP
D
Q
Q
R
CP
D
Q
Q
R
CP
3
TS88915T
2122AHIREL06/02
Pin Assignments
29-lead Pin Grid Array
(PGA)
Figure 2. 29-lead PGA (Bottom View)
28-lead Ceramic Leaded
Chip Carrier (LDCC)
Figure 3. 28-lead LDCC (Top View)
1
2
3
4
5
6
A
B
C
D
E
F
TS88915T
(BOTTOM VIEW)
VCC
GND
Q4
FDBK
SYC0
VCCA
GNDA
RST
Q5
VCC
Q/2
GND
VCC
Q2
LOCK
F/SL
SYC1
RC1
R/SL
VCC
Q0
GND
GND
Q1
P/EN
GND
Q3
Q*2
NC
FEEDBACK
REF_SEL
SYNC[0]
VCC (AN)
RC1
GND (AN)
SYNC[1]
5
6
7
8
9
10
11
25
24
23
22
21
20
19
TS88915T
(TOP VIEW)
OE/RST VCC
VCC 2X_Q
GND
Q5
Q4
FREQ_SELGND
GND PLL_EN
Q0
Q1
VCC
12
13
14
15
16
17
18
4
3
2
1
28
27
26
Q/2
GND
Q3
VCC
Q2
GND
LOCK
4
TS88915T
2122AHIREL06/02
Signal Description
Scope
This drawing describes the specific requirements for the clock driver TS88915T, in com-
pliance with MIL-STD-883 class B or Atmel standard screening.
Applicable
Documents
1. MIL-STD-883: Test methods and procedures for electronics.
2. MIL-PRF-38535 appendix A: General specifications for microcircuits.
Requirements
General
The microcircuits are in accordance with the applicable documents and as specified
herein.
Design and Construction
Terminal Connections
Depending on the package, the terminal connections shall be as shown in Figure 2 and
Figure 3.
Lead Material and Finish
Lead material and finish shall be as specified in MIL-STD-1835 (see "Package Mechan-
ical Data" on page 17).
Package
The macrocircuits are packaged in hermetically sealed ceramic packages, which con-
form to case outlines of MIL-STD-1835, but "Package Mechanical Data" on page 17.
The precise case outlines are described at the end of the specification (see "Package
Mechanical Data" on page 178) and into MIL-STD-1835.
Table 1. Signal Index
Pin Name
Num
I/O
Signal Function
SYNC[0]
1
Input
Reference Clock Input
SYNC[1]
1
Input
Reference Clock Input
REF_SEL
1
Input
Chooses Reference Between SYNC[0] and SYNC[1]
FREQ_SEL
1
Input
Doubles VCO Internal Frequency
FEEDBACK
1
Input
Feedback Input to Phase Detector
RC1
1
Input
Input for External RC Network
Q(0-4)
5
Output
Clock Output (Locked to SYNC)
Q5
1
Output
Inverse of Clock Output
2x_Q
1
Output
2 x Clock Output (Q) Frequency (Synchronous)
Q/2
1
Output
Clock Output (Q) Frequency 2 (Synchronous)
LOCK
1
Output
Indicates Phase Lock has been Achieved (High when Locked)
OE/RST
1
Input
Output Enable/Asynchronous Reset (Active Low)
PLL_EN
1
Input
Disables Phase-lock for Low Frequency Testing
VCC, GND
11
Power
Power and Ground pins
Pins 8 and 10 are "analog" supply pins for internal PLL only
5
TS88915T
2122AHIREL06/02
Absolute Maximum
Ratings
Stresses above the absolute maximum rating may cause permanent damage to the
device. Extended operation at the maximum levels may degrade performance and affect
reliability.
Note:
Functional operating conditions are given in AC and DC electrical specifications.
Stresses beyond the absolute maximums listed may affect device reliability or cause per-
manent damage to the device.
Caution: Input voltage must not be greater than the supply voltage by more than 2.5V at
all times including during power-on reset.
Mechanical and
Environment
The microcircuits shall meet all environmental requirements of either MIL-STD-883 for
class B devices or for Atmel standard screening.
Marking
The document that defines the markings is identified in the related reference docu-
ments. Each microcircuit is legible and permanently marked with the following
information as minimum:
Atmel Logo
Manufacturer's Part Number
Class B Identification
Date-code of Inspection Lot
ESD Identifier If Available
Country of Manufacturing
Electrical
Characteristics
General Requirements
All static and dynamic electrical characteristics specified for inspection purposes and the
relevant measurement conditions are given below:
Table Static Electrical Characteristics for the Electrical Variants
Table Dynamic Electrical Characteristics for TS88915T (70 MHz and 100 MHz
Versions)
Table 2. Absolute Maximum Rating for the TS88915T
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
-0.5
6.0
V
Input Voltage
V
in
-0.5
V
CC
+
0.5
V
Storage Temperature Range
T
stg
-65
+150
C
Power Dissipation
PGA Package
LDCC Package
P
D
500
mW
Thermal Resistance Junction-Case
PGA29
LDCC28
JC
-
-
7
7
C/W
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