2102CHIREL01/05
Features
Processor Bus Frequency Up to 66 MHz and 83.3 MHz
64-bit Data Bus and 32-bit Address Bus
L2 Cache Control for 256-Kbyte, 512-Kbyte, 1-Mbyte Sizes
Provides Support for Either Asynchronous SRAM, Burst SRAM
or Pipelined Burst SRAM
Compliant with PCI Specification, Revision 2.1
PCI Interface Operates at 20 to 33 MHz, 3.3V/5.0V-compatible
IEEE 1149.1-compliant, JTAG Boundary-scan Interface
P
D
Max = 1.7 Watts (66 MHz), Full Operating Conditions
Nap, Doze and Sleep Modes Reduce Power Consumption
Fully Compliant with MIL-STD-883 Class Q or According to Atmel Standards
Upscreenings Based on Atmel Standards
Full Military Temperature Range (-55
C T
j
+125C)
Industrial Temperature Range (-40
C T
j
+110C)
V
CC
= 3.3V 5%
Available in a 303-ball CBGA or a 303-ball CBGA with Solder Column Interposer (SCI)
(CI-CGA) Package
Description
The TSPC106 provides an integrated, high-bandwidth, high-performance, TTL-com-
patible interface between a 60x processor, a secondary (L2) cache or up to a total of
four additional 60x processors, the PCI bus and main memory.
PCI support allows system designers to rapidly design systems using peripherals
already designed for PCI.
The TSPC106 uses an advanced 3.3V CMOS-process technology and maintains full
interface compatibility with TTL devices.
The TSPC106 integrates system testability and debugging features via JTAG bound-
ary-scan capability.
G suffix
CBGA 303
Ceramic Ball Grid Array
GS suffix
CI-CGA 303
Ceramic Ball Grid Array
with Solder Column Interposer (SCI)
PCI Bus Bridge
Memory
Controller
66-83 MHz
TSPC106
Rev. 2102CHIREL01/05
2
TSPC106A
2102CHIREL01/05
Figure 1. TSPC106 Block Diagram
Functional Description
The TSPC106 provides a PowerPC
microprocessor CHRP-compliant bridge between
the PowerPC microprocessor family and the PCI bus. CHRP is a set of specifications
that defines a unified personal computer architecture and brings the combined advan-
tages of the Power Macintosh
platform and the standard PC environment to both
system vendors and users. PCI support allows system designers to rapidly design sys-
tems using peripherals already designed for PCI and other standard interfaces available
in the personal computer hardware environment. These open specifications make it
easier for system vendors to design computers capable of running multiple operating
systems. The TSPC106 integrates secondary cache control and a high-performance
memory controller. The TSPC106 uses an advanced 3.3V CMOS process technology
and is fully compatible with TTL devices.
The TSPC106 supports a programmable interface to a variety of PowerPC microproces-
sors operating at select bus speeds. The 60x address bus is 32 bits wide; the data bus
is 64 bits wide. The 60x processor interface of the TSPC106 uses a subset of the 60x
bus protocol, supporting single-beat and burst data transfers. The address and data
buses are decoupled to support pipelined transactions.
Memory
Interface
Power Management
60x Processor
Interface
L2 Cache
Interface
Error/Interrupt
Control
Target
Master
Configuration
Registers
PCI Interface
Memory
L2
60x Bus
PCI Bus
3
TSPC106A
2102CHIREL01/05
The TSPC106 provides support for the following configurations of 60x processors and
L2 cache:
Up to four 60x processors with no L2 cache
A single 60x processor plus a direct-mapped, lookaside L2 cache using the internal
L2 cache controller of the TSPC106
Up to four 60x processors plus an externally controlled L2 cache (e.g., the Freescale
MPC2604GA integrated L2 lookaside cache)
The memory interface controls processor and PCI interactions to main memory and is
capable of supporting a variety of configurations using DRAM, EDO, or SDRAM and
ROM or Flash ROM.
The PCI interface of the TSPC106 complies with the PCI local bus specification Revi-
sion 2.1 and follows the guidelines in the PCI System Design Guide Revision 1.0 for
host bridge architecture. The PCI interface connects the processor and memory buses
to the PCI bus to which I/O components are connected. The PCI bus uses a 32-bit mul-
tiplexed address/data bus plus various control and error signals.
The PCI interface of the TSPC106 functions as both a master and target device. As a
master, the 106 supports read and write operations to the PCI memory space, the PCI
I/O space and the PCI configuration space. The TSPC106 also supports PCI special-
cycle and interrupt-acknowledge commands. As a target, the TSPC106 supports read
and write operations to system memory.
The TSPC106 provides hardware support for four levels of power reduction: doze, nap,
sleep and suspend. The design of the TSPC106 is fully static, allowing internal logic
states to be preserved during all power saving modes.
5
TSPC106A
2102CHIREL01/05
Figure 3. Pin Assignments Shading Ley
Pinout
NC
VSS
No connect
Power Supply Ground
VDD
AVDD
Power Supply Positive
Clock Power Supply Positive (K9)
Signals
VIEW
Table 1. TSPC106 Pinout in 303-ball CBGA Package
Signal Name
Pin Number
Active
I/O
60x Processor Interface Signals
A[0:31]
R2, P2, N2, M2, L2, K2, J5, K4, K5, K6, J2, J6, J3, J4, H3, H4, H2, G2,
F1, E1, E2, F4, E3, D1, C1, C2, B1, C3, B2, E4, D3, E5
High
I/O
AACK
D2
Low
I/O
ARTRY
F2
Low
I/O
BG0
K3
Low
Output
BG1 (DIRTY_OUT)
R4
Low
Output
BG2 (TWE)
R5
Low
Output
BG3 (DCS)
T1
Low
Output
BR0
L3
Low
Input
BR1 (DIRTY_IN)
T3
Low
Input
BR2 (TV)
T6
Low
Input
BR3 (BA0)
T5
Low
Input
CI
N3
Low
I/O
DBG0
L5
Low
Output
DBG1 (TOE)
U4
Low
Output
DBG2 (DWE0)
P3
Low
Output
DBG3 (DWE1)
H11
Low
Output
DBGLB (CKE)
J10
Low
Output
DH[0:31]
T14, R13, R14, P13, P14, N13, U3, W1, V2, W2, V3, W3, V4, W4, V5,
W5, V6, W6, V7, W7, V8, W8, N8, W9, V9, W10, V10, W11, V11, W12,
V12, W13
High
I/O
DL[0:31]
U6, T7, U7, T8, U8, R8, P8, N9, P9, R9, U9, T9, U10, T10, U13, T13,
R12, N14, M13, T2, U1, U2, V1, U15, V16, U14, W16, V15, W15, V14,
W14, V13
High
I/O
GBL
M3
Low
I/O
LBCLAIM
N4
Low
Input
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