1
AFE1144
AFE1144
AFE1144
HDSL /MDSL ANALOG FRONT END
FEATURES
q
LOWER OUT OF BAND PSD
q
SSOP-28
q
PIN COMPATIBLE WITH AFE1124
DESCRIPTION
Burr-Brown's Analog Front End chip greatly reduces
the size and cost of an xDSL (Digital Subscriber Line)
system by providing all of the active analog circuitry
needed to connect a digital signal processor to an
external compromise hybrid and line transformer. The
AFE1144 is optimized for HDSL (High bit rate DSL)
and for lower speed MDSL (Medium speed DSL) and
RADSL (Rate Adaptive DSL) applications. Because
the transmit and receive filter responses automatically
change with clock frequency, the AFE1144 is particu-
larly suitable for RADSL and multiple rate DSL sys-
tems. The device operates over a wide range of data
rates from 64kbps to 1168kbps.
Modulator
Pulse Former
Programmable
Gain Amp
Difference
Amplifier
Patents Pending
AFE1144
Line Driver
txLINE
txLINE
rxHYB
rxHYB
rxLINE
rxLINE
tx and rx
Control
Registers
tx and rx
Interface
Lines
Decimation
Filter
1999 Burr-Brown Corporation
PDS-1575A
Printed in U.S.A. December, 1999
For most current data sheet and other product
information, visit www.burr-brown.com
Functionally, this unit consists of a transmit and a
receive section. The transmit section generates analog
signals from 2-bit digital symbol data and filters the
analog signals to create 2B1Q symbols. The on board
differential line driver provides a 13.5dBm signal to
the telephone line. The receive section filters and
digitizes the symbol data received on the telephone
line. This IC operates on a single 5V supply. The
digital circuitry in the unit can be connected to a
supply from 3.3V to 5V. It is housed in a SSOP-28
package.
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64kbps TO 1168kbps OPERATION
q
SCALABLE DATA RATE
q
250mW POWER DISSIPATION
q
+5V POWER (5V or 3.3V Digital)
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/ Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
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AFE1144
SPECIFICATIONS
Specifications are at 25
C, AV
DD
= +5V, DV
DD
= +3.3V, f
tx
= 584kHz (E1 rate), unless otherwise noted.
AFE1144E
PARAMETER
COMMENTS
MIN
TYP
MAX
UNITS
RECEIVE CHANNEL
Number of Inputs
Differential
2
Input Voltage Range
Balanced Differential
(1)
3.0
V
Common-Mode Voltage
AV
DD
/2
V
Input Impedance All Inputs
See Typical Performance Curves
Input Capacitance
10
pF
Input Gain Matching
Line Input vs Hybrid Input
2
%
Resolution
14
Bits
Programmable Gain
0dB, 3dB, 6dB, 9dB and 12dB
0
+12
dB
Settling Time for Gain Change
6
Symbol Periods
Gain + Offset Error
Tested at Each Gain Range
5
%FSR
(2)
Output Data Coding
Two's Complement
Output Symbol Rate, rxSYNC
(3)
32
584
kHz
Output Bit Rate, rxSYNC
(3)
64
1168
kbits/sec
TRANSMIT CHANNEL
Transmit Clock Rate, f
tx
Symbol Rate
32
584
kHz
T1 Transmit 3dB Point
T1E1 4/99 - 002R4 Draft Compliant
196
kHz
T1 Rate Power
(4, 5)
txBoost = 0
13
14
dBm
E1 Transmit 3dB Point
ETSI Compliant
292
kHz
E1 Transmit Power
(4, 5)
txBoost = 0
13
14
dBm
Common-Mode Voltage, V
CM
AV
DD
/2
V
Output Resistance
(6)
DC to 1MHz
1
TRANSCEIVER PERFORMANCE
Uncancelled Echo
(5)
rxGAIN = 0dB, Loopback Enabled
71
68.5
dB
rxGAIN = 0dB, Loopback Disabled
71
68.5
dB
rxGAIN = 3dB, Loopback Disabled
74
71
dB
rxGAIN = 6dB, Loopback Disabled
76
73.5
dB
rxGAIN = 9dB, Loopback Disabled
78
75.5
dB
rxGAIN = 12dB, Loopback Disabled
80
77.5
dB
DIGITAL INTERFACE
Logic Levels
V
IH
|I
IH
| < 10
A
DV
DD
1
DV
DD
+0.3
V
V
IL
|I
IL
| < 10
A
0.3
+0.8
V
V
OH
I
OH
= 20
A
DV
DD
0.5
V
V
OL
I
OL
= 20
A
+0.4
V
t
rx1
Interface
9
14
ns
POWER
Analog Power Supply Voltage
Specification
5
V
Analog Power Supply Voltage
Operating Range
4.75
5.25
V
Digital Power Supply Voltage
Specification
3.3
V
Digital Power Supply Voltage
Operating Range
3.15
5.25
V
Power Dissipation
(4, 5)
AV
DD
= 5V, DV
DD
= 3.3V,
250
mW
Power Dissipation
(4, 5)
AV
DD
= DV
DD
= 5V
300
mW
PSRR
55
dB
TEMPERATURE RANGE
Operating
(6)
40
+85
C
NOTES: (1) With a balanced differential signal, the positive input is 180
out of phase with the negative input, therefore the actual voltage swing about the common-
mode voltage on each pin is
1.5V to achieve a total input range of
3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol
rate with interpolated values. (4) With a pseudorandom equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (16.5dBm output from txLINEP
and txLINEN). (5) See the Discussion of Specifications section of this data sheet for more information. (6) Funtionality is guaranteed over temperature range.
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AFE1144
PIN CONFIGURATION
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
NC
NC
DV
DD
DGND
txbaudCLK
tx48xCLK
Data In
rxbaudCLK
rx48xCLK
Data Out
DV
DD
DGND
AV
DD
rxHYB
NC
AGND
txLINE+
AV
DD
txLINE
AGND
AV
DD
vrREFN
VCM
vrREFP
AGND
rxLINE+
rxLINE
rxHYB+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AFE1144
Analog Inputs: Current ..............................................
100mA, Momentary
10mA, Continuous
Voltage .................................. AGND 0.3V to AV
DD
+0.3V
Analog Outputs Short Circuit to Ground (+25
C) ..................... Continuous
AV
DD
to AGND ......................................................................... 0.3V to 6V
DV
DD
to DGND ......................................................................... 0.3V to 6V
Digital Input Voltage to DGND .................................. 0.3V to DV
DD
+0.3V
Digital Output Voltage to DGND ............................... 0.3V to DV
DD
+0.3V
AGND, DGND, Differential Voltage .................................................... 0.3V
Junction Temperature (T
J
) ............................................................. +150
C
Storage Temperature Range .......................................... 40
C to +125
C
Lead Temperature (soldering, 3s) .................................................. +260
C
Power Dissipation .......................................................................... 700mW
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE
SPECIFIED
DRAWING
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE
NUMBER
RANGE
MARKING
NUMBER
(1)
MEDIA
AFE1144
SSOP-28
324
40
C to +85
C
AFE1144E
AFE1144E
Rails
"
"
"
"
"
AFE1144E/1K
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of "AFE1144E/1K" will get a single 1000-piece Tape and Reel.
PACKAGE/ORDERING INFORMATION
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AFE1144
PIN #
TYPE
NAME
DESCRIPTION
1
No Connection
NC
2
No Connection
NC
3
Power
DV
DD
Digital Supply (+3.3 to +5V)
4
Ground
DGND
Digital Ground
5
Input
txbaudCLK
Transmit Baud Clock (584kHz for E1)
6
Input
tx48xCLK
Transmit Clock at 48x baud clock (28.032MHz for E1)
7
Input
Data In
Input Data Word
8
Input
rxbaudCLK
Receive baud clock (584kHz for E1)
9
Input
rx48xCLK
Receive clock at 48x baud clock (28.032MHz for E1)
10
Output
Data Out
Output Data Word
11
Power
DV
DD
Digital Supply (+3.3 to +5V)
12
Ground
DGND
Digital Ground
13
Power
AV
DD
Analog Supply (+5V)
14
Input
rxHYB
Negative input from hybrid network
15
Input
rxHYB+
Positive input from hybrid network
16
Input
rxLINE
Negative line input
17
Input
rxLINE+
Positive line input
18
Ground
AGND
Analog Ground
19
Output
vrREFP
Positive reference output
20
Output
VCM
Common-mode voltage (buffered)
21
Output
vrREFN
Negative reference output
22
Power
AVDD
Analog Supply (+5V)
23
Ground
AGND
Analog Ground
24
Output
txLINE
Negative line output
25
Power
AV
DD
Output buffer supply (+5V)
26
Output
txLINE+
Positive line output
27
Ground
AGND
Output buffer ground
28
No Connection
NC
PIN DESCRIPTIONS
BLOCK DIAGRAM
Pulse
Former
Filter
txbaudCLK
tx48xCLK
Data In
rxbaudCLK
rx48xCLK
Data Out
Output
Buffer
Voltage
Reference
Modulator
Transmit
Control
Receive
Control
Decimation
Filter
txLINE
txLINE+
REF
P
V
CM
REF
N
rxLINE+
rxLINE
rxHYB+
rxHYB
5
AFE1144
TYPICAL PERFORMANCE CURVES
At Output of HDSL Pulse Transformer
The curves shown below are measured at the line output of the HDSL transformer. Typical at 25
C, AV
DD
+ = +5V, DV
DD
+ = +3.3V, f
TX
= 1168kHz, unless otherwise specified.
CURVE 1. Upper Bound of Power Spectral Density Measured at Output of HDSL Transformer.
POWER SPECTRAL DENSITY LIMIT - T1 RATE
Frequency (kHz)
500
1000
1500
2000
2500
0
Power Spectral Density (dBm/Hz)
0
20
40
60
80
100
120
CURVE 2. Input Impedance of rxLINE and rxHYB.
100
200
150
100
50
0
300
500
INPUT IMPEDANCE vs BIT RATE
Input Impedance (k
)
Bit Rate (kbps)
700
900
1300
1100
T1 = 784kbps,
32k
E1 = 1168kbps,
21k
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