DC-to-DC
Voltage Converter
CLM7660
FEATURES
Converts +5V Logic Supply to
5 System
Wide Input Voltage Range . . . . . . . . . . . . . . 1.5V to 10V
Low Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . 500
A
Efficient Voltage Conversion . . . . . . . . . . . . . . . . . 99.9%
RS232 Negative Power Supply
Low Cost, Simple to Use
APPLICATIONS
A-to-D Converters
D-to-A Converters
Multiplexers
Operational Amplifiers
DESCRIPTION
Calogic CLM7660 DC-to-DC converter will generate a negative
voltage from a positive source. The CLM7660 generates -5V
in +5V digital systems and with two external capacitors, the device
will convert a 1.5V to 10V input signal to a -1.5V to -10V level.
Applications include analog-to-digital converters, digital-to-analog
converters, operational amplifiers and multiplexers. Many of these
systems require negative supply voltages. The CLM7660 allows
+5V digital logic systems to incorporate these analog components
without an additional main power source. Lower part count, less real
estate, ease of use are just a few of the benefits of the CLM7660.
ORDERING INFORMATION
Part
Package
Temperature
CLM7660CP
8 Pin DIP
-40
o
C to +85
o
C
CLM7660DY
8 Pin SOIC
-40
o
C to +85
o
C
CORPORATION
CALOGIC CORPORATION,
237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
PIN CONFIGURATION AND BLOCK DIAGRAM
1B-35
RC
OSCILLATOR
2
VOLTAGE-
LEVEL
TRANSLATOR
INTERNAL
VOLTAGE
REGULATOR
LOGIC
NETWORK
LV
OSC
GND
2
3
4
5
6
7
8
CAP
V
OU T
CAP
+
V
+
LOW
VOLTAGE (LV)
1K-17
NC
1
2
3
8
7
6
4
5
OSC
V
GND
+
V
OUT
NC = NO INTERNAL CONNECTION
CAP
+
CAP
CLM7660
ABSOLUTE MAXIMUM RATINGS
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10.5V
LV and OSC Inputs
Voltage (Note 1) . . . . . . . . . . . . . . . . . . . -0.3V to (V
+
+0.3V)
for V
+
<5.5V
(V
+
-5.5V) to (V
+
+0.3V)
for V
+
<5.5V
Current into LV (Note 1). . . . . . . . . . . . . . . 20
A for V
+
>3.5V
Output Short Duration (V
SUPPLY
5.5V) . . . . . . . . Continuous
Power Dissipation (Note 2)
Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375mW
Operating Temperature Range
D Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
Storage Temperature Range . . . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300
o
C
Static-sensitive device. Unused devices must be stored in conductive material.
Protect devices from static discharge and static fields. Stresses above those
listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at
these or any other conditions above those indicated in the operation sections of
the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CLM7660
CALOGIC CORPORATION,
237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
CORPORATION
ELECTRICAL CHARACTERISTICS V
+
= 5V, T
A
= +25
o
C, C
OSC
= 0, Test Circuit (Figure 1), unless otherwise indicated.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
TEST CONDITIONS
I
+
Supply Current
-
80
180
A
R
L
=
V
+
H1
Supply Voltage Range, High
3
-
6.5
V
0
o
C
T
A
+70
o
C, R
L
= 10k
, LV Open
3
-
5
V
-55
o
C
T
A
+125
o
C, 10k
, LV Open
V
+
L1
Supply Voltage Range, Low
(D
X
Out of Circuit)
1.5
-
3.5
V
Min
T
A
Max, R
L
= 10k
, LV to GND
V
+
H2
Supply Voltage Range, High
(D
X
In Circuit)
3
-
10
V
Min
T
A
Max, R
L
= 10k
, LV Open
V
+
L2
Supply Voltage Range, Low
(D
X
In Circuit)
1.5
-
3.5
V
Min
T
A
Max, R
L
= 10k
, LV to GND
R
OUT
Output Source Resistance
-
55
100
I
OUT
= 20mA, T
A
= 25
o
C
-
-
120
I
OUT
= 20mA, 0
o
C
T
A
+70
o
C (C Device)
-
-
300
V
+
= 2V, I
OUT
= 3mA, LV to GND
0
o
C
T
A
+70
o
C
f
OSC
Oscillator Frequency
-
10
-
kHz
PEF
Power Efficiency
95
98
-
%
R
L
= 5k
V
OUT EF
Voltage Conversion Efficiency
97
99.9
-
%
R
L
=
Z
OSC
Oscillator Impedance
-
1
-
M
V
+
= 2V
-
100
-
k
V
+
= 5V
NOTES:
1. Connecting any input terminal to voltages greater than C+ or less than GND may cause destructive latch-up. It is recommended that no inputs
from sources operating from external supplies be applied prior to "power up" of the CLM7660.
2. Derate linearly above 50
o
C by 5.5mW/
o
C.
CLM7660
CORPORATION
CIRCUIT DESCRIPTION
The CLM7660 is an excellent voltage doubler, the device has
all the characteristic with the exception of two inexpensive
10
F polarized electrolytic external capacitors. Figure 3
demonstrates the most effective means of using the device as
a voltage doubler. Capacitor C
1
is charged to a voltage, V+,
for the half cycle when switches S
1
and S
3
are closed. (Note
Switches S
2
and S
4
are open during this half cycle.) During
the second half of the operation, switches S
2
and S
4
are
closed, with S
1
and S
3
open, thereby shifting capacitor C
1
negatively by V+ volts. Charge is then transferred from C
1
to
C
2
, such that voltage on C
2
is exactly V+, asumming ideal
switches and no load on C
2
.
The four switches in Figure 3 are MOS power switches, S
1
is
a P-Channel device, S
2
, S
3
and S
4
are N-Channel devices.
The major challenge with this approach while integrating the
switches, the substrates of S
3
and S
4
must always remain
reversed-biased with respect to their sources, but not so
much as to degrade their ON-resistances. In addition, at
circuit start-up, and under short circuit conditions (V
OUT
=V
+
),
the output voltage must be sensed and the substrate bias
adjusted accordingly. Failure to accomplish this will result in
high power losses and probable device latch-up.
The above problem is eliminated in the CLM7660 by a logic
network which senses the output voltage (V
OUT
) together with
the level translators, and switches the substrates of S
3
and S
4
to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the CLM7660 is an integral
part of the anti-latch-up circuitry. Its inherent voltage drop can
degrade operation at low voltages. To improve low-voltage
operation, the LV pin should be connected to GND, disabling
the regulator. For supply voltages greater than 3.5V, the LV
terminal must be left open to ensure latch-up proof operation
and prevent device damage.
THEORETICAL POWER EFFICIENCY CONSIDERATIONS
In theory, a voltage multiplier can approach 100% efficiency if
certain conditions are met:
1. The drive circuitry consumes minimal power.
2. The output switches have extremely low ON-resistance and
virtually no offset.
3. The impedances of the pump and reservoir capacitors are
negligible at the pump frequency.
When larger values of C
1
and C
2
are used, the CLM7660
approaches the above conditions for negative voltage
multiplication.
Energy is lost only if the transfer of the charge
between capacitors if a change in voltage occurs. The energy
lost is defined by:
E=1/2C
1
(V
1
2-V
2
2)
During the pump and transfer cycles V
1
and V
2
are the
voltages on C
1
. If the impedances of C
1
and C
2
are high at
the pump frequency (see Figure 3), compared to the value of
R
L
, there will be a substantial difference in voltages V
1
and
V
2
. The most optimum selection would be to make C
2
as
large as possible to eliminate output voltage ripple, and to
utilize a large value for C
1
to achieve maximum efficiency of
operation.
OPERATIONAL RULES:
Never exceed maximum supply voltages.
Never connect LV terminal to GND for supply voltages over
3.5V.
Never short circuit the output to V
+
supply voltages above
5.5V for extended periods; however, transient conditions
including start-up are acceptable.
For polarized capacitors, the + terminal of C
1
must be
connected to pin 2 of the CLM7660 and the + terminal to of C
2
must be connected to GND.
For high-voltage, elevated temperature applications add a
diode D
X
(reference Figure 1). The 1N914 diode is an
appropriate choice.
CALOGIC CORPORATION,
237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
CLM7660
FIGURE 1. CLM7660 TEST CIRCUIT
L
I
S
I
1
2
3
8
6
4
5
CLM7660
1K-11
+
+
O
V
10
F
10
F
2
C
1
C
(+5)
L
R
X
D **
7
OSC
C
*
+
V
CALOGIC CORPORATION,
237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
CORPORATION
FIGURE 2. CHIP TOPOGRAPHY
DIE SIZE = 81.5 x 57.5 (mm)
1L-05
C+
GND
C-
V
OUT
LV
OSC
V8
FIGURE 3. IDEALIZED SWITCHED CAPACITOR
1K-12
C
1
GND
3
S
V
OUT
= V
IN
4
S
2
C
2
S
1
S
+
V
FIGURE 4. SIMPLE NEGATIVE CONVERTER
1
2
3
8
7
6
4
5
CLM7660
1K-05
+
+
V
+
OUT
V
X
D
10
F
10
F
2
C
1
C
*
FIGURE 5. PARALLELING DEVICES LOWERS OUTPUT IMPEDANCE
1
2
3
8
7
6
4
5
CLM7660
1
C
1K-06
+
V
1
2
3
8
7
6
4
5
CLM7660
1
C
+
2
C
L
R
"n"
"1"
X
D
X
D
NOTES:
* For large values of C
OSC
(>1000pf), the
values of C
1
and C
2
should be increased to 100
F.
** DX is required for supply voltages greater than 6.5V at
-55
o
T
A
+70
o
C. Refer to performance curves for
additional information.
*NOTES:
1. V
OUT
= -n V
+
for 1.5V
V
+
6.5V.
2. V
OUT
= -n (V
+
V
FDX
) for 6.5V
V
+
10V.
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