Preliminary Product Information

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright

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CS4392

24-Bit, 192 kHz Stereo DAC with Volume Control

Features

Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
114 dB Dynamic Range
100 dB THD+N
Up to 192kHz Sample Rates
Direct Stream Digital Mode
Low Clock Jitter Sensitivity
Single +5 V Power Supply
Selectable Digital Filters

Fast and Slow roll-off

Volume Control with Soft Ramp

1 dB Step Size
Zero Crossing Click-Free Transitions

Direct Interface with 5 V to 1.8 V Logic
ATAPI mixing functions
Pin compatible with the CS4391

Description

The CS4392 is a complete stereo digital-to-analog sys-
tem including digital interpolation, fifth-order delta-sigma
digital-to-analog conversion, digital de-emphasis, vol-
ume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera-
ture, and a high tolerance to clock jitter.

The CS4392 accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD audio data, has selectable digital
filters, and consumes very little power. These features
are ideal for DVD, SACD players, A/V receivers, CD and
set-top box systems. The CS4392 is pin and register
compatible with the CS4391, making easy performance
upgrades possible.

ORDERING INFORMATION

CS4392-KS

-10 to 70 °C

20-pin SOIC

CS4392-KZ

-10 to 70 °C

20-pin TSSOP

CDB4392

Evaluation Board

LRCK

SDATA

(SDA/CDIN)

MCLK

AMUTEC

AOUTA-

AOUTB-

SERIAL

PORT

INTERPOLATION

(CONTROL PORT)

DAC

EXTERNAL

ANALOG

FILTER

ANALOG

FILTER

MUTE CONTROL

FILTER

RST

SCLK

VOLUME

CONTROL

VOLUME

CONTROL

MIXER

(SCL/CCLK)

(AD0/CS)

AOUTA+

AOUTB+

CMOUT

REFERENCE

FILT+

BMUTEC

MODE SELECT

SEP `02

DS459PP2

CS4392

DS459PP2

TABLE OF CONTENTS

1. PIN DESCRIPTION - PCM DATA MODE .................................................................... 5

1.1 PIN DESCRIPTION - DSD mode ..................................................................... 6

2. TYPICAL CONNECTION DIAGRAMS ........................................................................ 7
3. APPLICATIONS ........................................................................................................... 9

3.1 Recommended Power-up Sequence for Hardware Mode ................................ 9
3.2 Recommended Power-up Sequence and Access to

Control Port Mode ............................................................................................. 9

3.3 Analog Output and Filtering .............................................................................. 9
3.4 Interpolation Filter ........................................................................................... 10
3.5 System Clocking ............................................................................................. 10
3.6 Digital Interface Format .................................................................................. 11
3.7 De-Emphasis .................................................................................................. 12
3.8 Oversampling Modes ...................................................................................... 12
3.9 Using DSD mode ............................................................................................ 13
3.10 Mute Control ................................................................................................. 13

4. CONTROL PORT INTERFACE ................................................................................. 14

4.0.1 MAP Auto Increment ............................................................................. 14
4.0.2 I2C Mode ............................................................................................... 14

I2C Write.................................................................................................... 14
I2C Read ................................................................................................... 15

4.0.3 SPI Mode ............................................................................................... 16

SPI Write.................................................................................................... 16

4.1 Memory Address Pointer (MAP) ...................................................................... 16

5. REGISTER QUICK REFERENCE ............................................................................. 17
6. REGISTER DESCRIPTION ........................................................................................ 18

6.1 Mode Control 1 - Address 01h ........................................................................ 18

6.1.1 Auto-Mute (Bit 7) ................................................................................... 18
6.1.2 Digital Interface Formats (Bits 6:4) ........................................................ 18
6.1.3 De-Emphasis Control (Bits 3:2) ............................................................. 19
6.1.4 Functional Mode (Bits 1:0) .................................................................... 19

6.2 Volume and Mixing Control (Address 02h) ..................................................... 20

6.2.1 Channel A Volume = Channel B Volume (Bit 7) .................................... 20

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to

http://www.cirrus.com/corporate/contacts/sales.cfm

IMPORTANT NOTICE

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product infor-
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mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-
marks or service marks of their respective owners.

CS4392

DS459PP2

6.2.2 Soft Ramp or Zero Cross Enable (Bits 6:5) ...........................................20
6.2.3 ATAPI Channel Mixing and Muting (Bits 4:0) .........................................20

6.3 Channel A Volume Control - Address 03h ......................................................22

6.4.1 Mute (Bit 7) ............................................................................................22
6.4.2 Volume Control (Bits 6:0) .......................................................................22

6.5 Mode Control 2 - Address 05h ........................................................................22

6.5.1 Invert Signal Polarity (Bits 7:6) ...............................................................22
6.5.2 Control Port Enable (Bit 5) .....................................................................23
6.5.3 Power Down (Bit 4) ................................................................................23
6.5.4 AMUTEC = BMUTEC (Bit 3) ..................................................................23
6.5.5 Freeze (Bit 2) .........................................................................................23
6.5.6 Master Clock Divide (Bit 1) ....................................................................23

6.6 Mode Control 3 - Address 06h ........................................................................23

6.6.1 Interpolation Filter Select (Bit 4) .............................................................23
6.6.2 Soft Volume Ramp-up after Reset (Bit 3) ..............................................24
6.6.3 Soft Ramp-down before Reset (Bit 2) ....................................................24

6.7 Chip ID - Register 07h .....................................................................................24

7. CHARACTERISTICS/SPECIFICATIONS ..................................................................25

ANALOG CHARACTERISTICS (CS4392-KS/KZ) ..................................................25
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER
RESPONSE ............................................................................................................26
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE .......................32
SWITCHING SPECIFICATIONS - DSD INTERFACE.............................................33
SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE....................34
SWITCHING CHARACTERISTICS - SPI CONTROL PORT ..................................35
DC ELECTRICAL CHARACTERISTICS .................................................................36
DIGITAL INPUT CHARACTERISTICS & SPECIFICATIONS .................................36
RECOMMENDED OPERATING SPECIFICATIONS ..............................................37
ABSOLUTE MAXIMUM RATINGS ..........................................................................37

8. PARAMETER DEFINITIONS ......................................................................................38
9. REFERENCES ............................................................................................................38
10. PACKAGE DIMENSIONS ........................................................................................39

LIST OF TABLES

Table 1. Clock Ratios .................................................................................................................... 10
Table 2. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies ......................... 10
Table 3. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies................... 10
Table 4. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies ................... 10
Table 5. Digital Interface Format, Stand-Alone Mode Options...................................................... 11
Table 5. De-Emphasis Select, Stand-Alone Mode........................................................................ 12
Table 6. Mode Selection, Stand-Alone Mode Options .................................................................. 12
Table 7. Direct Stream Digital (DSD), Stand-Alone Mode Options ............................................... 13
Table 8. Digital Interface Formats - PCM Modes .......................................................................... 18
Table 10. De-Emphasis Mode Selection...................................................................................... 19
Table 11. Functional Mode Selection............................................................................................ 19
Table 12. Soft Cross or Zero Cross Mode Selection.................................................................... 20
Table 13. ATAPI Decode .............................................................................................................. 21
Table 14. Digital Volume Control Example Settings ..................................................................... 22

CS4392

DS459PP2

LIST OF FIGURES

Figure 1. Typical Connection Diagram - PCM Mode ....................................................................... 7
Figure 2. Typical Connection Diagram - DSD Mode ....................................................................... 8
Figure 3. CS4392 Output Filter ....................................................................................................... 9
Figure 4. Format 0, Left Justified up to 24-Bit Data....................................................................... 11
Figure 5. Format 1, I2S up to 24-Bit Data ..................................................................................... 11
Figure 6. Format 2, Right Justified 16-Bit Data

Format 3, Right Justified 24-Bit Data
Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only)
Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)................ 11

Figure 7. De-Emphasis Curve ....................................................................................................... 12
Figure 8. Control Port Timing, I2C Mode....................................................................................... 15
Figure 9. Control Port Timing, SPI mode ...................................................................................... 16
Figure 10. De-Emphasis Curve ..................................................................................................... 19
Figure 11. ATAPI Block Diagram .................................................................................................. 21
Figure 12. Single Speed (fast) Stopband Rejection ...................................................................... 28
Figure 13. Single Speed (fast) Transition Band ............................................................................ 28
Figure 14. Single Speed (fast) Transition Band (detail) ................................................................ 28
Figure 15. Single Speed (fast) Passband Ripple .......................................................................... 28
Figure 16. Single Speed (slow) Stopband Rejection ..................................................................... 28
Figure 17. Single Speed (slow) Transition Band ........................................................................... 28
Figure 18. Single Speed (slow) Transition Band (detail) ............................................................... 29
Figure 19. Single Speed (slow) Passband Ripple ......................................................................... 29
Figure 20. Double Speed (fast) Stopband Rejection ..................................................................... 29
Figure 21. Double Speed (fast) Transition Band ........................................................................... 29
Figure 22. Double Speed (fast) Transition Band (detail) ............................................................... 29
Figure 23. Double Speed (fast) Passband Ripple ......................................................................... 29
Figure 24. Double Speed (slow) Stopband Rejection ................................................................... 30
Figure 25. Double Speed (slow) Transition Band.......................................................................... 30
Figure 26. Double Speed (slow) Transition Band (detail).............................................................. 30
Figure 27. Double Speed (slow) Passband Ripple........................................................................ 30
Figure 28. Quad Speed (fast) Stopband Rejection ....................................................................... 30
Figure 29. Quad Speed (fast) Transition Band.............................................................................. 30
Figure 30. Quad Speed (fast) Transition Band (detail).................................................................. 31
Figure 31. Quad Speed (fast) Passband Ripple............................................................................ 31
Figure 32. Quad Speed (slow) Stopband Rejection ...................................................................... 31
Figure 33. Quad Speed (slow) Transition Band ............................................................................ 31
Figure 34. Quad Speed (slow) Transition Band (detail) ................................................................ 31
Figure 35. Quad Speed (slow) Passband Ripple .......................................................................... 31
Figure 36. Serial Mode Input Timing ............................................................................................. 32
Figure 37. Direct Stream Digital - Serial Audio Input Timing ......................................................... 33
Figure 38. I2C Mode Control Port Timing...................................................................................... 34
Figure 39. SPI Control Port Timing ............................................................................................... 35

CS4392

DS459PP2

1. PIN DESCRIPTION - PCM DATA MODE

RST

Reset (Input) - Powers down device and resets all internal registers to their default settings.

Logic Power (Input) - Positive power for the digital input/output.

SDATA

Serial Audio Data (Input) - Input for two's complement serial audio data.

SCLK

Serial Clock (Input/Output) - Serial clock for the serial audio interface.

LRCK

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.

MCLK

Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

FILT+

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

CMOUT

Common Mode Voltage (Output) - Filter connection for internal quiescent voltage.

AMUTEC
BMUTEC

20
13

Mute Control (Output) - The Mute Control pin goes high during power-up initialization, reset, muting,
power-down or if the master clock to left/right clock frequency ratio is incorrect.

AOUTB-
AOUTB+
AOUTA+
AOUTA

14
15
18
19

Differential Analog Output (Outputs) - The full scale differential analog output level is specified in the
Analog Characteristics specification table.

AGND

Ground (Input)

Analog Power (Input) - Positive power for the analog section.

Control Port Mode Definitions

Mode Selection (Input) - This pins should be tied to GND level during control port mode.

SCL/CCLK

Serial Control Port Clock (Input) - Serial clock for the serial control port.

SDA/CDIN

Serial Control Data (Input/Output) - SDA is a data I/O line in I

C mode. CDIN is the input data line for

the control port interface in SPI mode.

AD0/CS

Address Bit 0 (I

C) / Control Port Chip Select (SPI) (Input/Output) - AD0 is a chip address pin in I

mode; CS is the chip select signal for SPI format.

Stand-Alone Mode Definitions

M3
M2
M1
M0

7
8
9

Mode Selection (Input) - Determines the operational mode of the device.

RST

AMUTEC

AOUTA-

SDATA

AOUTA+

SCLK

LRCK

AGND

MCLK

AOUTB+

AOUTB-

(SCL/CCLK) M2

BMUTEC

(SDA/CDIN) M1

CMOUT

(AD0/CS) M0

FILT+

CS4392

DS459PP2

3. APPLICATIONS

3.1

Recommended Power-up Sequence for Hardware Mode

1) Hold

RST

low until the power supplies, master, and left/right clocks are stable.

2) Bring

RST

high. After 10ms the device will begin normal operation.

3.2

Recommended Power-up Sequence and Access to Control Port Mode

1) Hold

RST

low until the power supply, master, and left/right clocks are stable. In this state, the control

port is reset to its default settings and FILT+ will remain low.

2) Bring

RST

high. The device will remain in a low power state with FILT+ low and the control port is

accessible.

3) Write 30h to register 05h within 10 ms cycles following the release of RST. If after 10ms the control

port has not been initiated with this command, the device will enter stand-alone mode. The CPEN bit,
however, may be written at any time after 10ms. It is recommended to write CPEN before 10ms in or-
der to reduce the possibility of any extraneous click or pop noise from occurring.

4) The desired register settings can be loaded while keeping the PDN bit set to 1.

5) Set the PDN bit to 0. This will initiate the power-up sequence which requires approximately 10 µS.

3.3

Analog Output and Filtering

The application note "Design Notes for a 2-Pole Filter with Differential Input" discusses the second-order
Butterworth filter and differential to single-ended converter as seen in Figure 3. An alternate configuration
can be seen on the CDB4392. This alternate filter configuration accounts for the differing AC loads on the
+ and - differential output pins which are normally present in a circuit like Figure 3. It also shows an AC
coupling configuration which reduces the number of required AC coupling capacitors to 2 caps per chan-
nel. The circuit in figure 3 may also be DC coupled, however the filter on the CDB4392 must be
AC coupled. The CS4392 is a linear phase design and does not include phase or amplitude compensation
for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the
external analog circuitry.

3.01k

1.58k

3.01k

10 uF

560

1.58k

10 uF

3.32k

R17

3.32k

10 uF

680 pF

C10

680 pF

2700 pF

47k

Aout -

Aout +

Analog_Out

Figure 3. CS4392 Output Filter

CS4392

DS459PP2

3.4

Interpolation Filter

To accommodate the increasingly complex requirements of digital audio systems, the CS4392 incorpo-
rates selectable interpolation filters for each mode of operation. A fast and a slow roll-off filter is available
in each of Single, Double, and Quad Speed modes. These filters have been designed to accommodate a
variety of musical tastes and styles. Bit 5 of the Mode Control 3 register (06h) is used to select which filter
is used. Filter specifications can be found in Section 8, and filter response plots can be found in Figures 12
to 35.

In stand-alone mode, only the fast roll-off filter is available.

3.5

System Clocking

The required MCLK to LRCK and suggested SCLK to LRCK ratios are outlined in table 1. MCLK can be
at any phase in regards to LRCK and SCLK. SCLK, LRCK and SDATA must meet the phase and timing
relationships outlined in Section 7. Some common MCLK frequencies have been outlined in tables 2 to 4.

*Note:These clocking ratios are only available in Control Port Mode when the MCLK Divide bit is enabled.

MCLK/LRCK

SCLK/LRCK

LRCK

Single Speed

256, 384, 512, 768, 1024*

32, 48, 64, 96, 128

Double Speed

128, 192, 256, 384, 512*

32, 48, 64

Quad Speed

32 (16 bits only)

32, 48

128, 256*

32, 64

192

32, 48, 64, 96

Table 1. Clock Ratios

Sample Rate

(kHz)

MCLK (MHz)

See Note

256x

384x

512x

768x

1024x*

8.1920

12.2880

16.3840

24.5760

32.7680

44.1

11.2896

16.9344

22.5792

33.8688

45.1584

12.2880

18.4320

24.5760

36.8640

49.1520

Table 2. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies

Sample Rate

(kHz)

MCLK (MHz)

See Note

128x

192x

256x

384x

512x*

8.1920

12.2880

16.3840

24.5760

32.7680

88.2

11.2896

16.9344

22.5792

33.8688

45.1584

12.2880

18.4320

24.5760

36.8640

49.1520

Table 3. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies

Sample Rate

(kHz)

MCLK (MHz)

See Note

64x

96x

128x

192x

256x*

176.4

11.2896

16.9344

22.5792

33.8688

45.1584

192

12.2880

18.4320

24.5760

36.8640

49.1520

Table 4. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies

CS4392

DS459PP2

3.6

Digital Interface Format

The device will accept audio samples in several digital interface formats as illustrated in Tables 5 and 8.
The desired format is selected via the M0 and M1 pins for stand alone mode, and through the DIF2:0 bits
in the control port. For an illustration of the required relationship between the Left/Right Clock, Serial
Clock and Serial Audio Data, see Figures 4-6.

DESCRIPTION

FORMAT

FIGURE

Left Justified, up to 24-bit data

S, up to 24-bit data

Right Justified, 16-bit Data

Right Justified, 24-bit Data

Table 5. Digital Interface Format, Stand-Alone Mode Options

Figure 4. Format 0, Left Justified up to 24-Bit Data

L R C K

S C L K

L eft C ha n n el

R igh t C ha n n el

S D A T A

+3 +2 +1 LS B

+5 +4

M SB -1 -2 -3 -4 -5

+3 +2 +1 LSB

+5 +4

M SB -1 -2 -3 -4

Figure 5. Format 1, I

S up to 24-Bit Data

L R C K

S C L K

L e ft C h a nn e l

R ig h t C ha n n el

S D A T A

+3 +2 +1 LSB

+5 +4

MS B -1 -2 -3 -4 -5

+3 +2 +1 L SB

+5 +4

MS B -1 -2 -3 -4

LR CK

S CLK

L e ft C h a nne l

S D A TA

+ 5 + 4 + 3 +2 + 1 LSB

MSB -1 -2 -3 -4 -5

32 c lo c k s

R igh t C h a n ne l

LSB

+ 5 + 4 +3 + 2 +1 LSB

MSB -1

-2 -3 -4 -5

+ 6

-6

+ 6

-6

Figure 6. Format 2, Right Justified 16-Bit Data

Format 3, Right Justified 24-Bit Data

Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only)
Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)

CS4392

DS459PP2

3.7

De-Emphasis

The device includes on-chip digital de-emphasis. Figure 7 shows the de-emphasis curve for F

equal to

44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sam-
ple rate, F

. Please see Table 5 for the desired de-emphasis control for Stand-alone mode and Table 10 for

control port mode.

The de-emphasis feature is included to accommodate audio recordings that utilize 50/15

µS pre-emphasis

equalization as a means of noise reduction.
De-emphasis is only available in Single Speed Mode.

3.8

Oversampling Modes

The CS4392 operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the M3 and M2 pins in Stand-Alone mode or the FM bits in Control Port mode. Single-
Speed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed
mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed mode
supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x

DESCRIPTION

Single-Speed without De-Emphasis (4 to 50 kHz sample rates)

Single-Speed with 44.1kHz De-Emphasis

Double-Speed (50 to 100 kHz sample rates)

Quad-Speed (100 to 200 kHz sample rates)

Table 6. Mode Selection, Stand-Alone Mode Options

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

3.183 kHz

10.61 kHz

Figure 7. De-Emphasis Curve

(DEM)

DESCRIPTION

FIGURE

No De-Emphasis

De-Emphasis Enabled

Table 5. De-Emphasis Select, Stand-Alone Mode

CS4392

DS459PP2

3.9

Using DSD mode

In stand-alone mode, DSD operation is selected by holding DSD_EN(LRCK) high and applying the DSD
data and clocks to the appropriate pins. The M2:0 pins set the expected DSD rate and MCLK ratio.

In control-port mode the FM bits set the device into DSD mode (DSD_EN pin is not required to be held
high). The DIF register then controls the expected DSD rate and MCLK ratio.

3.10

Mute Control

The Mute Control pins go high during power-up initialization, reset, or if the Master Clock to Left Right
Clock ratio is incorrect. These pins will also go high following the reception of 8192 consecutive audio
samples of static 0 or -1 on both the left and right channels. A single sample of non-zero data on either
channel will cause the Mute Control pins to go low. These pins are intended to be used as control for an
external mute circuit in order to add off-chip mute capability.

Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute

minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system de-
signer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute cir-
cuit. See the CDB4392 data sheet for a suggested mute circuit.

DSD_Mode

DESCRIPTION

64x oversampled DSD data with a 4x MCLK to DSD data rate

64x oversampled DSD data with a 6x MCLK to DSD data rate

64x oversampled DSD data with a 8x MCLK to DSD data rate

64x oversampled DSD data with a 12x MCLK to DSD data rate

128x oversampled DSD data with a 2x MCLK to DSD data rate

128x oversampled DSD data with a 3x MCLK to DSD data rate

128x oversampled DSD data with a 4x MCLK to DSD data rate

128x oversampled DSD data with a 6x MCLK to DSD data rate

Table 7. Direct Stream Digital (DSD), Stand-Alone Mode Options

CS4392

DS459PP2

4. CONTROL PORT INTERFACE

The control port is used to load all the internal register settings (see section 6). The operation of the control
port may be completely asynchronous with the audio sample rate. However, to avoid potential interference
problems, the control port pins should remain static if no operation is required.

The control port operates in one of two modes: I

or SPI.

Notes: MCLK must be applied during all I

C communication.

4.0.1

MAP Auto Increment

The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit
(also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I

C writes

or reads, and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written,
allowing block reads or writes of successive registers.

4.0.2

C Mode

In the I

C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by

the serial control port clock, SCL (see Figure 8 for the clock to data relationship). There is no CS
pin. Pin AD0 enables the user to alter the chip address (001000[AD0][R/W]) and should be tied to
VL or AGND as required, before powering up the device. If the device ever detects a high to low
transition on the AD0/CS pin after power-up, SPI mode will be selected.

4.0.2a

C Write

To write to the device, follow the procedure below while adhering to the control port
Switching Specifications in section 7.

1) Initiate a START condition to the I

C bus followed by the address byte. The upper 6 bits

must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must
be 0. The eighth bit of the address byte is the R/W bit.

2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer,
MAP. This byte points to the register to be written.

3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register
pointed to by the MAP.

4) If the INCR bit (see section 4.0.1) is set to 1, repeat the previous step until all the desired
registers are written, then initiate a STOP condition to the bus.

5) If the INCR bit is set to 0 and further I

C writes to other registers are desired, it is nec-

essary to initiate a repeated START condition and follow the procedure detailed from step
1. If no further writes to other registers are desired, initiate a STOP condition to the bus.

CS4392

DS459PP2

4.0.2b

C Read

To read from the device, follow the procedure below while adhering to the control port
Switching Specifications.

1) Initiate a START condition to the I

C bus followed by the address byte. The upper 6 bits

must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must
be 1. The eighth bit of the address byte is the R/W bit.

2) After transmitting an acknowledge (ACK), the device will then transmit the contents of
the register pointed to by the MAP. The MAP register will contain the address of the last
register written to the MAP, or the default address (see section 4.1) if an I

C read is the first

operation performed on the device.

3) Once the device has transmitted the contents of the register pointed to by the MAP, issue
an ACK.

4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive
registers. Continue providing a clock and issue an ACK after each byte until all the desired
registers are read, then initiate a STOP condition to the bus.

5) If the INCR bit is set to 0 and further I

C reads from other registers are desired, it is nec-

essary to initiate a STOP condition and follow the procedure detailed from steps 1 and 2
from the I

C Write instructions followed by step 1 of the I

C Read section. If no further

reads from other registers are desired, initiate a STOP condition to the bus.

S D A

S C L

001 00 0

A D D R
A D 0

R /W

S ta rt

A C K

D A T A
1 -8

A C K

D A TA
1-8

A C K

Stop

N o te : If o p e ra tio n is a w rite , th is b yte co n ta in s th e M e m o ry A d d re ss P o in te r, M A P .

N o te 1

Figure 8. Control Port Timing, I

C Mode

CS4392

DS459PP2

4.0.3

SPI Mode

In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock,
CCLK (see Figure 9 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip
select signal and is used to control SPI writes to the control port. When the device detects a high to
low transition on the AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs
and data is clocked in on the rising edge of CCLK.

4.0.3a

SPI Write

To write to the device, follow the procedure below while adhering to the control port
Switching Specifications in section 7.

1) Bring CS low.

2) The address byte on the CDIN pin must then be 00100000.

3) Write to the memory address pointer, MAP. This byte points to the register to be written.

4) Write the desired data to the register pointed to by the MAP.

5) If the INCR bit (see section 4.0.1) is set to 1, repeat the previous step until all the desired
registers are written, then bring CS high.

6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is nec-
essary to bring CS high, and follow the procedure detailed from step 1. If no further writes
to other registers are desired, bring CS high.

4.1

Memory Address Pointer (MAP)

00000000

M A P

MSB

LS B

DATA

b yte 1

b y te n

R/W

M A P = M e m ory A d dre s s P o in te r

ADDRESS

C H IP

C D IN

C C LK

00 10 00 0

Figure 9. Control Port Timing, SPI mode

4.1.1

INCR (AUTO MAP INCREMENT ENABLE)

Default = `0'
0 - Disabled,

the MAP will stay constant for successive writes

1 - Enabled,

the MAP will auto increment after each byte is written, allowing block reads or

writes of successive registers

4.1.2

MAP3-0 (MEMORY ADDRESS POINTER)

Default = `0000'

INCR

Reserved

MAP3

MAP2

MAP1

MAP0

CS4392

DS459PP2

REGISTER DESCRIPTION

** All registers are read/write in Two-Wire mode and write only in SPI mode, unless otherwise noted**

6.1

Mode Control 1 - Address 01h

6.1.1

Auto-Mute (Bit 7)

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and
muting is done independently for each channel. (However, Auto-Mute detection and muting can be-
come dependent on either channel if the Mute A = B function is enabled.) The common mode on the
output will be retained and the Mute Control pin for that channel will go active during the mute period.
The muting function is effected, similar to volume control changes, by the Soft and Zero Cross bits in
the Volume and Mixing Control register.

6.1.2

Digital Interface Formats (Bits 6:4)

Function:

PCM Mode - The required relationship between the Left/Right clock, serial clock and serial data is
defined by the Digital Interface Format and the options are detailed in Table 8 and Figures 4-6.

AMUTE

DIF2

DIF1

DIF0

DEM1

DEM0

FM1

FM0

DIF2

DIF1

DIFO

DESCRIPTION

Format

Figure

Left Justified, up to 24-bit data (default)

S, up to 24-bit data

Right Justified, 16-bit Data

Right Justified, 24-bit Data

Right Justified, 20-bit Data

Right Justified, 18-bit Data

Reserved

Table 8. Digital Interface Formats - PCM Modes

CS4392

DS459PP2

DSD Mode - The relationship between the oversampling ratio of the DSD audio data and the required
Master clock to DSD data rate is defined by the Digital interface Format pins. Note that the Functional
Mode registers must be set to DSD Mode. See 9 for register options.

6.1.3

De-Emphasis Control (Bits 3:2)

Function:

Implementation of the standard 15

µs/50 µs digital de-emphasis filter response, Figure 7, requires re-

configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample
rates. NOTE: De-emphasis is available only in Single-Speed Mode. See 10 below.

6.1.4

Functional Mode (Bits 1:0)

Function:

Selects the required range of input sample rates or DSD Mode. See Table 11.

DIF2

DIF1

DIFO

DESCRIPTION

64x oversampled DSD data with a 4x MCLK to DSD data rate (default)

64x oversampled DSD data with a 6x MCLK to DSD data rate

64x oversampled DSD data with a 8x MCLK to DSD data rate

64x oversampled DSD data with a 12x MCLK to DSD data rate

128x oversampled DSD data with a 2x MCLK to DSD data rate

128x oversampled DSD data with a 3x MCLK to DSD data rate

128x oversampled DSD data with a 4x MCLK to DSD data rate

128x oversampled DSD data with a 6x MCLK to DSD data rate

Table 9. Digital Interface Formats - DSD Mode

DEM1

DEMO

DESCRIPTION

Disabled (default)

44.1 kHz de-emphasis

48 kHz de-emphasis

32 kHz de-emphasis

Table 10. De-Emphasis Mode Selection

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

3.183 kHz

10.61 kHz

Figure 10. De-Emphasis Curve

FM1

FM0

MODE

Single-Speed Mode: 4 to 50 kHz sample rates
(default)

Double-Speed Mode: 50 to 100 kHz sample rates

Quad-Speed Mode: 100 to 200 kHz sample rates

Direct Stream Digital Mode

Table 11. Functional Mode Selection

CS4392

DS459PP2

6.2

Volume and Mixing Control (Address 02h)

6.2.1

Channel A Volume = Channel B Volume (Bit 7)

Function:

The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Vol-
ume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are de-
termined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function
is enabled.

6.2.2

Soft Ramp or Zero Cross Enable (Bits 6:5)

Function:

Soft Ramp Enable

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock
periods.

Zero Cross Enable

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel.

Soft Ramp and Zero Cross Enable

Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes
or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel. See Table 12

6.2.3

ATAPI Channel Mixing and Muting (Bits 4:0)

Function:

The CS4392 implements the channel mixing functions of the ATAPI CD-ROM specification. See
Table 13 on page 21

A = B

Soft

Zero Cross

ATAPI4

ATAPI3

ATAPI2

ATAPI1

ATAPI0

SOFT

ZERO

Mode

Changes to affect immediately

Zero Cross enabled

Soft Ramp enabled (default)

Soft Ramp and Zero Cross enabled

Table 12. Soft Cross or Zero Cross Mode Selection

CS4392

DS459PP2

6.3

Channel A Volume Control - Address 03h

See 4.4 Channel B Volume Control - Address 04h

6.4

CHANNEL B VOLUME CONTROL - ADDRESS 04H

6.4.1

Mute (Bit 7)

Function:

The Digital-to-Analog converter output will mute when enabled. The common mode voltage on the
output will be retained. The muting function is effected, similiar to attenuation changes, by the Soft
and Zero Cross bits in the Volume and Mixing Control register. The MUTEC pin for that channel will
go active during the mute period if the Mute function is enabled. Both the AMUTEC and BMUTEC
will go active if either MUTE register is enabled and the MUTEC A = B bit (register 5) is enabled.

6.4.2

Volume Control (Bits 6:0)

Function:

The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -127 dB.

Volume settings are decoded as shown in Table 14. The volume changes are implemented as dictated

by the Soft and Zero Cross bits in the Volume and Mixing Control register (see section 6.2.2).

6.5

Mode Control 2 - Address 05h

6.5.1

Invert Signal Polarity (Bits 7:6)

Function:

When set to 1, this bit inverts the signal polarity for the appropriate channel. This is useful if a board
layout error has occurred, or an other situations where a 180 degree phase shift is desirable. Default
is 0.

MUTE

VOL6

VOL5

VOL4

VOL3

VOL2

VOL1

VOL0

Binary Code

Decimal Value

Volume Setting

0000000

0 dB

0010100

-20 dB

0101000

-40 dB

0111100

-60 dB

1011010

-90 dB

Table 14. Digital Volume Control Example Settings

INVERT_A

INVERT_B

CPEN

PDN

MUTEC A = B

FREEZE

MCLKDIV2

Reserved

CS4392

DS459PP2

6.5.2

Control Port Enable (Bit 5)

Function:

This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode
can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by
the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean power-
up, the user should write 30h to register 5 within 10 ms following the release of Reset.

6.5.3

Power Down (Bit 4)

Function:

The device will enter a low-power state whenever this function is activated (set to 1). The power-down
bit defaults to `enabled' (1) on power-up and must be disabled before normal operation will begin. The
contents of the control registers are retained when the device is in power-down.

6.5.4

AMUTEC = BMUTEC (Bit 3)

Function:

When this function is enabled, the individual controls for AMUTEC and BMUTEC are internally con-
nected through a AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC
pins will go active only when the requirements for both AMUTEC and BMUTEC are valid.

6.5.5

Freeze (Bit 2)

Function:

This function allows modifications to the control port registers without the changes taking effect until
Freeze is disabled. To make multiple changes in the Control port registers take effect simultaneously,
set the Freeze Bit, make all register changes, then Disable the Freeze bit.

6.5.6

Master Clock Divide (Bit 1)

Function:

This function allows the user to select an internal divide by 2 of the Master Clock. This selection is
required to access the higher Master Clock rates as shown in Tables 2 through 4 on page 10.

6.6

Mode Control 3 - Address 06h

6.6.1

Interpolation Filter Select (Bit 4)

Function:

This Function allows the user to select whether the Interpolation Filter has a fast (set to 0 - default) or
slow (set to 1) roll off. The - 3dB corner is approximately the same for both filters, but the slope of
the roll of is greater for the `fast' roll off filter.

Reserved

FILT_SEL

RMP_UP

RMP_DN

Reserved

CS4392

DS459PP2

6.6.2

Soft Volume Ramp-up after Reset (Bit 3)

Function:

This function allows the user to control whether a soft ramp up in volume is applied when reset is re-
leased either by the reset pin or internal to the chip. The modes are as follows:

0 - An instantaneous change is made from max attenuation to the control port volume setting on re-
lease of reset (default setting).
1 - Volume is ramped up using the soft-ramp settings in Bits 6:5 of register 02h (see 6.2.2) from max
attenuation to the control port volume setting on release of reset.

6.6.3

Soft Ramp-down before Reset (Bit 2)

Function:

This function allows the user to control if a soft ramp-down in volume is applied before a known reset
condition. The modes are as follows:

0 - An instantaneous change is made from the control port volume setting to max attenuation when
chip resets (default setting).
1 - Volume is ramped down using the soft-ramp settings in Bits 6:5 of register 02h (see 6.2.2) from
the control port volume setting to max attenuation when chip resets.

6.7

Chip ID - Register 07h

Function:

This register is Read-Only. Bits 7 through 4 are the part number ID which is 1000b (8h) and the re-
maining Bits (3 through 0) are for the chip revision.

PART3

PART2

PART1

PART0

REV3

REV2

REV1

REV0

CS4392

DS459PP2

7. CHARACTERISTICS/SPECIFICATIONS

ANALOG CHARACTERISTICS (CS4392-KS/KZ)

((Test conditions (unless otherwise speci-

fied): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load
R

= 3k

, C

= 10 pF. Typical performance characteristics are derived from measurements taken at T

= 25

°C,

VL = VA = 5.0V. Min/Max performance characteristics are guaranteed over the specified operating temperature
and voltages.)

Notes: 1. One-half LSB of Triangular PDF dither is added to data.

2. V

is tested under load R

but does not include attenuation due to Z

OUT

Parameter

VA = 5.0V

Symbol

Min

Typ

Max

Unit

Dynamic Performance for All Speed Modes and DSD

Dynamic Range

(Note 1)

unweighted

A-Weighted

105
108

111
114

-
-

dB
dB

Total Harmonic Distortion + Noise

(Note 1)

0 dB

-20 dB
-60 dB

THD+N

-
-
-

-100

-91
-51

-94

-45

dB
dB
dB

Idle Channel Noise / Signal-to-Noise Ratio

114

Interchannel Isolation

(1 kHz)

100

DC Accuracy

Interchannel Gain Mismatch

ICGM

0.1

Gain Drift

100

ppm/°C

Analog Output Characteristics and Specifications

Full Scale Differential Output Voltage

0.95xVA

0.99xVA

1.05xVA

Vpp

Output Resistance

(Note 2)

out

100

Minimum AC-Load Resistance

Maximum Load Capacitance

100

CS4392

DS459PP2

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

(The

filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be
referenced to the desired sample rate by multiplying the given characteristic by Fs.)

Parameter

Fast Roll-Off

Unit

Min

Typ

Max

Single-Speed Mode - (4 kHz to 50 kHz sample rates)

Passband

to -0.01 dB corner

to -3 dB corner

0
0

-
-

0.454
0.499

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-0.01

+0.01

StopBand

0.547

StopBand Attenuation

(Note 4)

Group Delay

12/Fs

Passband Group Delay Deviation

0 - 20 kHz

±0.41/Fs

De-emphasis Error (Relative to 1kHz)

Fs = 32 kHz

(Note 5)

Fs = 44.1 kHz

Fs = 48 kHz

-
-
-

±0.23
±0.14
±0.09

dB
dB
dB

Double-Speed Mode - (50 kHz to 100 kHz sample rates)

Passband

to -0.01 dB corner

to -3 dB corner

0
0

-
-

0.430
0.499

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-0.01

0.01

StopBand

0.583

StopBand Attenuation

(Note 4)

Group Delay

4.6/Fs

Passband Group Delay Deviation

0 - 20 kHz

±0.03/Fs

Quad Speed Mode - (100 kHz to 200 kHz)

Passband

to -0.01 dB corner

to -3 dB corner

0
0

-
-

0.105
0.490

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-0.01

0.01

StopBand

0.635

StopBand Attenuation

(Note 4)

Group Delay

4.7/Fs

Passband Group Delay Deviation

0 - 20 kHz

±0.01/Fs

DSD Mode

Passband

to -0.1 dB corner

to -3 dB corner

0
0

-
-

120

kHz
kHz

Frequency Response 10 Hz to 20 kHz

-.01

0.1

CS4392

DS459PP2

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

(Cont.)

Notes: 3. Slow Roll-Off interpolation filter is only available in control port mode.

4. For Single and Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.

For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.

5. De-emphasis is only available in Single Speed Mode; The 44.1kHz De-emphasis filter is the only filter

available in Stand-Alone Mode.

Parameter

Slow Roll-Off

(Note 3)

Unit

Min

Typ

Max

Single-Speed Mode - (4 kHz to 50 kHz sample rates)

Passband

to -0.01 dB corner

to -3 dB corner

0
0

-
-

0.417
0.499

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-0.01

+0.01

StopBand

0.583

StopBand Attenuation

(Note 4)

Group Delay

6.5/Fs

Passband Group Delay Deviation

0 - 20 kHz

±0.14/Fs

De-emphasis Error (Relative to 1kHz)

Fs = 32 kHz

(Note 5)

Fs = 44.1 kHz

Fs = 48 kHz

-
-
-

±0.23
±0.14
±0.09

dB
dB
dB

Double-Speed Mode - (50 kHz to 100 kHz sample rates)

Passband

to -0.01 dB corner

to -3 dB corner

0
0

-
-

0.296
0.499

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-0.01

0.01

StopBand

0.792

StopBand Attenuation

(Note 4)

Group Delay

3.9/Fs

Passband Group Delay Deviation

0 - 20 kHz

±0.01/Fs

Quad Speed Mode - (100 kHz to 200 kHz)

Passband

to -0.01 dB corner

to -3 dB corner

0
0

-
-

0.104
0.481

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-0.01

0.01

StopBand

0.868

StopBand Attenuation

(Note 4)

Group Delay

4.2/Fs

Passband Group Delay Deviation

0 - 20 kHz

±0.01/Fs

DSD Mode

Passband

to -0.1 dB corner

to -3 dB corner

0
0

-
-

120

kHz
kHz

Frequency Response 10 Hz to 20 kHz

-.01

0.1

CS4392

DS459PP2

DC ELECTRICAL CHARACTERISTICS

(AGND = 0V; all voltages with respect to AGND.)

Notes: 10. Normal operation is defined as RST = HI with a 997 Hz, 0dBFS input sampled at F

= 48kHz, and open

outputs, unless otherwise stated.

11. Power-Down Mode is defined as RST = LO with all clocks and data lines held static.

12. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 1 and 2.

DIGITAL INPUT CHARACTERISTICS & SPECIFICATIONS

(AGND = 0V; all voltages

with respect to AGND.)

THERMAL CHARACTERISTICS AND SPECIFICATIONS

Parameter

Symbol

Min

Typ

Max

Units

Normal Operation

(Note 10)

Power Supply Current

All Supplies=5.0V

+ I

Power Dissipation

130

150

Power-Down Mode

(Note 11)

Power Supply Current

All Supplies=5.0V

+ I

300

µA

Power Dissipation

1.5

All Modes of Operation

Power Supply Rejection Ratio

(Note 12)

(1 kHz)

(60 Hz)

PSRR

-
-

60
40

-
-

dB
dB

Common Mode Voltage

Output Impedance
Maximum allowable DC current source/sink

CMOUT

-
-
-

0.48·VA

250

0.001

-
-
-

Filt+ Nominal Voltage

Output Impedance
Maximum allowable DC current source/sink

-
-
-

250

0.001

-
-
-

MUTEC Low-Level Output Voltage

MUTEC High-Level Output Voltage

Maximum MUTEC Drive Current

Parameters

Symbol

Min

Typ

Max

Units

Input Leakage Current

±10

µA

Input Capacitance

High-Level Input Voltage

70%

Low-Level Input Voltage

20%

Parameters

Symbol

Min

Typ

Max

Units

Package Thermal Resistance

CS4392-KS

CS4392-KZ

-
-

68
72

-
-

°C/Watt
°C/Watt

Ambient Operating Temperature

(Power Applied)

-10

+70

°C

CS4392

DS459PP2

8. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
effect the measurement. This measurement technique has been accepted by the Audio Engineering So-
ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

9. REFERENCES

1. CDB4392 Evaluation Board Datasheet
2. "The I

C-Bus Specification: Version 2.1" Philips Semiconductors, January 2000.

http://www.semiconductors.philips.com

CS4392

DS459PP2

10. PACKAGE DIMENSIONS

Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.

2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not
reduce dimension "b" by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

INCHES

MILLIMETERS

NOT

DIM

MIN

NOM

MAX

MIN

NOM

MAX

0.043

1.10

0.002

0.004

0.006

0.05

0.15

0.03346

0.0354

0.037

0.85

0.90

0.95

0.00748

0.0096

0.012

0.19

0.245

0.30

2,3

0.252

0.256

0.259

6.40

6.50

6.60

0.248

0.2519

0.256

6.30

6.40

6.50

0.169

0.1732

0.177

4.30

4.40

4.50

0.026

0.65

0.020

0.024

0.028

0.50

0.60

0.70

0°

4°

8°

0°

4°

8°

JEDEC #: MO-153

Controlling Dimension is Millimeters.

20L TSSOP (4.4 mm BODY) PACKAGE DRAWING

1 2 3

SEATING

PLANE

SIDE VIEW

END VIEW

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