ChipFind - документация

Электронный компонент: DS1258AB

Скачать:  PDF   ZIP
www.docs.chipfind.ru
background image
1 of 8
033104




FEATURES
10-Year Minimum Data Retention in the
Absence of External Power
Data is Automatically Protected During a
Power Loss
Separate Upper Byte and Lower Byte Chip-
Select Inputs
Unlimited Write Cycles
Low-Power CMOS
Read and Write Access Times as Fast as 70ns
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
Full 10% Operating Range (DS1258Y)
Optional 5% Operating Range (DS1258AB)
Optional Industrial Temperature Range of
-40
C to +85C, Designated IND

PIN ASSIGNMENT
























PIN DESCRIPTION
A0 to A16
- Address Inputs
DQ0 to DQ15
- Data In/Data Out
CEU
- Chip Enable Upper Byte
CEL
- Chip Enable Lower Byte
WE
- Write Enable
OE
- Output Enable
V
CC
-
Power
(+5V)
GND
-
Ground

DESCRIPTION
The DS1258 128k x 16 nonvolatile (NV) SRAMs are 2,097,152-bit fully static, NV SRAMs, organized as
131,072 words by 16 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry that constantly monitors V
CC
for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. DIP-package DS1258 devices can be used in place of solutions that build NV
128k x 16 memory by utilizing a variety of discrete components. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
DS1258Y/AB
128k x 16 Nonvolatile SRAM
www.maxim-ic.com
13
1
2
3
4
5
6
7
8
9
10
11
12
14
39
40-Pin Encapsulated Package
740mil Extended
DQ15
DQ13
DQ11
DQ10
DQ9
DQ8
GND
DQ7
DQ5
DQ6
V
CC
WE
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A6
A7
40
38
37
36
35
34
33
32
31
30
29
27
28
CEL
DQ14
DQ12
CEU
DQ4
DQ3
15
16
26
25
A5
A4
17
18
DQ1
DQ2
A2
A3
23
24
DQ0
OE
19
20
22
21
A1
A0
background image
DS1258Y/AB
2 of 8
READ MODE
The DS1258 devices execute a read cycle whenever
WE
(Write Enable) is inactive (high) and either/both
of
CEU
or
CEL
(Chip Enables) are active (low) and
OE
(Output Enable) is active (low). The unique
address specified by the 17 address inputs (A0-A16) defines which of the 131,072 words of data is
accessed. The status of
CEU
and
CEL
determines whether all or part of the addressed word is accessed. If
CEU
is active with
CEL
inactive, then only the upper byte of the addressed word is accessed. If
CEU
is
inactive with
CEL
active, then only the lower byte of the addressed word is accessed. If both the
CEU
and
CEL
inputs are active (low), then the entire 16-bit word is accessed. Valid data will be available to
the 16 data output drivers within t
ACC
(Access Time) after the last address input signal is stable, providing
that
CEU
,
CEL
and
OE
access times are also satisfied. If
CEU
,
CEL
, and
OE
access times are not
satisfied, then data access must be measured from the later occurring signal, and the limiting parameter is
either t
CO
for
CEU
,
CEL
, or t
OE
for
OE
rather than address access.
WRITE MODE
The DS1258 devices execute a write cycle whenever
WE
and either/both of
CEU
or
CEL
are active (low)
after address inputs are stable. The unique address specified by the 17 address inputs (A0-A16) defines
which of the 131,072 words of data is accessed. The status of
CEU
and
CEL
determines whether all or
part of the addressed word is accessed. If
CEU
is active with
CEL
inactive, then only the upper byte of
the addressed word is accessed. If
CEU
is inactive with
CEL
active, then only the lower byte of the
addressed word is accessed. If both the
CEU
and
CEL
inputs are active (low), then the entire 16-bit word
is accessed. The write cycle is terminated by the earlier rising edge of
CEU
and/or
CEL
, or
WE
. All
address inputs must be kept valid throughout the write cycle.
WE
must return to the high state for a
minimum recovery time (t
WR
) before another cycle can be initiated. The
OE
control signal should be kept
inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled
(
CEU
and/or
CEL
, and
OE
active) then
WE
will disable the outputs in t
ODW
from its falling edge.
READ/WRITE FUNCTION Table 1
OE
WE
CEL
CEU
V
CC
CURRENT
DQ0-DQ7 DQ8-DQ15
CYCLE
PERFORMED
H H X X I
CCO
High-Z High-Z
Output
Disabled
L H L L
Output Output
L H L H
Output High-Z
L H H L
I
CCO
High-Z Output
Read Cycle
X L L L
Input Input
X L L H
Input High-Z
X L H L
I
CCO
High-Z Input
Write Cycle
X X H H I
CCS
High-Z High-Z
Output
Disabled

DATA RETENTION MODE
The DS1258AB provides full functional capability for V
CC
greater than 4.75V, and write protects by
4.5V. The DS1258Y provides full functional capability for V
CC
greater than 4.5V and write protects by
4.25V. Data is maintained in the absence of V
CC
without any additional support circuitry. The NV static
RAMs constantly monitor V
CC
. Should the supply voltage decay, the NV SRAMs automatically write
protect themselves, all inputs become "don't care," and all outputs become high impedance. As V
CC
falls
below approximately 3.0V, a power switching circuit connects the lithium energy source to RAM to
background image
DS1258Y/AB
3 of 8
retain data. During power-up, when V
CC
rises above approximately 3.0V, the power switching circuit
connects external V
CC
to RAM and disconnects the lithium energy source. Normal RAM operation can
resume after V
CC
exceeds 4.75V for the DS1258AB and 4.5V for the DS1258Y.
FRESHNESS SEAL
The DS1258 devices are shipped from Dallas Semiconductor with the lithium energy sources
disconnected, guaranteeing full energy capacity. When V
CC
is first applied at a level greater than V
TP
, the
lithium energy source is enabled for battery backup operation.

ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
-0.3V to +6.0V
Operating Temperature Range
0C to +70C, -40
C to +85C for Industrial Parts
Storage Temperature Range
-40C to +70C, -40
C to +85C for Industrial Parts
Soldering
Temperature
See
IPC/JEDEC
J-STD-020A
Specification
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (t
A
: See Note 10)
PARAMETER SYMBOL
MIN
TYP
MAX
UNITS
NOTES
DS1258AB Power Supply Voltage
V
CC
4.75
5.0 5.25 V
DS1258Y Power Supply Voltage
V
CC
4.5
5.0 5.5 V
Logic 1
V
IH
2.2 V
CC
V
Logic 0
V
IL
0.0 +0.8 V

DC ELECTRICAL
(V
CC
= 5V
5% for DS1258AB)
CHARACTERISTICS (t
A
: See Note 10) (V
CC
= 5V
10% for DS1258Y)
PARAMETER SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Leakage Current
I
IL
-2.0 +2.0 mA
I/O Leakage Current
CEU = CEL
V
IH
V
CC
I
IO
-1.0 +1.0
mA
Output Current @ 2.4V
I
OH
-1.0
mA
Output Current @ 0.4V
I
OL
2.0
mA
Standby Current
CEU
,
CEL
=2.2V
I
CCS1
0.7 1.5 mA
Standby Current
CEU
,
CEL
=V
CC
- 0.5V
I
CCS2
150 300 mA
Operating Current
I
CCO1
170
mA
Write Protection Voltage (DS1258AB)
V
TP
4.50 4.62 4.75
V
Write Protection Voltage (DS1258Y)
V
TP
4.25 4.37 4.5
V
background image
DS1258Y/AB
4 of 8
CAPACITANCE (t
A
= +25
C)
PARAMETER SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
C
IN
20 25 pF
Input/Output Capacitance
C
I/O
5 10 pF

AC ELECTRICAL
(V
CC
= 5V
5% for DS1258AB)
CHARACTERISTICS (t
A
: See Note 10) (V
CC
= 5V
10% for DS1258Y)
DS1258AB-70
DS1258Y-70
DS1258AB-100
DS1258Y-100
PARAMETER SYMBOL
MIN MAX MIN MAX UNITS NOTES
Read Cycle Time
t
RC
70 100 ns
Access Time
t
ACC
70 100 ns
OE
to Output Valid
t
OE
35 50 ns
CEU or CEL
to Output Valid
t
CO
70 100 ns
OE
or
CEU or CEL
to Output Valid
t
COE
5 5 ns 5
Output High Z from Deselection
t
OD
25 35 ns 5
Output Hold from Address Change
t
OH
5 5 ns
Write Cycle Time
t
WC
70 100 ns
Write Pulse Width
t
WP
55 75 ns 3
Address Setup Time
t
AW
0 0 ns
Write Recovery Time
t
WR1
t
WR2
5
15
5
15
ns
ns
12
13
Output High Z from
WE
t
ODW
25 35 ns 5
Output Active from
WE
t
OEW
5 5 ns 5
Data Setup Time
t
DS
30 40 ns 4
Data Hold Time
t
DH1
t
DH2
0
10
0
10
ns
ns
12
13

READ CYCLE
SEE NOTE 1
background image
DS1258Y/AB
5 of 8
WRITE CYCLE 1
SEE NOTE 2, 3, 4, 6, 7, 8 AND 12

WRITE CYCLE 2