November 1988
Revised December 1998
7
4
A
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T563 Octal
Latc
h
wit
h
3-
ST
A
T
E Output
s
1999 Fairchild Semiconductor Corporation
DS009970.prf
www.fairchildsemi.com
74ACT563
Octal Latch with 3-STATE Outputs
General Description
The ACT563 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output
Enable (OE) inputs.
The ACT563 device is functionally identical to the ACT573,
but with inverted outputs.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
s
Useful as input or output port for microprocessors
s
Functionally identical to ACT573 but with inverted out-
puts
s
Outputs source/sink 24 mA
s
ACT563 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Assignment
for SOIC
Pin Descriptions
FACT
TM
is a trademark of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74ACT563SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body
Pin Names
Description
D
0
D
7
Data Inputs
LE
Latch Enable Input
OE
3-STATE Output Enable Input
O
0
O
7
3-STATE Latch Outputs
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2
74A
CT563
Functional Description
The ACT563 contains eight D-type latches with 3-STATE
complementary outputs. When the Latch Enable (LE) input
is HIGH, data on the D
n
inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW the latches store the information that was present on
the D inputs at setup time preceding the HIGH-to-LOW
transition of LE. The 3-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers
are in the bi-state mode. When OE is HIGH the buffers are
in the high impedance mode but that does not interfere with
entering new data into the latches.
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
NC
=
No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Internal
Outputs
Function
OE
LE
D
Q
O
H
X
X
X
Z
High-Z
H
H
L
H
Z
High-Z
H
H
H
L
Z
High-Z
H
L
X
NC
Z
Latched
L
H
L
H
H
Transparent
L
H
H
L
L
Transparent
L
L
X
NC
NC
Latched
3
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7
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T563
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
TM
circuits outside databook specifications.
DC Electrical Characteristics
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Diode Current (I
IK
)
V
I
=
-
0.5V
-
20 mA
V
I
=
V
CC
+
0.5V
+
20 mA
DC Input Voltage (V
I
)
-
0.5V to V
CC
+
0.5V
DC Output Diode Current (I
OK
)
V
O
=
-
0.5V
-
20 mA
V
O
=
V
CC
+
0.5V
+
20 mA
DC Output Voltage (V
O
)
-
0.5V to V
CC
+
0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Junction Temperature (T
J
)
(PDIP)
140
C
Supply Voltage (V
CC
)
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
V/
t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=-
40
C to
+
85
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
4.5
1.5
2.0
2.0
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
2.0
2.0
or V
CC
-
0.1V
V
IL
Maximum LOW Level
4.5
1.5
0.8
0.8
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
0.8
0.8
or V
CC
-
0.1V
V
OH
Minimum HIGH Level
4.5
4.49
4.4
4.4
V
I
OUT
=
-
50
A
Output Voltage
5.5
5.49
5.4
5.4
V
IN
=
V
IL
or V
IH
4.5
3.86
3.76
V
I
OH
=
-
24 mA
5.5
4.86
4.76
I
OH
=
-
24 mA (Note 2)
V
OL
Maximum LOW Level
4.5
0.001
0.1
0.1
V
I
OUT
=
50
A
Output Voltage
5.5
0.001
0.1
0.1
V
IN
=
V
IL
or V
IH
4.5
0.36
0.44
V
I
OL
=
24 mA
5.5
0.36
0.44
I
OL
=
24 mA (Note 2)
I
IN
Maximum Input
5.5
0.1
1.0
A
V
I
=
V
CC
, GND
Leakage Current
I
OZ
Maximum 3-STATE
5.5
0.25
2.5
A
V
I
=
V
IL
, V
IH
Current
V
O
=
V
CC
, GND
I
CCT
Maximum
5.5
0.6
1.5
mA
V
I
=
V
CC
-
2.1V
I
CC
/Input
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
=
1.65V Max
I
OHD
Output Current (Note 3)
5.5
-
75
mA
V
OHD
=
3.85V Min
I
CC
Maximum Quiescent
5.5
4.0
40.0
A
V
IN
=
V
CC
Supply Current
or GND
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4
74A
CT563
AC Electrical Characteristics
Note 4: Voltage Range 5.0 is 5.0V
0.5V
AC Operating Requirements
Note 5: Voltage Range 5.0 is 5.0V
0.5V
Capacitance
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 4)
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
5.0
3.0
7.0
11.5
2.5
12.5
ns
D
n
to O
n
t
PHL
Propagation Delay
5.0
3.0
6.0
10.0
2.5
11.0
ns
D
n
to O
n
t
PLH
Propagation Delay
5.0
3.0
6.5
10.5
2.5
11.5
ns
LE to O
n
t
PHL
Propagation Delay
5.0
2.5
5.5
9.5
2.0
10.5
ns
LE to O
n
t
PZH
Output Enable Time
5.0
2.5
5.5
9.0
2.0
10.0
ns
t
PZL
Output Enable Time
5.0
2.0
5.5
8.5
2.0
9.5
ns
t
PHZ
Output Disable Time
5.0
3.5
6.5
10.5
2.5
11.5
ns
t
PLZ
Output Disable Time
5.0
2.0
4.5
8.0
1.0
8.5
ns
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 5)
Typ
Guaranteed Minimum
t
s
Setup Time, HIGH or LOW
5.0
1.5
4.0
4.5
ns
D
n
to LE
t
h
Hold Time, HIGH or LOW
5.0
-
2.0
0
0
ns
D
n
to LE
t
w
LE Pulse Width, HIGH
5.0
2.0
3.0
3.0
ns
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
=
OPEN
C
PD
Power Dissipation Capacitance
50.0
pF
V
CC
=
5.0V
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
7
4
A
C
T563 Octal
Latc
h
wit
h
3-
ST
A
T
E Output
s
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body
Package Number M20B
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