Flash MCU(HMS39C7092)

Preliminary

Released : February. 2001

ARM

is trademark of Advanced RISC Machine Ltd.

ARM7TDMI is designed by ARM Ltd.

The information contained herein is subject to change without notice.

The information contained herein is presented only as a guide for the applications of our products. No

responsibility is assumed by Hynix for any infringements of patents or other rights of the third parties

which may result from its use. No license is granted by implication or otherwise under any patent or

patent rights of Hynix or others.

These Hynix products are intended for usage in general electronic equipment (office equipment,

communication equipment, measuring equipment, domestic electrification, etc.).

Please make sure that you consult with us before you use these Hynix products in equipment which

require high quality and / or reliability, and in equipment which could have major impact to the welfare of

human life (atomic energy control, airplane, spaceship, traffic signal, combustion control, all types of

safety devices, etc.). Hynix cannot accept liability to any damage which may occur in case these Hynix

products were used in the mentioned equipment without prior consultation with Hynix.

Flash MCU(HMS39C7092)

Preliminary

Contents

Chapter 1...........................................................................................................................13

Introduction .................................................................................................................13

1.1

General Description................................................................................14

1.2

Feature..................................................................................................15

1.3

Pin Descriptions .....................................................................................16

1.4

Operation Mode description ....................................................................21

1.5

Memory Map..........................................................................................25

Chapter 2...........................................................................................................................27

ARM7TDMI Core .........................................................................................................27

2.1

General Description................................................................................28

2.2

Feature..................................................................................................28

2.3

Core Block Diagram ...............................................................................29

2.4

Instruction Set ........................................................................................30

2.4.1 ARM Instruction ..................................................................................30

2.4.2 THUMB Instruction..............................................................................33

2.4.3 The Program Status Registers .............................................................36

2.4.3.1 The condition code flags ............................................................37

2.4.3.2 The control bits..........................................................................37

2.4.4 ARM pseudo-instructions .....................................................................39

2.4.5 THUMB pseudo-instructions ................................................................43

Chapter 3...........................................................................................................................47

BUS Controller ............................................................................................................47

3.1

Overview ...............................................................................................48

3.1.1 Features .............................................................................................48

3.1.2 Pin Configuration.................................................................................49

3.2

Bus Controller Registers .........................................................................50

3.2.1 Configuration Registers .......................................................................51

3.3

Operation ..............................................................................................52

3.3.1 Area Division ......................................................................................52

3.3.2 Area Division ......................................................................................53

3.3.3 Chip Select Signals .............................................................................53

3.4

Basic Bus Interface ................................................................................54

3.4.1 Overview ............................................................................................54

3.4.2 Byte Lane Write Control .......................................................................54

3.4.3 Basic Bus Control Signal Timing...........................................................56

3.4.4 Wait Control ........................................................................................62

3.4.5 Bus Arbiter..........................................................................................63

Chapter 4...........................................................................................................................65

MCU Controller ...........................................................................................................65

4.1

General Description................................................................................66

4.2

Pin Function Description.........................................................................66

4.3

4.3.1 Register Memory Map .........................................................................67

4.3.2 PINMUX Register ................................................................................68

4.3.3 MCU Device Code Register (0x0900_002C Read Only) ......................72

Flash MCU(HMS39C7092)

Preliminary

Chapter 5...........................................................................................................................73

Power Management Unit..............................................................................................73

5.1

General Description................................................................................74

5.2

Operation Modes....................................................................................75

5.2.1 Introduction.........................................................................................75

5.2.2 Reset and Operation Modes ................................................................75

5.3

Power Management Unit Register Map....................................................77

5.4

5.5

Signal Timing Diagram............................................................................81

5.5.1 Power on Reset ..................................................................................81

5.5.2 Watch Dog Timer Overflow ..................................................................81

5.5.3 Soft-Reset ..........................................................................................82

Chapter 6...........................................................................................................................83

The Interrupt Controller................................................................................................83

6.1

About the Interrupt controller ...................................................................84

6.1.1 Interrupt sources .................................................................................85

6.1.2 Interrupt Control ..................................................................................85

6.2

Interrupt Controller Registers ..................................................................87

Chapter 7...........................................................................................................................91

Watchdog Timer ..........................................................................................................91

7.1

General Description................................................................................92

7.2

Watchdog Timer Introduction...................................................................93

7.3

Watchdog Timer Operation .....................................................................94

7.3.1 Timing of Setting and Clearing the Overflow Flag ..................................95

7.4

Watchdog Timer Memory Map.................................................................96

7.5

Watchdog Timer Register Descriptions ....................................................97

7.6

Examples of Register Setting ................................................................ 100

7.6.1 Interval Timer Mode......................................................................... 100

7.6.2 Watchdog Timer Mode with Internal Reset Disable .............................. 101

7.6.3 Watchdog Timer Mode with Power-on Reset ....................................... 102

7.6.4 Watchdog Timer Mode with Manual Reset .......................................... 103

Chapter 8......................................................................................................................... 105

The General Purpose Timer ....................................................................................... 105

8.1

About the General Purpose Timer Unit................................................... 106

8.1.1 General Purpose Timer Unit Introduction ............................................ 107

8.2

General Purpose Timer Unit Memory Map ............................................. 108

8.2.1 Register Assignment ......................................................................... 108

8.2.2 General Purpose Timer Unit Register Descriptions .............................. 109

8.2.2.1 Timer Global Control Registers ................................................. 109

8.2.2.2 Timer Channel Control Registers .............................................. 110

8.3

General Purpose Timer Unit Operation .................................................. 114

8.3.1 Free Running Mode........................................................................... 115

8.3.2 Compare Match Mode ....................................................................... 117

8.3.3 Input Capture Mode........................................................................... 119

8.3.4 Synchronized Clear and Write Mode................................................... 120

8.3.5 PWM Mode....................................................................................... 121

8.3.5.1 PWM Mode Operation ............................................................. 121

Chapter 9......................................................................................................................... 125

UART (Universal Asynchronous Receiver/Transmitter)................................................. 125

Flash MCU(HMS39C7092)

Preliminary

9.1

General Description.............................................................................. 126

9.2

Features .............................................................................................. 127

9.3

Signal Description ................................................................................ 127

9.4

Internal Block Diagram ......................................................................... 128

9.5

Registers Description ........................................................................... 129

9.6

UART Operations ................................................................................. 140

9.6.1 FIFO Interrupt Mode Operation .......................................................... 140

9.6.2 FIFO Polled Mode Operation ............................................................. 141

9.7

Chapter 10. ...................................................................................................................... 143

GPIO (General Purpose Input Output) ........................................................................ 143

10.1

General Description.............................................................................. 144

10.2

GPIO Registers .................................................................................... 145

10.2.1 Register Memory Map...................................................................... 145

10.3.1 Register Description ........................................................................ 146

10.3

Functional Description .......................................................................... 147

Chapter 11 ....................................................................................................................... 149

On-Chip SRAM ......................................................................................................... 149

11.1

General Description.............................................................................. 150

11.2

Function Description............................................................................. 150

Chapter 12 ....................................................................................................................... 151

On-chip Flash Memory ............................................................................................... 151

12.1

General Description.............................................................................. 152

12.2

Features .............................................................................................. 152

12.3

Block Diagram ..................................................................................... 154

12.4

Flash Memory Register Description ....................................................... 156

12.5

On-Board Programming Mode .............................................................. 161

12.5.1 Boot Mode ..................................................................................... 161

12.5.2 User Program Mode ....................................................................... 164

12.6

Flash Memory Programming/Erasing ..................................................... 166

12.6.1 Program & Program-Verify Mode ...................................................... 166

12.6.2 Pre-program & Pre-program Verify Mode ......................................... 168

12.6.3 Erase & Erase Verify Mode ............................................................. 170

12.6.4 Erase Algorithm .............................................................................. 172

12.7

Flash Memory PROM Mode .................................................................. 173

12.7.1 PROM Mode Setting ....................................................................... 173

12.7.2 Memory Map .................................................................................. 174

12.7.3 PROM Mode Operation................................................................... 174

12.7.4 Timing Diagram and AC/DC Characteristics ..................................... 175

Chapter 13 ....................................................................................................................... 179

A/D Converter ........................................................................................................... 179

13.1

Overview ............................................................................................. 180

13.1.1 Features ......................................................................................... 180

13.1.2 Pin Configuration ............................................................................. 181

13.2

A/D Converter Registers ....................................................................... 182

13.2.1 Register Descriptions ....................................................................... 182

13.3

Operation ............................................................................................ 185

13.4

Interrupts ............................................................................................. 186

13.5

Usage Notes ........................................................................................ 187

Flash MCU(HMS39C7092)

Preliminary

13.6

Example .............................................................................................. 190

Chapter 14 ....................................................................................................................... 191

Electrical Characteristics............................................................................................ 191

14.1

Absolute Maximum Ratings................................................................... 192

14.2

Recommended Operating Conditions: ................................................... 192

14.3

DC Characteristics ............................................................................... 193

14.4

AC Characteristics................................................................................ 194

14.4

AD Conversion characteristics (Preliminary)........................................... 196

14.5

Operational Timing ............................................................................... 197

14.5.1 Clock Timing ..................................................................................... 197

14.5.2 Reset Timing .................................................................................... 197

14.5.3 Bus Timing ....................................................................................... 198

Appendix

A-1

Peripheral Setting & Flash memory control Examples

A-2

Package Dimension

Flash MCU(HMS39C7092)

Preliminary

Figures

Figure 1.1 Package Outline........................................................................................14

Figure 1.2 HMS39C7092 Block Diagram ....................................................................15

Figure 1.3 HMS39C7092 Memory Map.......................................................................25

Figure 1.4 Memory Map of Mode 3.............................................................................25

Figure 1.5 Memory Map of when Mode 4 and Mode 5 .................................................26

Figure 1.6 Memory Map of Mode 6 and Mode 7 ..........................................................26

Figure 2.1 ARM7TDMI Core Block Diagram ................................................................29

Figure 2.2 ARM instruction set formats .......................................................................30

Figure 2.3 Register Organization in ARM state............................................................32

Figure 2.4 THUMB instruction set formats...................................................................33

Figure 2.5 Register Organization in THUMB state .......................................................35

Figure 2.6 Mapping of THUMB state registers onto ARM state registers. ......................35

Figure 2.7 Program status register format ...................................................................36

Figure 3.1 Block Diagram of the Bus Controller ...........................................................48

Figure 3.2 Access Area Map for Each Operating Mode................................................52

Figure 3.3 Access Size and Data Alignment Control (8-Bit Access Area) ......................54

Figure 3.4 Access Size and Data Alignment Control (16-Bit Access Area) ....................55

Figure 3.5 Bus Control Signal Write Timing for 16-Bit, 1-Wait (Word Access) ................56

Figure 3.6 Bus Control Signal Read Timing for 16-Bit, 1-Wait (Word Access)................56

Figure 3.7 Bus Control Signal Write Timing for 16-Bit, 1-Wait (Half-word Access)..........57

Figure 3.8 Bus Control Signal Read Timing for 16-Bit, 1-Wait (Half-word Access)..........57

Figure 3.9 Bus Control Signal Write Timing for 16-Bit, 1-Wait (Byte Access)..................58

Figure 3.10 Bus Control Signal Read Timing for 16-Bit, 1-Wait (Byte Access)................58

Figure 3.11 Bus Control Signal Write Timing for 16-Bit, 2-Wait (Word Access)...............59

Figure 3.12 Bus Control Signal Read Timing for 16-Bit, 2-Wait (Word Access) ..............59

Figure 3.13 Bus Control Signal Write Timing for 16-Bit, 2-Wait (Half-Word Access)........60

Figure 3.14 Bus Control Signal Read Timing for 16-Bit, 2-Wait (Half-Word Access) .......60

Figure 3.15 Bus Control Signal Write Timing for 16-Bit, 2-Wait (Byte Access)................61

Figure 3.16 Bus Control Signal Read Timing for 16-Bit, 2-Wait (Byte Access)................61

Figure 3.17 Example of Wait State Insertion Timing. ....................................................62

Figure 3.18 Example of External Bus Master Operation...............................................64

Figure 5.1 PMU Block Diagram ..................................................................................74

Figure 5.2 Reset and Power Management State Machine. ...........................................76

Figure 5.3 Power on Reset Timing Diagram ................................................................81

Figure 5.4 Watch Dog Timer Overflow Timing Diagram ................................................81

Figure 5.5 Soft Reset (from WDT) Timing Diagram ......................................................82

Figure 5.6 Soft Reset (from PMU) Timing Diagram ......................................................82

Figure 6.1 Interrupt Control Flow Diagram ..................................................................84

Figure 7.1 Watchdog Timer Module Block Diagram .....................................................92

Figure 7.2 Operation in the Watchdog Timer Mode ......................................................94

Figure 7.3 Operation in the Interval Timer Mode ..........................................................95

Figure 7.4 Interrupt Clear in the Interval Timer Mode ................................................. 100

Figure 7.5 Interrupt Clear in the Watchdog Timer Mode with Reset Disable................. 101

Figure 7.6 Interrupt Clear in the Watchdog Timer Mode with Power-on Reset.............. 102

Figure 7.7 Interrupt Clear in the Watchdog Timer Mode with Manual Reset ................. 103

Figure 8.1 General-purpose Timer Unit Module Block Diagram .................................. 106

Flash MCU(HMS39C7092)

Preliminary

Figure 8.2 Free-Running Counter Operation ............................................................. 115

Figure 8.3 Periodic Counter Operation...................................................................... 116

Figure 8.4 Example of 0 Output/1 Output .................................................................. 117

Figure 8.5 Example of Toggle Output ........................................................................ 118

Figure 8.6 Compare Match Signal Output Timing ...................................................... 118

Figure 8.7 Input Capture Operation .......................................................................... 119

Figure 8.8 Synchronized Operation Example ............................................................ 120

Figure 8.9 PWM Mode Operation Example 1 ............................................................ 121

Figure 8.10 PWM Mode Operation Example 2........................................................... 122

Figure 8.11 Reset-Synchronized PWM Mode Operation Example............................... 123

Figure 9.1 TOP BLOCK Diagram ............................................................................. 126

Figure 9.2 Internal UART Diagram ........................................................................... 128

Figure 10.1 GPIO Block Diagram and PADS Connections(example for Port A and Port B)

......................................................................................................................... 144

Figure 12.1 Block Diagram of Flash Memory ............................................................. 154

Figure 12.2 System Configuration When Using On-Board Boot Mode ......................... 161

Figure 12.3 Boot Mode Execution Procedure ............................................................ 162

Figure 12.4 User Mode Execution Procedure............................................................ 164

Figure 12.5 Flash Program & Program Verify Sequence............................................ 167

Figure 12.6 Flash Pre-program & Pre-program Verify Sequence ................................ 169

Figure 12.7 Flash Erase & Erase Verify Sequence .................................................... 171

Figure 12.8 Flash Erase Algorithm ........................................................................... 172

Figure 12.9 Timing Diagram of Read ........................................................................ 175

Figure 12.10 Timing Diagram of Pre-Program/Program ............................................. 176

Figure 12.11 Timing Diagram of Erase...................................................................... 176

Figure 12.12 Timing Diagram of Pre-Program/Program Verify .................................... 177

Figure 12.13 Timing Diagram of Erase Verify ............................................................ 177

Figure 13.1 Block Diagram of A/D Converter............................................................. 180

Figure 13.2 A/D converter Operation ........................................................................ 185

Figure 13.3 Example of Analog Input Circuit ............................................................. 188

Figure 13.4 A/D Converter Accuracy Definitions (1)................................................... 188

Figure 13.5 A/D Converter Accuracy Definitions (2)................................................... 189

Figure 14.1 The settling time of the crystal oscillator.................................................. 197

Figure 14.2 Reset Input Timing ................................................................................ 197

Figure 14.3 The Write Timing Diagram of the Bus Controller ...................................... 198

Figure 14.4 The Read Timing Diagram of the Bus Controller ...................................... 198

Figure 14.5 Basic Bus Cycle with External Wait State................................................ 199

Figure 14.6 Bus Release Mode Timing ..................................................................... 199

Flash MCU(HMS39C7092)

Preliminary

Tables

Table 1.1 Pin Descriptions .........................................................................................16

Table 1.1 Pin Descriptions (Continued) .......................................................................17

Table 1.1 Pin Descriptions (Continued) .......................................................................18

Table 1.1 Pin Descriptions (Continued) .......................................................................19

Table 1.1 Pin Descriptions (Continued) .......................................................................20

Table 1.2 HMS39C7092 Operation modes ..................................................................21

Table 1.3 Pin assignment by mode.............................................................................22

Table 1.3 Pin assignment by mode (continued) ...........................................................23

Table 1.3 Pin assignment by mode (continued) ...........................................................24

Table 2.1 The ARM Instruction set ..............................................................................31

Table 2.2 THUMB instruction set opcodes ...................................................................34

Table 2.3 Condition code summary .............................................................................36

Table 2.4 PSR mode bit values ..................................................................................38

Table 3.1 Bus Controller Pins .....................................................................................49

Table 3.2 BUS Controller Register Map.......................................................................50

Table 3.3 Byte Lane condition by XA[0] .......................................................................55

Table 4.1 Pin Function Descriptions ............................................................................66

Table 4.2 Memory map of the MCU Controller .............................................................67

Table 4.3 MCU Controller Initial values in each mode ..................................................67

Table 5.1 Register Map of the PMU ............................................................................77

Table 6.1 Interrupt Controller Default Setting Value......................................................85

Table 6.2 Memory Map of the Interrupt Controller ........................................................87

Table 6.3 Interrupt Source Trigger Mode.....................................................................88

Table 7.1 Memory Map of the Watchdog Timer APB Peripheral ....................................96

Table 7.2 Internal Counter Clock Sources (SYSCLK = 40 MHz)....................................98

Table 8.1 Timer Global Control Register Map ............................................................ 108

Table 8.2 Timer Channel Control Register Map ......................................................... 108

Table 8.3 Timer Channel Starting Address ................................................................ 108

Table 9.1 Signal Descriptions ................................................................................... 127

Table 9.2 UART Register Address Map (0x1500 in UART1) ....................................... 129

Table 9.3 UART Register Reset Values ..................................................................... 129

Table 9.4a Divisor Values for each Baud rate (CLK=1.8432MHz)................................ 133

Table 9.4b Divisor Values for each Baud rate (CLK=3.6864MHz)................................ 133

Table 9.5 Interrupt Control Functions ........................................................................ 138

Table 9.6 Summary of Registers............................................................................... 142

Table 10.1 GPIO Register Memory Map.................................................................... 145

Table 12.1 Operating mode...................................................................................... 153

Table 12.2 Signal description of Figure 12.1(BUS Interface) ....................................... 155

Table 12.3 Flash Memory Registers.......................................................................... 156

Table 12.4 Control Register...................................................................................... 158

Table 12.5 Erase Block Register............................................................................... 159

Table 12.6 Status & Power Register ......................................................................... 160

Table 12.7 FR_SEL Value for access to internal Register ........................................... 173

Table 12.8 Setting for Register read/write.................................................................. 173

Table 12.9 Erase Block Register............................................................................... 174

Table 12.10 Setting for Flash PROM read/write ......................................................... 175

Flash MCU(HMS39C7092)

Preliminary

Table 12.11 DC Characteristics ................................................................................ 178

Table 12.12 AC Characteristics ................................................................................ 178

Table 13.1 A/D Converter Pins ................................................................................. 181

Table 13.2 Summarizes the A/D converter's registers. ............................................... 182

Table 14.1 Absolute Maximum Ratings - Preliminary -............ 192

Table 14.2 Recommended Operating Conditions - Preliminary- ............. 192

Table 14.3 DC Characteristics - Preliminary- .......... 193

Table 14.4 IO Circuits with pull-ups - Preliminary- ........... 193

Table 14.5 IO Circuits with pull-downs - Preliminary- ............ 193

Table 14.6 Clock Timing - Preliminary-........... 194

Table 14.7 Control Signal Timing - Preliminary- ........... 194

Table 14.8 Bus Timing - Preliminary- .......... 195

Table 14.9 Operating Conditions of the AD Conversion - Preliminary-............. 196

Table 14.10 Electrical characteristics of the AD converter - Preliminary-............. 196

Introduction

Flash MCU(HMS39C7092)

Preliminary

1.1

General Description

The 16bit MCU with embedded flash memory for optical storage is the first member

of Hynix Micro Electronics 16/32bit MCU Family of high performance microcontroller

units (MCUs). This family includes a series of peripherals from which numerous

MCUs are assembled. This MCU contains extensive peripherals : 192Kbytes flas h

memory, 4K bytes SRAM, 6 channel 16bit Timer, Watch Dog Timer, 2 channel UART,

Programmable Priority Interrupt Controller, 81bits PIO, BUS Controller including Chip

select logic, which is On-Chip Modular Architecture (using AMBA).

Figure 1.1 Package Outline

1 2 3

4 5

7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

75 74 73

72 71

69 68 67

66 65

63 62 61 60 59 58 57 56 55

54 53

52 51

100

HMS39C7092

2001.02

/P2

VSS

/P1

VDD

/P3

/P4

VDD

nCS

/TIOCA

/PB

nCS

/TIOCB

/PB

nCS

/TIOCA

/PB

nCS

/TIOCB

/PB

TMS

/PB

TDO/PB

TDI/PB

TCK/PB

XP9

VSS

TxD

/P9

RxD

/P9

TxD

/P9

RxD

/P9

nIRQ

/P9

nIRQ

/P9

/P4

VSS

/P4

/P2

/P5

VSS

nWAIT

/P6

nBREQ

/P6

nBACK

/P6

CLKO/P6

nSTBY

nRES

nTRST

/P9

VSS

XTALOUT

XTALIN

VDD

nAS
/P6

nRD

/P6

nHWR

/P6

nLWR

/P6

MODE

AVDD
AV

REF

/P7

VSS

TIOCA

/nIRQ

/P7

TIOCB

/nIRQ

/P7

nIRQ

/P8

nCS

/nIRQ

/P8

nCS

/nIRQ

/P8

nCS

/nIRQ

/P8

nCS

/P8

VSS

TCLKA/PA

TCLKB/PA

TCLKC/TCIOA

/PA

TCLKD/TCIOB

/PA

/TIOCA

/PA

/TIOCB

/PA

/TIOCA

/PA

/TIOCB

/PA

Flash MCU(HMS39C7092)

Introduction

Preliminary

1.2

Feature

On-Chip Modular Architecture (using AMBA)

Utilizes the ARM7TDMI 32/16bit RISC Family

192Kbyte flash memory

4Kbyte internal SRAM

8/16-bit external Data Bus

Eight Programmable Chip Select Outputs with external wait input

Low Power Consumption using Power Management Unit

Fully static operation : Max. 50MHz

Programmable Priority Interrupt Controller (8 external sources)

Six 16bit Multi Function Timers/Counters for General Purpose Applications

One 8bit Watch Dog Timer (WDT)

Two UARTs (Universal Asynchronous Receiver Transmitter) compatible with

16C550 UART

Programmable Input/Output ports (81-bits)

100 TQFP Package

Figure 1.2 HMS39C7092 Block Diagram

BUS

Controller

BUS

Controller

APB

Bridge

APB

Bridge

SRAM

4kbyte

SRAM

4kbyte

Flash Memory

192kbyte

Flash Memory

192kbyte

Arbiter

WDT

PIO

INTC

TIMER

UART

ADC

Multi-Function Pin MUX

ARM7TDMI

TIC*

PMU

* TIC : Test Interface Controller

Max. 50MHz

ASB (Max. 50MHz)

Introduction

Flash MCU(HMS39C7092)

Preliminary

1.3

Pin Descriptions

Table 1.1 Pin Descriptions

PIN

SYMBOL

DIR

DESCRIPTION

VDD

Power Supply 3.3V

nCS

External Chip Selection Number 7

TCIOA

I/O

PWM output, Compare match output of Reg.A and signal capture input of Timer Ch3

I/O

General purpose input output of port B bit0

nCS

External Chip Selection Number 6

TCIOB

I/O

PWM output, Compare match output of Reg.B and signal capture input of Timer Ch3

I/O

General purpose input output of port B bit 1

nCS

External Chip Selection Number 5

TIOCA

I/O

PWM output, Compare match output of Reg.A and signal capture input of Timer Ch4

I/O

General purpose input output of port B bit2

nCS

External Chip Selection Number 4

TIOCB

I/O

PWM output, Compare match output of Reg.B and signal capture input of Timer Ch4

I/O

General purpose input output of port B bit3

TMS

JTAG Test Mode Selection

I/O

General purpose input output of port B bit4

TDO

JTAG Test Data Output

I/O

General purpose input output of port B bit5

TDI

JTAG Test Data Input

I/O

General purpose input output of port B bit6

TCK

JTAG Test Clock

I/O

General purpose input output of port B bit7

TVPPD

5Vinput for the use of Programming and Erasing of the Flash Memory

VSS

Power ground

TxD

Transmit Data of UART Ch0

I/O

General purpose input output of port 9 bit 0

RxD

Receive Data of UART Ch0

I/O

General purpose input output of port 9 bit 1

TxD

Transmit Data of UART Ch1

I/O

General purpose input output of port 9 bit 2

RxD

Receive Data of UART Ch1

I/O

General purpose input output of port 9 bit 3

nIRQ

External Interrupt Request number 4

I/O

General purpose input output of port 9 bit 4

nIRQ

External Interrupt Request number 5

I/O

General purpose input output of port 9 bit 5

I/O

External Data Bus bit 0

I/O

General purpose input output or port 4 bit 0

I/O

External Data Bus bit 1

I/O

General purpose input output or port 4 bit 1

I/O

External Data Bus bit 2

I/O

General purpose input output or port 4 bit 2

I/O

External Data Bus bit 3

I/O

General purpose input output or port 4 bit 3

Flash MCU(HMS39C7092)

Introduction

Preliminary

Table 1.1 Pin Descriptions (Continued)

PIN

SYMBOL

DIR

DESCRIPTION

VSS

Power ground

I/O

External Data Bus bit 4

I/O

General purpose input output or port 4 bit 4

I/O

External Data Bus bit 5

I/O

General purpose input output or port 4 bit 5

I/O

External Data Bus bit 6

I/O

General purpose input output or port 4 bit 6

I/O

External Data Bus bit 7

I/O

General purpose input output or port 4 bit 7

I/O

External Data Bus bit 8

I/O

General purpose input output or port 3 bit 0

I/O

External Data Bus bit 9

I/O

General purpose input output or port 3 bit 1

I/O

External Data Bus bit 10

I/O

General purpose input output or port 3 bit 2

I/O

External Data Bus bit 11

I/O

General purpose input output or port 3 bit 3

I/O

External Data Bus bit 12

I/O

General purpose input output or port 3 bit 4

I/O

External Data Bus bit 13

I/O

General purpose input output or port 3 bit 5

I/O

External Data Bus bit 14

I/O

General purpose input output or port 3 bit 6

I/O

External Data Bus bit 15

I/O

General purpose input output or port 3 bit 7

VDD

Power Supply 3.3V

External Address Bus bit 0

I/O

General purpose input output or port 1 bit 0

External Address Bus bit 1

I/O

General purpose input output or port 1 bit 1

External Address Bus bit 2

I/O

General purpose input output or port 1 bit 2

External Address Bus bit 3

I/O

General purpose input output or port 1 bit 3

External Address Bus bit 4

I/O

General purpose input output or port 1 bit 4

External Address Bus bit 5

I/O

General purpose input output or port 1 bit 5

External Address Bus bit 6

I/O

General purpose input output or port 1 bit 6

External Address Bus bit 7

I/O

General purpose input output or port 1 bit 7

VSS

Power ground

External Address Bus bit 8

I/O

General purpose input output or port 2 bit 0

External Address Bus bit 9

I/O

General purpose input output or port 2 bit 1

External Address Bus bit 10

I/O

General purpose input output or port 2 bit 2

Introduction

Flash MCU(HMS39C7092)

Preliminary

Table 1.1 Pin Descriptions (Continued)

PIN

SYMBOL

DIR

DESCRIPTION

External Address Bus bit 11

I/O

General purpose input output or port 2 bit 3

External Address Bus bit 12

I/O

General purpose input output or port 2 bit 4

External Address Bus bit 13

I/O

General purpose input output or port 2 bit 5

External Address Bus bit 14

I/O

General purpose input output or port 2 bit 6

External Address Bus bit 15

I/O

General purpose input output or port 2 bit 7

External Address Bus bit 16

I/O

General purpose input output of port 5 bit 0

External Address Bus bit 17

I/O

General purpose input output of port 5 bit 1

External Address Bus bit 18

I/O

General purpose input output of port 5 bit 2

External Address Bus bit 19

I/O

General purpose input output of port 5 bit 3

VSS

Power ground

nWAIT

External BUS cycle wait signal

I/O

General purpose input output of port 6 bit 0

nBREQ

External BUS Request

I/O

General purpose input output of port 6 bit 1

nBACK

External BUS Acknowledge

I/O

General purpose input output of port 6 bit 2

CLKO

BUS Clock Output

I/O

General purpose input output of port 6 bit 7

nSTBY

Standby mode signal. Power Down mode indicating

nRES

External Reset input

nTRST

JTAG Test Reset input

I/O

General purpose input output of port 9 bit 7

VSS

Power ground

XTALOUT

Crystal feedback output

XTALIN

Crystal or External Oscillator input

VDD

Power Supply 3.3V

nAS

External Address Bus strobe

I/O

General purpose input output of port 6 bit 3

nRD

External Bus Read

I/O

General purpose input output of port 6 bit 4

nHWR

External upper 8 bit data bus write

I/O

General purpose input output of port 6 bit 5

nLWR

External lower 8 bit data bus write

I/O

General purpose input output of port 6 bit 6

MODE

MODE bit 0

MODE

MODE bit 1

MODE

MODE bit 2

AVDD

Analog Power Supply 3.3V

AVREF

ADC Reference Voltage

Flash MCU(HMS39C7092)

Introduction

Preliminary

Table 1.1 Pin Descriptions (Continued)

PIN

SYMBOL

DIR

DESCRIPTION

General purpose output of port 7 bit 0

ADC Channel 0 input

General purpose output of port 7 bit 1

ADC Channel 1 input

General purpose output of port 7 bit 2

ADC Channel 2 input

General purpose output of port 7 bit 3

ADC Channel 3 input

General purpose output of port 7 bit 4

ADC Channel 4 input

VSS

Power ground

TIOCA

I/O

PWM output, Compare match output of Reg.A and signal capture input of Timer Ch5

nIRQ

External Interrupt Request number 6

I/O

General purpose input output of port 7 bit 6

TIOCB

I/O

PWM output, Compare match output of Reg.B and signal capture input of Timer Ch5

nIRQ

External Interrupt Request number 7

I/O

General purpose input output of port 7 bit 7

I/O

General purpose input output of port 7 bit 5

nIRQ

External Interrupt Request number 0

I/O

General purpose input output of port 8 bit 0

nCS

External Chip Selection Number 3

nIRQ

External Interrupt Request number 1

I/O

General purpose input output of port 8 bit 1

nCS

External Chip Selection Number 2

nIRQ

External Interrupt Request number 2

I/O

General purpose input output of port 8 bit 2

nCS

External Chip Selection Number 1

nIRQ

External Interrupt Request number 3

I/O

General purpose input output of port 8 bit 3

nCS

External Chip Selection Number 0

I/O

General purpose input output of port 8 bit 4

VSS

Power ground

TCLKA

External timer input clock A

I/O

General purpose input output of port A bit 0

TCLKB

External timer input clock B

I/O

General purpose input output of port A bit 1

TCLKC

External timer input clock C

TIOCA

I/O

PWM output, Compare match output of Reg.A and signal capture input of Timer Ch0

I/O

General purpose input output of port A bit 2

TCLKD

External timer input clock D

TIOCB

I/O

PWM output, Compare match output of Reg.B and signal capture input of Timer Ch0

I/O

General purpose input output of port A bit 3

External Address Bus bit 23

TIOCA

I/O

PWM output, Compare mat ch output of Reg.A and signal capture input of Timer Ch1

I/O

General purpose input output of port A bit 4

Introduction

Flash MCU(HMS39C7092)

Preliminary

Table 1.3 Pin assignment by mode

MODE 2

MODE 3

MODE 4

MODE 6

MODE 5

MODE 7

PIN

External

8bit BUS

External

16bit BUS

Flash boot mode

with 16bit BUS

UART boot mode

with 16bit BUS

Flash boot mode

(MICOM mode)

UART boot mode

(MICOM mode)

VDD

nCS7

TIOCA3

nCS6

TIOCB3

nCS5

TIOCA4

nCS4

TIOCB4

TMS

TDO

TDI

TCK

TVPPD

VSS

TxD0

RxD0

TxD1

RxD1

nIRQ4

nIRQ5

P40

P41

P42

P43

VSS

P44

P45

P46

P47

P30

P31

P32

D10

P32

P33

D11

P33

P34

D12

P34

P35

D13

P35

P36

D14

P36

P37

D15

P37

VDD

P10

P11

P12

P13

P14

Flash MCU(HMS39C7092)

Introduction

Preliminary

Table 1.3 Pin assignment by mode (continued)

MODE2

MODE3

MODE4

MODE6

MODE5

MODE7

PIN

No.

External

8bit BUS

External

16bit BUS

Flash boot mode

with 16bit BUS

UART boot mode

with 16bit BUS

Flash boot mode

(MICOM mode)

UART boot mode

(MICOM mode)

P15

P16

P17

VSS

P20

P21

A10

P22

A11

P23

A12

P24

A13

P25

A14

P26

A15

P27

A16

P50

A17

P51

A18

P52

A19

P53

VSS

nWAIT

P60

nBREQ

P61

nBACK

P62

CLKO

P67

nSTBY

nRES

nTRST

VSS

XTALOUT

XTALIN

VDD

nAS

P63

nRD

P64

nHWR

P65

nLWR

P66

MODE0

MODE1

MODE2

AVDD

AVREF

AN0

AN1

AN2

Flash MCU(HMS39C7092)

Introduction

Preliminary

1.5

Memory Map

Figure 1.3 HMS39C7092 Memory Map

Figure 1.4 Memory Map of Mode 3

APB Register

0x0900 1FFF

0x0900 1000

ASB Register

0x0900 0FFF

0x0900 0000

Reserved

0x0900 1FFF

0x0900 1800

On Chip

BOOT ROM

0x0804 FFFF

0x0804 0000

On Chip

SRAM(4KB)

0x0803 FFFF

0x0803 0000

FLASH

0x0802 FFFF

0x0800 0000

nCS0 ~ nCS7

Chip Select

Area

0x07FF FFFF

0x0000 0000

ADC

0x0900 17FF

0x0900 1700

GPIO

0x0900 16FF

0x0900 1600

UART1

0x0900 15FF

0x0900 1500

UART0

0x0900 14FF

0x0900 1400

TIMER

0x0900 13FF

0x0900 1300

INTC

0x0900 12FF

0x0900 1200

WDT

0x0900 11FF

0x0900 1100

PMU

0x0900 10FF

0x0900 1000
0x0900 0FFF

0x0900 0400

ARM7TEST

0x0900 03FF

0x0900 0300

FMI

0x0900 02FF

0x0900 0200

SMI

0x0900 01FF

0x0900 0100

MCUC

0x0900 00FF

0x0900 0000

Reserved

0xFFFF FFFF

0x0900 2000

n C S 0

0x000F FFFF

0x0000 0000

n C S 1

0x001F FFFF
0x0010 0000

n C S 2

0x002F FFFF

0x0020 0000

n C S 3

0x003F FFFF

0x0030 0000

n C S 4

0x004F FFFF

0x0040 0000

n C S 5

0x005F FFFF

0x0050 0000

n C S 6

0x006F FFFF

0x0060 0000

n C S 7

0x007F FFFF

0x0070 0000

Reserved

0x07FF FFFF

0x0080 0000

Default.

SM=0 in the PMU register.

n C S 0

0x00FF FFFF

0x0000 0000

n C S 1

0x01FF FFFF

0x0100 0000

n C S 2

0x02FF FFFF

0x0200 0000

n C S 3

0x03FF FFFF

0x0300 0000

n C S 4

0x04FF FFFF

0x0400 0000

n C S 5

0x05FF FFFF

0x0500 0000

n C S 6

0x06FF FFFF

0x0600 0000

n C S 7

0x07FF FFFF

0x0700 0000

SM=1 in the PMU register.

Remap mode (Remap =1)

SM=0 in the PMU register.

n C S 0

0x00FF FFFF

0x0000 1000

n C S 1

0x01FF FFFF

0x0100 0000

n C S 2

0x02FF FFFF

0x0200 0000

n C S 3

0x03FF FFFF

0x0300 0000

n C S 4

0x04FF FFFF

0x0400 0000

n C S 5

0x05FF FFFF

0x0500 0000

n C S 6

0x06FF FFFF

0x0600 0000

n C S 7

0x07FF FFFF

0x0700 0000

n C S 0

0x000F FFFF

0x0000 1000

n C S 1

0x001F FFFF
0x0010 0000

n C S 2

0x002F FFFF

0x0020 0000

n C S 3

0x003F FFFF
0x0030 0000

n C S 4

0x004F FFFF

0x0040 0000

n C S 5

0x005F FFFF

0x0050 0000

n C S 6

0x006F FFFF

0x0060 0000

n C S 7

0x007F FFFF

0x0070 0000

Reserved

0x07FF FFFF

0x0080 0000

Remap mode (Remap =1)

SM=1 in the PMU register.

On Chip

S R A M

0x0000 0FFF

0x0000 0000

On Chip

S R A M

0x0000 0FFF

0x0000 0000

Introduction

Flash MCU(HMS39C7092)

Preliminary

Figure 1.5 Memory Map of when Mode 4 and Mode 5

Figure 1.6 Memory Map of Mode 6 and Mode 7

n C S 0

0x 0 0 0 F F F F F

0x0003 0000

n C S 1

0x 0 0 1 F F F F F

0x0010 0000

n C S 2

0x 0 0 2 F F F F F

0x0020 0000

n C S 3

0x 0 0 3 F F F F F
0x0030 0000

n C S 4

0x 0 0 4 F F F F F

0x0040 0000

n C S 5

0x 0 0 5 F F F F F
0x0050 0000

n C S 6

0x 0 0 6 F F F F F
0x0060 0000

n C S 7

0x 0 0 7 F F F F F
0x0070 0000

R e s e r v e d

0x07FF FFFF

0x0080 0000

Default.
SM=0 in the PMU register.

n C S 0

0 x00FF FFFF

0x0003 0000

n C S 1

0 x01FF FFFF

0x0100 0000

n C S 2

0 x02FF FFFF

0x0200 0000

n C S 3

0 x03FF FFFF

0x0300 0000

n C S 4

0 x04FF FFFF

0x0400 0000

n C S 5

0 x05FF FFFF

0x0500 0000

n C S 6

0 x06FF FFFF

0x0600 0000

n C S 7

0 x07FF FFFF

0x0700 0000

SM=1 in the PMU register.

Remap mode ( Remap=1)
SM=0 in the PMU register.

n C S 0

0x00FF FFFF

0x0003 0000

n C S 1

0x01FF FFFF

0x0100 0000

n C S 2

0x02FF FFFF

0x0200 0000

n C S 3

0x03FF FFFF

0x0300 0000

n C S 4

0x04FF FFFF

0x0400 0000

n C S 5

0x05FF FFFF

0x0500 0000

n C S 6

0x06FF FFFF

0x0600 0000

n C S 7

0x07FF FFFF

0x0700 0000

n C S 0

0x 0 0 0 F F F F F

0x0003 0000

n C S 1

0x 0 0 1 F F F F F

0x0010 0000

n C S 2

0x 0 0 2 F F F F F

0x0020 0000

n C S 3

0x 0 0 3 F F F F F
0x0030 0000

n C S 4

0x 0 0 4 F F F F F
0x0040 0000

n C S 5

0x 0 0 5 F F F F F
0x0050 0000

n C S 6

0x 0 0 6 F F F F F
0x0060 0000

n C S 7

0x 0 0 7 F F F F F
0x0070 0000

R e s e r v e d

0x07FF FFFF

0x0080 0000

Remap mode (Remap=1)
SM=1 in the PMU register.

F L A S H

( 1 9 2 K B )

0x0002 FFFF

0x0000 1000

F L A S H

( 1 9 2 K B )

0x0002 FFFF

0x0000 1000

F L A S H

( 1 9 2 K B )

0 x0002 FFFF

0x0000 0000

F L A S H

( 1 9 2 K B )

0x0002 FFFF

0x0000 0000

On Chip

S R A M ( 4 K B )

0x0000 0FFF

0x0000 0000

On Chip

S R A M ( 4 K B )

0x0000 0FFF

0x0000 0000

nCS0

0 x000F FFFF

0x0000 0100

nCS1

0 x001F FFFF

0x0010 0000

nCS2

0 x002F FFFF

0x0020 0000

nCS3

0 x003F FFFF

0x0030 0000

nCS4

0 x004F FFFF

0x0040 0000

nCS5

0 x005F FFFF

0x0050 0000

nCS6

0 x006F FFFF

0x0060 0000

nCS7

0 x007F FFFF

0x0070 0000

Reserved

0 x07FF FFFF

0x0080 0000

Default.

SM=0 in the PMU register.

nCS0

0 x00FF FFFF

0x0000 0100

nCS1

0 x01FF FFFF

0x0100 0000

nCS2

0 x02FF FFFF

0x0200 0000

nCS3

0 x03FF FFFF

0x0300 0000

nCS4

0 x04FF FFFF

0x0400 0000

nCS5

0 x05FF FFFF

0x0500 0000

nCS6

0 x06FF FFFF

0x0600 0000

nCS7

0 x07FF FFFF

0x0700 0000

SM=1 and OnFLASH =0

in the PMU register.

SM=0 and On FLASH=1

in the PMU register.

nCS0

0x00FF FFFF

0x0003 0000

nCS1

0x01FF FFFF

0x0100 0000

nCS2

0x02FF FFFF

0x0200 0000

nCS3

0x03FF FFFF

0x0300 0000

nCS4

0x04FF FFFF

0x0400 0000

nCS5

0x05FF FFFF

0x0500 0000

nCS6

0x06FF FFFF

0x0600 0000

nCS7

0x07FF FFFF

0x0700 0000

nCS0

0x000F FFFF

0x0003 0000

nCS1

0x001F FFFF

0x0010 0000

nCS2

0x002F FFFF

0x0020 0000

nCS3

0x003F FFFF

0x0030 0000

nCS4

0x004F FFFF

0x0040 0000

nCS5

0x005F FFFF

0x0050 0000

nCS6

0x006F FFFF

0x0060 0000

nCS7

0x007F FFFF

0x0070 0000

Reserved

0x07FF FFFF

0x0080 0000

SM=1 and OnFLASH =1

in the PMU register.

FLASH

(192KB)

0x0002 FFFF

0x0000 1000

FLASH

(192KB)

0x0002 FFFF

0x0000 1000

On Chip

Boot ROM
(256Byte)

0 x0000 00FF

0x0000 0000

On Chip

Boot ROM
(256Byte)

0 x0000 00FF

0x0000 0000

0x0000 0FFF

0x0000 0000

0x0000 0FFF

0x0000 0000

ARM7TDMI Core

Flash MCU(HMS39C7092)

Preliminary

2.1

General Description

The ARM7TDMI is a member of the ARM family of general-purpose 32bit

microprocessors, which offers high performance for very low power consumption and

price. This processor employs a unique architectural strategy known as THUMB,

which makes it ideally suited to high volume applications with memory restrictions or

applications where code density is an issue.

The key idea behind THUMB is a super reduced instruction set. Essentially, the

ARM7TDMI has two instruction sets, the standard 32bit ARM set and 16bit THUMB

set. The THUMB set's 16bit instruction length allows it to approach twice the density

of standard ARM code while retaining most of the ARM's performance advantage

over a traditional 16bit processor by using 16bit registers. This is possible because

THUMB code operates on the same 32bit register set as ARM code.

See also ARM7TDMI Datasheet (ARM DDI 0029E) for detail.

2.2

Feature

32bit RISC architecture

Low power consumption

ARM7TDMI core with;

- On-chip ICEbreaker debug support

- 32bit x 8 hardware multiplier

- Thumb decompressor

Utilizes the ARM7TDMI embedded processor

- High performance 32 bit RISC architecture

- High density 16 bit instruction set (THUMB code)

Fully static operation : 0 ~ 80MHz

3-stage pipeline architecture (Fetch, decode, and execution stage)

Enhanced ARM software toolkit

THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

Flash MCU(HMS39C7092)

ARM7TDMI Core

Preliminary

2.3

Core Block Diagram

ICE

Breaker

Scan

Chain 0

RANGEOUT0
RANGEOUT1
ESTERN1
EXTERN0

TAP Controller

TCK

TMS

nTRST

TDI

TDO

TASPM [3:0]

IR [3:0]

SCREG [3:0]

Address Register

ALE

ABE

[

31:0]

Address

Incrementer

(31 x 32-bit registers)

(6 status registers)

32 x 8

Multiplier

Barrel Shifter

32-bit ALU

Write Data Register

Instruction Pipeline

& Read Data Register

& Thumb Instruction Decoder

nENOUT

nENIN

DBE

[

31:0]

Core

DBGRQI

BREAKPTI

DBGACK

ECLK

nEXEC

ISYNC

BL [3:0]

APE

MCLK

nWAIT

nIRQ

nFIQ

nRESET

ABORT

SEQ

LOCK

nCPI

CPA

CPB

nM [4:0]

TBE

TBIT

HIGHZ

Instruction

Decoder

Control

Logic

Scan

Control

D [0:31]
DIN [0:31]
DOUT [0:31]

Bus

Splitter

nRW

MAS [1:0]

nTRANS

nMREQ

nOPC

A [0:31]

Scan

Chain 1

ScanChain2

Figure 2.1 ARM7TDMI Core Block Diagram

ARM7TDMI Core

Flash MCU(HMS39C7092)

Preliminary

2.4

Instruction Set

2.4.1

ARM Instruction

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Cond 0 0 I Opcode S

Operand

Data Processing / PSR Transfer

Cond 0 0 0 0 0 0 A S

1 0 0 1

Multiply

Cond 0 0 0 0 1 U A S RdHi

RdLo

1 0 0 1

Multiply Long

Cond 0 0 0 1 0 B 0 0

0 0 0 0 1 0 0 1

Single Data Swap

Cond 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1

Branch and Exchange

Cond 0 0 0 P U 0 W L

0 0 0 0 1 S H 1

Halfword Data Transfer: register offset

Cond 0 0 0 P U 1 W L

Offset 1 S H 1 Offset

Halfword Data Transfer: immediate offset

Cond 0 1 I P U B W L

Offset

Single Data Transfer

Cond 0 1 1

Undefined

Cond 1 0 0 P U S W L

Block Data Transfer

Cond 1 0 1 L

Offset

Branch

Cond 1 1 0 P U N W L

CRd

CP#

Offset

Coprocessor Data Transfer

Cond 1 1 1 0 CP Opc

CRn

CRd

CP#

CP 0 CRm

Coprocessor Data Operation

Cond 1 1 1 0 CP

Opc

L CRn

CP#

CP 1 CRm

Coprocessor Register Transfer

Cond 1 1 1 1

Ignored by processor

Software Interrupt

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Figure 2.2 ARM instruction set formats

Flash MCU(HMS39C7092)

ARM7TDMI Core

Preliminary

Table 2.1 The ARM Instruction set

Mnemonic

Instruction

Action

ADC

Add with carry

Rd := Rn + Op2 + Carry

ADD

Add

Rd := Rn + Op2

AND

AND

Rd := Rn AND Op2

Branch

R15 := address

BIC

Bit Clear

Rd := Rn AND NOT Op2

Branch with Link

R14 := R15, R15 := address

Branch and Exchange

R15 := Rn, T bit := Rn[0]

CDP

Coprocessor Data Processing

(Coprocessor-specific)

CMN

Compare Negative

CPSR flags := Rn + Op2

CMP

Compare

CPSR flags := Rn - Op2

EOR

Exclusive OR

Rd := (Rn AND NOT Op2) OR (op2 AND NOT

Rn)

LDC

Load coprocessor from memory

Coprocessor load

LDM

Load multiple registers

Stack manipulation (Pop)

LDR

Load register from memory

Rd := (address)

MCR

Move CPU register to coprocessor

cRn := rRn {<op>cRm}

MLA

Multiply Accumulate

Rd := (Rm * Rs) + Rn

MOV

Move register or constant

Rd : = Op2

MRC

Move from coprocessor register to

CPU register

Rn := cRn {<op>cRm}

MRS

Move PSR status/flags to register

Rn := PSR

MSR

Move register to PSR status/flags

PSR := Rm

MUL

Multiply

Rd := Rm * Rs

MVN

Move negative register

Rd := 0XFFFFFFFF EOR Op2

ORR

Rd := Rn OR Op2

RSB

Reverse Subtract

Rd := Op2 - Rn

RSC

Reverse Subtract with Carry

Rd := Op2 - Rn - 1 + Carry

SBC

Subtract with Carry

Rd := Rn - Op2 - 1 + Carry

STC

Store coprocessor register to memory address := CRn

STM

Store Multiple

Stack manipulation (Push)

STR

Store register to memory

<address> := Rd

SUB

Subtract

Rd := Rn - Op2

SWI

Software Interrupt

OS call

SWP

Swap register with memory

Rd := [Rn], [Rn] := Rm

TEQ

Test bitwise equality

CPSR flags := Rn EOR Op2

TST

Test bits

CPSR flags := Rn AND Op2

ARM7TDMI Core

Flash MCU(HMS39C7092)

Preliminary

ARM state General Registers and Program Counter

System & User

FIQ

Supervisor

Abort

IRQ

Undefined

R8_fiq

R9_fiq

R10

R10_fiq

R10

R11

R11_fiq

R11

R12

R12_fiq

R12

R13

R13_fiq

R13_svc

R13_abt

R13_irq

R13_und

R14

R14_fiq

R14_svc

R14_abt

R14_irq

R14_und

R15 (PC)

ARM state Program Status Registers

CPSR

SPSR_fiq

SPSR_svc

SPSR_abt

SPSR_irq

SPSR_und

= banked register

Figure 2.3 Register Organization in ARM state

Flash MCU(HMS39C7092)

ARM7TDMI Core

Preliminary

2.4.2

THUMB Instruction

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 0 0 0

Offset5

Move shifted register

2 0 0 0 1 1 I Op Rn/offset3

Add/subtract

3 0 0 1

Offset8

Move/compare/add/subtract immediate

4 0 1 0 0 0 0

ALU operation

5 0 1 0 0 0 1

Op H1 H2 Rs/Hs

Rd/Hd

Hi register operations/branch exchange

6 0 1 0 0 1

Word8

PC-relative load

7 0 1 0 1 L B 0

Load/store with register Offset

8 0 1 0 1 H S 1

Load/store sign-extended byte/halfword

9 0 1 1 B L

Offset5

Load/store with immediate

10 1 0 0 0 L

Offset5

Load/store halfword

11 1 0 0 1 L

Word8

SP-relative load/store

12 1 0 1 0 SP

Word8

Load address

13 1 0 1 1 0 0 0 0 S

SWord7

Add offset to stack pointer

14 1 0 1 1 L 1 0 R

Rlist

Push/pop registers

15 1 1 0 0 L

Rlist

Multiple load/store

16 1 1 0 1

Cond

Soffset8

Conditional branch

17 1 1 0 1 1 1 1 1

Value8

Software Interrupt

18 1 1 1 0 0

Offset11

Unconditional branch

19 1 1 1 1 H

Offset11

Long branch with link

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Figure 2.4 THUMB instruction set formats

ARM7TDMI Core

Flash MCU(HMS39C7092)

Preliminary

Table 2.2 THUMB instruction set opcodes

Mnemonic

Instruction

Lo reg. oper.

Hi reg. oper

Condition code set

ADC

Add with Carry

ADD

Add

AND

AND

ASR

Arithmetic Shift Right

Unconditional branch

B xx

Conditional branch

BIC

Bit Clear

Branch and Link

Branch and Exchange

CMN

Compare Negative

CMP

Compare

EOR

EOR

LDMIA

Load multiple

LDR

Load word

LDRB

Load byte

LDRH

Load halfword

LSL

Logical Shift Left

LDSB

Load sign-extended byte

LDSH

Load sign-extended Halfword

LSR

Logical Shift Right

MOV

Move register

MUL

Multiply

MVN

Move Negative register

NEG

Negate

ORR

POP

Pop registers

PUSH

Push registers

ROR

Rotate Right

SBC

Subtract with Carry

STMIA

Store Multiple

STR

Store word

STRB

Store byte

STRH

Store halfword

SWI

Software Interrupt

SUB

Subtract

TST

Test bits

Flash MCU(HMS39C7092)

ARM7TDMI Core

Preliminary

THUMB state General Registers and Program Counter

System & User

FIQ

Supervisor

Abort

IRQ

Undefined

SP_fiq

SP_svc

SP_abt

SP_irq

SP_und

LR_fiq

LR_svc

LR_abt

LR_irq

LR_und

THUMB state Program Status Registers

CPSR

SPSR_fiq

SPSR_svc

SPSR_abt

SPSR_irq

SPSR_und

= banked register

Figure 2.5 Register Organization in THUMB state

THUMB state

ARM state

R10

R11

R12

Stack Pointer (SP)

Stack Pointer (R13)

Link Register (LR)

Link Register (R14)

Program Counter (PC)

Program Counter (R15)

CPSR

SPSR

Figure 2.6 Mapping of THUMB state registers onto ARM state registers.

registers

Hi registers

ARM7TDMI Core

Flash MCU(HMS39C7092)

Preliminary

Table 2.3 Condition code summary

Code

Suffix

Flags

Meaning

0000

set equal

0001

clear not equal

0010

set unsigned higher or same

0011

clear unsigned lower

0100

set negative

0101

clear positive or zero

0110

set overflow

0111

clear no overflow

1000

set and Z clear unsigned higher

1001

clear or Z set unsigned lower or same

1010

equals V greater or equal

1011

not equal to V less than

1100

clear AND (N equals V) greater than

1101

set OR (N not equal to V) less than or equal

1110

(Ignored)

always

2.4.3

The Program Status Registers

The ARM7TDMI contains Current Program Status Register (CPSR), plus five Saved

Program Status Register (SPSRs) for use by exception handlers. These registers

hold information about the most recently performed ALU operation control the

enabling and disabling of interrupts set the processor operating mode

The arrangement of bits is shown in Fig. 2.7 Program status register format.

Condition code flags (reserved) Control bits

31 30 29 28 27 26 25 24 23

.... ... ...

M4 M3 M2 M1 M0

Overflow

Mode bits

Carry / Borrow / Extend

State bit

Zero

FIQ disable

Negative / Less Than

IRQ disable

Figure 2.7 Program status register format

Flash MCU(HMS39C7092)

ARM7TDMI Core

Preliminary

2.4.3.1

The condition code flags

The N,Z,C and V bits are the condition code flags. These may be changed as a

result of arithmetic and logical operations, and may be tested to determine whether

an instruction should be executed.

In ARM state, all instructions may be executed conditionally : see table 2.3 in chapter

2.4.2.

In THUMB state, only the Branch instruction is capable of conditional execution

2.4.3.2

The control bits

The bottom 8 bits of a PSR(incorporating I,F,T and M[4:0]) are known collectively as

the control bits. These will change when an exception arises. If the processor is

operating in a privileged mode, they can also be manipulated by software.

The T bit

This reflects the operating states. When this bit is

set, the processor is executing in THUMB state,

otherwise it is executing in ARM state.

Note that the software must never change the state

of the TBIT in the CPSR. If this happens, the

processor will enter an unpredictable state.

Interrupt disable bits

The I and F bits are the interrupt disable bits. When

set, these disable the IRQ and FIQ interrupts

respectively.

The mode bits

The M4, M3, M2, M1 and M0 bits (M[4:0]) are the

mode bits. These determine the processor's

operating mode, as shown in following table 2.4.

Not all combinations of the mode bits define a valid

processor mode. Only those explicitly described

shall be used. The user should be aware that if

any illegal value is programmed into the mode bits,

M{4:0}

, then the processor will enter an

unrecoverable state. If this occurs, reset should be

applied.

Reserved bits

The remaining bits in the PSRs are reserved.

When changing a PSR's flag or control bits, you must

ensure these unused bits are not altered. Also,

your program should not rely on them containing

specific values, since in future processors they may

read as one or zero.

Flash MCU(HMS39C7092)

ARM7TDMI Core

Preliminary

2.4.4

ARM pseudo-instructions

ADR

The ADR pseudo-instruction loads a program-relative or register-relative address into a register.

Syntax

The syntax of ADR is:

ADR{ condition} register, expression

where:

register is the register to load.

expression is a program-relative or register-relative expression that evaluates to:

· a non word-aligned address within 255 bytes

· a word-aligned address within 1020 bytes.

The address can be either before or after the address of the instruction or the base

Usage

ADR always assembles to one instruction. The assembler attempts to produce a single ADD or

SUB instruction to load the address. If the address cannot be constructed in a single instruction,

an error is generated and the assembly fails.

Use the ADRL pseudo-instruction to assemble a wider range of effective addresses.

If expression is program-relative, it must evaluate to an address in the same code area as the

ADR pseudo-instruction. Otherwise the address may be out of range after linking.

Example

start

MOV r0,#10
ADR r4,start

; => SUB r4,pc,#0xc

ARM7TDMI Core

Flash MCU(HMS39C7092)

Preliminary

ADRL

The ADRL pseudo-instruction loads a program-relative or register-relative address into a

than ADR because it generates two data processing instructions.

Syntax

The syntax of ADRL is:

ADRL{ condition} register, expression

where:

register is the register to load.

expression is a register-relative or program-relative expression that evaluates to:

· a non word-aligned address within 64KB

· a word-aligned address within 256KB.

The address can be either before or after the address of the instruction or the base

Usage

ADRL always assembles to two instructions. Even if the address can be reached in a single

instruction, a second, redundant instruction is produced.

If the assembler cannot construct the address in two instructions, it generates an error message

and the assembly fails. See LDR ARM pseudo-instruction for information on loading a wider

range of addresses. See also Chapter 5 Basic Assembly Language Programming in the ARM

Software Development Toolkit User Guide.

If expression is program-relative, it must evaluate to an address in the same code area as the

ADRL pseudo-instruction. Otherwise the address may be out of range after linking.

Note

ADRL is not available when assembling Thumb instructions. Use it only in ARM code.

Example

start

MOV r0,#10

ADRL r4,start + 60000

; => ADD r4,pc,#0xe800

; ADD r4,r4,#0x254

Flash MCU(HMS39C7092)

ARM7TDMI Core

Preliminary

LDR

The LDR pseudo-instruction loads a register with either:

· a 32-bit constant value

· an address.

Note

This section describes the LDR pseudo-instruction only. Refer to the ARM Architectural

Reference Manual for information on the LDR instruction.

Syntax

The syntax of LDR is:

LDR{ condition} register, =[ expression | label-expression]

where:

condition is an optional condition code.

register is the register to be loaded.

expression evaluates to a numeric constant:

· If the value of expression is within range of a MOV or MVN instruction,

the assembler generates the appropriate instruction.

· If the value of expression is not within range of a MOV or MVN

instruction, the assembler places the constant in a literal pool and

generates a program-relative LDR instruction that reads the constant

from the literal pool.

The offset from the pc to the constant must be less than 4KB. You are responsible

for ensuring that there is a literal pool within range. See LTORG directive for more

information.

label-expression is a program-relative or external expression. The assembler places

the value of label-expression in a literal pool and generates a program-relative LDR

instruction that loads the value from the literal pool.

The offset from the pc to the value in the literal pool must be less than 4KB. You are

responsible for ensuring that there is a literal pool within range. See LTORG

directive for more information.

If label-expression is an external expression, or is not contained in the current area,

the assembler places a linker relocation directive in the object file. The linker

ensures that the correct address is generated at link time.

Usage

The LDR pseudo-instruction is used for two main purposes:

· to generate literal constants when an immediate value cannot be moved into a

· to load a program-relative or external address into a register. The address remains

valid regardless of where the linker places the AOF area containing the LDR.

Refer to Chapter 5 Basic Assembly Language Programming in the ARM Software

Development Toolkit User Guide for a more detailed explanation of how to use LDR,

and for more information on MOV and MVN.

Example

LDR r1,=0xfff

; loads 0xfff into r1

;

LDR r2,=place

; loads the address of

; place into r2

ARM7TDMI Core

Flash MCU(HMS39C7092)

Preliminary

LDR

The thumb LDR pseudo-instruction loads a low register with either:

· a 32-bit constant value

· an address.

Note

This section describes the LDR pseudo-instruction only. Refer to the ARM Architectural

Reference Manual for information on the LDR instruction.

Syntax

The syntax of LDR is:

LDR register, =[ expression | label-expression]

where:

register is the register to be loaded. LDR can access the low registers (r0-r7) only.

expression evaluates to a numeric constant:

· If the value of expression is within range of a MOV instruction, the

assembler generates the instruction.

· If the value of expression is not within range of a MOV instruction, the

assembler places the constant in a literal pool and generates a

program-relative LDR instruction that reads the constant from the literal

pool.

The offset from the pc to the constant must be positive and less than

1KB. You are responsible for ensuring that there is a literal pool within

range. See LTORG directive for more information.

label-expression is a program-relative or external expression. The assembler places

the value of label-expression in a literal pool and generates a program-relative LDR

instruction that loads the value from the literal pool.

The offset from the pc to the value in the literal pool must be positive and less than

1KB. You are responsible for ensuring that there is a literal pool within range. See

LTORG directive for more information.

If label-expression is an external expression, or is not contained in the current area,

the assembler places a linker relocation directive in the object file. The linker

ensures that the correct address is generated at link time.

Usage

The LDR pseudo-instruction is used for two main purposes:

· to generate literal constants when an immediate value cannot be

moved into a register because it is out of range of the MOV instruction.

· to load a program-relative or external address into a register. The

address remains valid regardless of where the linker places the AOF

area containing the LDR.

Refer to Chapter 5 Basic Assembly Language Programming in the ARM Software

Development Toolkit User Guide for a more detailed explanation of how to use LDR,

and for more information on MOV.

Example

LDR r1, =0xfff

; loads 0xfff into r1

;

LDR r2, = labelname ; loads the address of

; labelname into r2

BUS controller

Flash MCU(HMS39C7092)

Preliminary

3.1

Overview

The HMS39C7092 has an on-chip bus controller that manages the external address

space divided into eight areas, which can attaches SRAM, ROM, Flash-memory or

off-chip peripheral devices. The bus specifications, such as bus width and number of

access states, can be set independently for each area, enabling multiple memories to

be connected easily.

3.1.1

Features

The features of the bus controller are listed below.

8-bit access or 16-bit access can be selected for each area

(In THUMB mode, only 16-bit accessing of external code memory is allowed)

Active low chip select signals (nCS

to nCS

) can be output for area 0 to 7

Bus specifications can be set independently for each area

Support Little-Endian Memory Format

Variable wait states (up to 16 waits)

Bus transfers can be extended using the nWAIT signal. The nWAIT signal

is active LOW

Each area is 16MB(when SM='0' in PMU), or 1MB(when SM='1' in PMU) in

Size and can be programmed individually.

Figure 3.1 Block Diagram of the Bus Controller

Main State

Machine

External BUS

Control
Signals

Wait State
Controller

Bus

Arbiter

Address

Decoder

BUS control

Register

Pack

(BCRn)

Internal Address BUS

Bus reset / Clock signal

Access Control signal

BUS size signals

BUS slave signals

Internal signals

Configuration Reg.

Wait

nCS[7:0]

MD[2:0]

nAS

nHWR

nLWR

nRD

nWAIT

nBREQ

nBACK

Internal Data BUS

BUS controller

Flash MCU(HMS39C7092)

Preliminary

3.3

Operation

3.3.1

Area Division

The external address space is divided into area 0 to 7. Each area has a size of 16-

Mbyte modes, or 1-Mbyte modes. Figure 3.2 shows a general view of the memory

map.

Figure 3.2 Access Area Map for Each Operating Mode

Chip select signals (nCS

to nCS

) can be output for area 0 to 7. The bus

specifications for each area are selected in BCR0 to BCR7.

0x000F FFFF

0x001F FFFF

0x002F FFFF

0x003F FFFF

0x004F FFFF

0x005F FFFF

0x006F FFFF

0x007F FFFF

nCS1

nCS2

nCS3

nCS4

nCS5

nCS6

nCS7

Reserved

0x07FF FFFF

a) 16- Mbyte modes (Default)

SM=0 in the PMU

0x00FF FFFF

nCS1

0x01FF FFFF

nCS2

0x02FF FFFF

nCS3

0x03FF FFFF

nCS4

0x04FF FFFF

nCS5

0x05FF FFFF

nCS6

0x06FF FFFF

nCS7

0x07FF FFFF

b) 1-Mbyte mode

SM=1 in the PMU

0x0080 0000

0x0070 0000

0x0060 0000

0x0050 0000

0x0040 0000

0x0030 0000

0x0020 0000

0x0010 0000

0x0000 0000

0x0700 0000

0x0600 0000

0x0500 0000

0x0400 0000

0x0300 0000

0x0200 0000

0x0100 0000

0x0000 0000

nCS0

nCS1

Flash MCU(HMS39C7092)

BUS controller

Preliminary

3.3.2

Area Division

The external space bus specifications consist of two elements: (1) bus width, (2)

number of wait states.

The bus width and number of access states for on-chip memory and registers are

fixed, and are not affected by the bus controller.

Bus Width:

A bus width of 8 or 16 bits can be selected with MemWidth bit-field in

BCR0 to 7. An area for which an 8-bit bus is selected functions as an 8-bit access

space, and an area for which a 16-bit bus is selected functions as a 16-bit access

space.

If all areas are designed for 8-bit access, 8-bit bus mode is set; if any area is

designed for 16-bit access, 16-bit bus mode is set.

Number of Wait States:

One to 16 wait states can be selected with NormalWait bit-

field in BCR0 to 7. When using nWAIT signal, then wait state is the minimum over

two-states.

3.3.3

Chip Select Signals

For each of areas 0 to 7, the HMS39C7092 can output a chip select signal (nCS

nCS

) that goes low when the corresponding area is selected in expanded mode.

From Figure 3.3 to Figure 3.15 shows the output timing of nCS

0 ~ 7

signal.

Output of nCS

to nCS

Output of nCS

to nCS

is enabled or disabled in the data

direction register of the corresponding port.

BUS controller

Flash MCU(HMS39C7092)

Preliminary

3.4

Basic Bus Interface

3.4.1

Overview

The HMS39C7092 has only a basic interface that allows direct connection of ROM,

SRAM, off-chip peripheral devices and so on.

3.4.2

Byte Lane Write Control

Data size for the CPU and other internal masters are byte(8-bit), half-word(16-bit),

word(32-bit). The bus controller has a data alignment function, and when accessing

external space, controls whether the upper data bus (D

to D

) or lower data bus (D

to D

) is used according to the bus specifications for the area being accessed (8-bit

access area or 16-bit access area) and the data size.

8-Bit Access Areas:

Figure 3.3 shows data alignment control for 8-bit access space.

With 8-bit access space, the lower data bus (D

to D

) is always used for accesses.

The amount of data that can be accessed at one time is one byte: a half-word access

is performed as two byte accesses, and a word access, as four byte accesses.

Figure 3.3 Access Size and Data Alignment Control (8-Bit Access Area)

Byte size

Half-word size

Word size

Lower Byte

1st bus cycle

Lower Byte

2nd bus cycle

Lower Byte

1st bus cycle

Lower Byte

2nd bus cycle

Lower Byte

3rd bus cycle

Lower Byte

4th bus cycle

Lower Byte

Flash MCU(HMS39C7092)

BUS controller

Preliminary

16-Bit Access Areas:

Figure 3.4 shows data alignment control for 16-bit access

areas. With 16-bit access areas, the lower data bus (D

to D

) and higher data bus

to D

) are used for accesses. The amount of data that can be accessed at one

time is one byte or one half-word, and a word access is executed as two half-word

accesses.

Figure 3.4 Access Size and Data Alignment Control (16-Bit Access Area)

nHWR

, nLWR signals are generated according to the memory transfer width,

external memory width, A0, and the access sequencing. The following table shows

the basic coding example assuming 16-bit external memory:

Table 3.3 Byte Lane condition by XA[0]

CPU access Size

nHWR

nLWR

Number of

Access

Word (32bit)

Low

Half-word (16-bit)

Low

Byte (8bit)

High

Low

Byte (8bit)

Low

High

Byte size

Half-word size

Word size

Lower Byte

1st bus cycle

Lower Byte

2nd bus cycle

Lower Byte

Even Address

Odd Address

Upper Byte

BUS controller

Flash MCU(HMS39C7092)

Preliminary

3.4.4

Wait Control

When accessing external space, the HMS39C7092 can extend the bus cycle by

inserting wait states (Tw). There are two ways of inserting wait states: (1) program

wait insertion and (2) pin wait insertion using the nWAIT pin.

Program Wait Insertion:

From 1 to 16 wait states can be inserted automatically

between the T2 state and T3 state on an individual basis in each access space,

according to the settings of NormWait bit fields in BCR0~7.

Pin Wait Insertion:

When external space is accessed in this state, a program wait is

first inserted. If the nWAIT pin is low at the falling edge of XIN in the last T2 or Tw

state, another Tw state is inserted. If the nWAIT pin is held low, Tw states are

inserted until it goes high.

Figure 3.17 shows an example of the timing for insertion of one program wait state in

3-wait-state space.

Figure 3.17 Example of Wait State Insertion Timing.

XIN

nCS

Address

nAS

Data

nHWR

nLWR

nRD

`1'

Valid

nWAIT

Flash MCU(HMS39C7092)

BUS controller

Preliminary

3.4.5

Bus Arbiter

The bus controller has a built-in bus arbiter that arbitrates between different bus

masters. The bus master can be either the CPU or an external bus master. When a

bus master has the bus right it can carry out read and write operations. Each bus

master uses a bus request signal to request the bus right. At fixed times the bus

arbiter determines priority and uses a bus acknowledge signal to grant the bus to a

bus master, which can operate using the bus.

The bus arbiter checks whether the bus request signal from a bus master is active or

inactive, and returns an acknowledge signal to the bus master. When two or more

bus masters request the bus, the highest-priority bus master receives an

acknowledge signal can continue to use the bus until the acknowledge signal is

deactivated.

The bus master priority order is:

(High)

External bus master > ARM CPU

(Low)

The bus arbiter samples the bus request signals and determines priority at all times,

but it does not always grant the bus immediately, even when it receives a bus request

a bus master with higher priority than the current bus master. Each bus master has

certain times at which it can release the bus to a higher-priority bus master.

ARM CPU:

The ARM CPU is the lowest-priority bus master. If an external bus master

requests the bus while the CPU has the right, the bus arbiter transfers the bus right to

the bus master that requested it. The bus right is transferred at the following times:

The bus right is transferred at the boundary of a bus cycle. If word data is

accessed by two consecutive byte accesses, however, the bus right is not

transferred between the two byte accesses.

If another bus master requests the bus while the CPU is performing internal

operations, such as executing a multiply or divide instruction, the bus right

is transferred immediately. The CPU continues its internal operations.

If another bus master requests the bus while the CPU is in power down

mode, the bus right is transferred immediately.

External Bus Master:

The HMS39C7092 can be always released to an external bus

master. The external bus master has highest priority, and requests the bus right from

the bus arbiter driving the nBREQ signal low. Once the external bus master acquires

the bus, it keeps the bus until the nBREQ signal goes to high. While the bus is

released to an external bus master, the HMS39C7092 chip holds the address bus,

data bus, bus control signals (nAS, nRD, nHWR, and nLWR), and chip select signals

(nCS0 to 7), and holds the nBACK pin in the low output state.

The bus arbiter samples the nBREQ pin at the rise of the system clock (XIN). If

nBREQ

is low, the bus is released to the external bus master at the appropriate

opportunity. The nBREQ signal should be held low until the nBACK goes low.

When the nBREQ pin is high in two consecutive samples, the nBACK pin is driven

high to end the bus-release cycle.

MCU controller

Flash MCU(HMS39C7092)

Preliminary

4.1

General Description

The MCU Controller (MCUC) is composed of 11 multi-function pin multiplex control

signal registers and device code register.

4.2

Pin Function Description

Table 4.1 shows Pin function description.

Table 4.1 Pin Function Descriptions

NAME

Port

No.

Multiplexed functions

NAME

Port

No.

Multiplexed functions

PA0

TCLKA

P40

PA1

TCLKB

P41

PA2

TCLKC, TIOCA0

P42

PA3

TCLKD, TIOCB0

P43

PA4

A23, TIOCA1

P44

PA5

A22, TIOCB1

P45

PA6

A21, TIOCA2

P46

Port A

PA7

A20, TIOCB2

Port 4

P47

PB0

nCS7, TIOCA3

P50

A16

PB1

nCS6, TIOCB3

P51

A17

PB2

nCS5, TUICA4

P52

A18

PB3

nCS4, TIOCB4

Port 5

P53

A19

PB4

TMS

P60

nWAIT

PB5

TDO

P61

nBREQ

PB6

TDI

P62

nBACK

Port B

PB7

TCK

P63

nAS

P10

P64

nRD

P11

P65

nHWR

P12

P66

nLWR

P13

Port 6

P67

CLKO

P14

P70

AN0

P15

P71

AN1

P16

P72

AN2

Port 1

P17

P73

AN3

P20

P74

AN4

P21

P75

P22

A10

P76

TIOCA5, nIRQ6

P23

A11

Port 7

P77

TIOCB5, nIRQ7

P24

A12

P80

nIRQ0

P25

A13

P81

nCS3, nIRQ1

P26

A14

P82

nCS2, nIRQ2

Port 2

P27

A15

P83

nCS1, nIRQ3

P30

Port 8

P84

nCS0

P31

P90

TxD0

P32

D10

P91

RxD0

P33

D11

P92

TxD1

P34

D12

P93

RxD1

P35

D13

XP96*

XFVPPD*

P36

D14

Port 9

P97

nTRST

Port 3

P37

D15

*XP96/XFVPPD pin is package bonding options

Note: Each port functions are changed by Mode-setting or user definition.

Default functions are showed in 4.3.2 PINMUX Register

Flash MCU(HMS39C7092)

MCU controller

Preliminary

4.3

Register Description

4.3.1

Register Memory Map

Table 4.2 is the memory map of the MCU Controller. The base address of MCU

control Register is 0x0900_0000. Table 4.3 shows the initial value in each mode. The

initial values are different by operation mode.

Table 4.2 Memory map of the MCU Controller

Reg.

I/O

OFFSET

Dir.

Description

PAMR

0x0000

R/W Pin MUX Control Register for Port A

PBMR

0x0004

R/W Pin MUX Control Register for Port B

P1MR

0x0008

R/W Pin MUX Control Register for Port 1

P2MR

0x000C

R/W Pin MUX Control Register for Port 2

P3MR

0x0010

R/W Pin MUX Control Register for Port 3

P4MR

0x0014

R/W Pin MUX Control Register for Port 4

P5MR

0x0018

R/W Pin MUX Control Register for Port 5

P6MR

0x001C

R/W Pin MUX Control Register for Port 6

P7MR

0x0020

R/W Pin MUX Control Register for Port 7

P8MR

0x0024

R/W Pin MUX Control Register for Port 8

P9MR

0x0028

R/W Pin MUX Control Register for Port 9

DCR

0x002C

MCU Device Code Register

Table 4.3 MCU Controller Initial values in each mode

Reg.

Mode

3,4

MODE

5,7

MODE

PAMR

0x0000

0x1540

PBMR

0x0000

0x0055

0x0000

P1MR

0x0000

0x00FF

0x0000

P2MR

0x0000

0x00FF

0x0000

P3MR

0x00FF

0x0000

0x00FF

0x0000

P4MR

0x0000

0x00FF

0x0000

P5MR

0x0000

0x000F

0x0000

P6MR

0x0000

0x03FF

0x0000

P7MR

0x0000

P8MR

0x0000

0x00D4

0x0000

P9MR

0x0000

DCR

0x39437092

MCU controller

Flash MCU(HMS39C7092)

Preliminary

4.3.2

PINMUX Register

PAMR

Port A Multiplex Register (

0x0900_0000 R/W)

b31 b14

b13 b12 b11 b10 b9

PAMR

Reserved

PA7

PA6

PA5

PA4

PA3

PA2

PA1 PA0

Initial value : depend on operating mode (refer to Table 4.3)

PA7

00 : A20

01 : TIOCB2

1x : PA7

PA6

00 : A21

01 : TIOCA2

1x : PA6

PA5

00 : A22

01 : TIOCB1

1x : PA5

PA4

00 : A23

01 : TIOCA1

1x : PA4

PA3

00 : TCLKD

01 : TIOCB0

1x : PA3

PA2

00 : TCLKC

01 : TIOCA0

1x : PA2

PA1

: TCLKB

: PA1

PA0

: TCLKA

: PA2

PBMR

Port B Multiplex Register (

0x0900_0004 R/W)

b31 b14 b11 b10 b9

PBMR

Reserved

PB7 PB6 PB5 PB4

PB3

PB2

PB1

PB0

Initial value : depend on operating mode (refer to Table 4.3)

PB7

: TCK

: PB7

PB6

: TDI

: PB6

PB5

: TDO

: PB5

PB4

: TMS

: PB4

PB3

00 : /CS4

01 : TIOCB4

1x : PB3

PB2

00 : /CS5

01 : TIOCA4

1x : PB2

PB1

00 : /CS6

01 : TIOCB3

1x : PB1

PB0

00 : /CS7

01 : TIOCA3

1x : PB0

Flash MCU(HMS39C7092)

MCU controller

Preliminary

P1MR

Port 1 Multiplex Register (

0x0900_0008 R/W)

b31 b8

P1MR

Reserved

P17 P16 P15 P14 P13 P12 P11 P10

Initial value : depend on operating mode (refer to Table 4.3)

P17

: A7

: P17

P16

: A6

: P16

P15

: A5

: P15

P14

: A4

: P14

P13

: A3

: P13

P12

: A2

: P12

P11

: A1

: P11

P10

: A0

: P10

P2MR

Port B Multiplex Register (

0x0900_000C R/W)

b31 b8

P2MR

Reserved

P27 P26 P25 P24 P23 P22 P21 P20

Initial value : depend on operating mode (refer to Table 4.3)

P27

: A15

: P27

P26

: A14

: P26

P25

: A13

: P25

P24

: A12

: P24

P23

: A11

: P23

P22

: A10

: P22

P21

: A9

: P21

P20

: A8

: P20

P3MR

Port 3 Multiplex Register (

0x0900_0010 R/W)

b31 b8

P3MR

Reserved

P37 P36 P35 P34 P33 P32 P31 P30

Initial value : depend on operating mode (refer to Table 4.3)

P37

: D8

: P37

P36

: D9

: P36

P35

: D10

: P35

P34

: D11

: P34

P33

: D12

: P33

P32

: D13

: P32

P31

: D14

: P31

P30

: D15

: P30

MCU controller

Flash MCU(HMS39C7092)

Preliminary

P4MR

Port 4 Multiplex Register (

0x0900_0014 R/W)

b31 b8

P4MR

Reserved

P47 P46 P45 P44 P43 P42 P41 P40

Initial value : depend on operating mode (refer to Table 4.3)

P47

: D7

: P47

P46

: D6

: P46

P45

: D5

: P45

P44

: D4

: P44

P43

: D3

: P43

P42

: D2

: P42

P41

: D1

: P41

P40

: D0

: P40

P5MR

Port 5 Multiplex Register (

0x0900_0018 R/W)

b31 b4

P5MR

Reserved

P53 P52 P51 P50

Initial value : depend on operating mode (refer to Table 4.3)

P53

: A19

: P53

P52

: A18

: P52

P51

: A17

: P51

P50

: A16

: P50

P6MR

Port 6 Multiplex Register (

0x0900_001C R/W)

b31 b10

P6MR

Reserved

P66 P65 P64 P63 P67

P62

P61

P60

Initial value : depend on operating mode (refer to Table 4.3)

P66

: /LWR

: P66

P65

: /HWR

: P65

P64

: /RD

: P64

P63

: /AS

: P63

P67

: BCLK

: P67

P62

00 : /BACK

01 : P62

1x : Reserved

P61

00 : /BREQ

01 : P61

1x : Reserved

P60

: /WAIT

: P60

Flash MCU(HMS39C7092)

MCU controller

Preliminary

P7MR

Port 7 Multiplex Register (

0x0900_0020 R/W)

b31 b9

P7MR

Reserved

P77

P76

P74 P73 P72 P71 P70

Initial value : depend on operating mode (refer to Table 4.3)

P77

00 : TIOCB5

01 : /IRQ7

1x : P77

P76

00 : TIOCA5

01 : /IRQ6

1x : P76

P74

: AN4

: P74

P73

: AN3

: P73

P72

: AN2

: P72

P71

: AN1

: P71

P70

: AN0

: P70

P8MR

Port 8 Multiplex Register (

0x0900_0024 R/W)

b31 b8

P8MR

Reserved

P84

P83

P82

P81

P80

Initial value : depend on operating mode (refer to Table 4.3)

P84

: /CS0

: P84

P83

00 : /CS1

01 : /IRQ3

1x : P83

P82

00 : /CS2

01 : /IRQ2

1x : P82

P81

00 : /CS3

01 : /IRQ1

1x : P81

P80

: /IRQ0

: P80

P9MR

Port 9 Multiplex Register (

0x0900_0028 R/W)

b31 b11

b10 b9

P9MR

Reserved

P97

P95

P94

P93

P92

P91 P90

Initial value : depend on operating mode (refer to Table 4.3)

P97

: /TRST

: P97

P95

00 : /IRQ5

01 : P95

1x : Reserved

P94

00 : /IRQ4

01 : P94

1x : Reserved

P93

00 : /RxD1

01 : P93

1x : Reserved

P92

00 : /TxD1

01 : P92

1x : Reserved

P91

: RxD0

: P91

P90

: TxD0

: P90

Flash MCU(HMS39C7092)

Power Management Unit

Preliminary

5.2

Operation Modes

5.2.1

Introduction

The PMU is consisted of clock controller and reset controller. User can control

internal clocks those are embedded peripherals and main clock of MCU by setting

the registers of PMU. The MCU has three reset sources those are external power-on

reset, soft-reset of PMU, soft-reset of WDT and overflow reset of WDT. And PMU has

status registers that old reset value and PMU status.

To improve power management, support for a power-saving mode where bus clocks

may be disabled (or dropped to lower clock) is included.

The reset and power-down mechanism provides:

Stable power-up sequence

Power On Reset

Soft Reset

Additionally a system bus, once operational, benefits from well-defined modes of

operation:

RUN

Power-down mode

5.2.2

Reset and Operation Modes

A set of four useful states or modes is defined as follows:

RESET

When it is power-on, watchdog timer overflow, watchdog soft-reset or PMU soft-reset,

the MCU is initialized

Power on Reset

This state should be forced by any on-chip power-on-reset cell or external power-on

signal and maintained until bus clock is safe and stable.

The POR is forced to be in an asynchronous start-up condition and must be

recognized by all master and slave devices to disable output drives (and wait for a

valid clock). The MCU is running after 32 clocks end of reset timing that rising edge

of reset signal.

Soft- Reset of PMU

The soft-reset, which may need to apply to allow all soft resetting of the bus for a

number of clock cycles. In this reset states the PMU block initializes all the ASB

blocks, Bus controller, DRAM Controller, DMA Controller, ARM CPU core, and Arbiter,

Decoder.

Power Management Unit

Flash MCU(HMS39C7092)

Preliminary

5.4

Register Description

The PMU supplies the clock to all of the blocks in the MCU. The start address of

PMUCR

PMU Control Register (0x0900_1000 Write-Only)

b31 - b8

PMUCR

Reserved

Reset

Initial value : 0x-00

11 : Entering the Power down Mode

00 : Clear PMU Status Register

This register controls the operation mode of PMU. When power on reset states,

PD(Power Down) mode. The other values don't effect. The address of register is

0x0900_1000.

PMUST

PMU Status Register (0x0900_1000 Read-Only)

b31 - b8

PMUST

Reserved

PMUST

Reserved

PMUST

Reset

Initial value : 0x-00

This register holds the previous status and reset state of PMU. The address of
register is 0x0900_1000.

PMUST

(Previous Reset Status bits)

00 The Power-On reset state (nPOR)

01 PMU Soft-reset state

10 WDT Soft-reset state

11 WDT Overflow-reset state

PMUST

(PMU Status bits)

00 Start after Power-On reset

01 reserved state

10 reserved state

11 Start after Power-Down mode

Flash MCU(HMS39C7092)

Power Management Unit

Preliminary

PCLKCR

Clock Control Register (0x0900_1008 R/W)

b31 - b16

b15

b14

b13 b12 b11 b10 b9 b8 b7 b6 B5 b4 b3 b2 b1 b0

PCLKCR

Reserved WU_SEL INTC_CC

WDT_CC

UART_Clk

UART_CC

TIMER_CC

ADC_CC

Reset

Initial value : 0x00000000

The address of register is 0x0900_1008.

WU_SEL

: Wake-up source interrupt select register

0 - MCU wake-up when nFIQ interrupt occurr

1 - MCU wake-up when nIRQ interrupt occurr

INTC_CC

: Interrupt controller clock control register

0 - Interrupt controller us e the XIN clock. XIN is not killed at any

mode

1 - Interrupt controller use the BCLK of internal Bus clock. The

Bus clock is killed when Power-down mode

WDT_CC

: Clock control register of WDT

000 - BCLK

001 - BCLK/2

010 ~ 111 Reserved

UART_Clk

: UART0,1 clocks on-off control register.

00 - UART0,1 clocks ON

01 - UART1 clock ON, UART0 clock OFF

10 - UART1 clock OFF, UART0 clock ON

11 UART0,1 clocks OFF

UART_CC

: Clocks Control register of UART.

000 - BCLK

001 - BCLK/2

010 ~ 111 Reserved

TIMER_CC

: Clocks Control register of TIMER.

000 - BCLK

001 - BCLK/2

010 ~ 111 Reserved

ADC_CC

: Clocks Control register of ADC.

Values are same as WDT_CC

Power Management Unit

Flash MCU(HMS39C7092)

Preliminary

MEMCR

Memory map Control Register (0x0900_1010 Write-Only)

MEMSR

Memory map Status Register (0x0900_100C Read-Only)

b31 - b3

MEMCR

MEMSR

Reserved

On-Flash

REMAP

Reset

Initial value : 0x-0

In write operation, the address of register is 0x0900_1010 and in read operation,

the address of register is 0x0900_100C.

: External bus controller mapping change.

0 - Each nCS0 ~ nCS7 of address space is 16MB

size

1 - Each nCS0 ~ nCS7 of address space is 1MB

size

On-Flash

: Re-mapping of Flash start address to 0x0 in MODE

6 and 7.

0 - Default value.

1 - Re-mapping of Flash start address to 0x0 in the

memory map. It is valid at MODE 6 and 7.

REMAP

: Re-map internal SRAM address location.

0 - Default value.

1 Re-mapping of internal SRAM start address to

0x0 in the memory map. It is used at MODE

2,3,4,5,6 and 7.

RSTCR

Soft-Reset Control Register (0x0900_1030 R/W)

b31 - b1

RSTCR

Reserved

RSTCR

Reset

Initial value : 0x-0

RSTCR

1 : Normal reset

0 : Normal

This register is used for generating the Soft-reset operation. The MCU is entered in

reset state, when this register is set to high, it is cleared automatically at the end of

Soft-Reset procedure. The address is 0x0900_1030.

Flash MCU(HMS39C7092)

Interrupt controller

Preliminary

6.1.1

Interrupt sources

The interrupt controller provides interface between multiple interrupt sources and the

processor. The interrupt controller supports internal and external interrupt sources.

Internally there are 11 peripheral interrupt sources. Externally there are 8 interrupt

sources. Therefore certain interrupt bits can be defined for the basic functionality

required in any system, while the remaining bits are available for use by other

devices in any particular implementation.

Table 6.1 Interrupt Controller Default Setting Value

Interrupt No.

INTERRUPT SOURCES

INT0

External Interrupt 0

INT1

External Interrupt 1

INT2

External Interrupt 2

INT3

External Interrupt 3

INT4

External Interrupt 4

INT5

External Interrupt 5

INT6

External Interrupt 6

INT7

External Interrupt 7

INT8

reserved

INT9

reserved

INT10

WDT

INT11

UART0

INT12

UART1

INT13

ADC

INT14

Timer 0

INT15

Timer 1

INT16

Timer 2

INT17

Timer 3

INT18

Timer 4

INT19

Timer 5

INT20

Software Interrupt

The Users can set the active mode of all interrupt source inputs. The default mode is

the falling-edge trigger mode. Any inversion or latching required to providing edge

sensitivity must be provided at the generating source of the interrupt.

No hardware priority scheme or any form of interrupt vectoring is provided, but the

priority can be determined using FIQ mask regis ter and IRQ mask register under

software control.

FIQ mask register and IRQ mask register are also provided to generate an interrupt

under software control. Typically these registers may be used to determine either a

FIQ interrupt or an IRQ interrupt.

6.1.2

Interrupt Control

The interrupt controller provides the interrupt source status and the interrupt request

status. The interrupt mask registers are used to determine whether an active interrupt

source should generate an interrupt request to the processor or not. A logic-level

HIGH in the interrupt mask register indicates that the interrupt source is masked and

then doesn`t generate a request.

FIQ mask register and IRQ mask register indicate whether the interrupt source

causes a processor interrupt or not.

Flash MCU(HMS39C7092)

Interrupt controller

Preliminary

6.2

Interrupt Controller Registers

The start address of the interrupt controller is 0x0900_1200. The offset of any

particular register from the start address is fixed. The following registers are

provided for both FIQ and IRQ interrupt controllers:

Table 6.2 Memory Map of the Interrupt Controller

REG.

I/O OFFSET

Dir

Description

GMR

0x1200

R/W

Global Mask Register

TMR

0x1204

R/W

Trigger Mode Register

TPR

0x1208

R/W

Trigger Polarity Register

IDR

0x120C

R/W

Interrupt Direction Register

FSR

0x1210

FIQ Status Register

ISR

0x1214

IRQ Status Register

FMR

0x1218

R/W

FIQ Mask Register

IMR

0x121C

R/W

IRQ Mask Register

ISCR

0x1220

Interrupt Status Clear Register

GMR

Global Mask Register (0x0900_1200 R/W)

b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

GMR

Reserved I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

Reset

0000000

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Initial value : 0x01FFFFF

Bit field I0-I24

1 : Mask

0 : Unmask

The interrupt mask register is used to mask the interrupt input sources and defines

which active sources will generate an interrupt request to the processor. If certain bits

within the interrupt controller are not implemented, the corresponding bits in the

interrupt mask register must be masked. A bit value 0 indicates that the interrupt is

unmasked and will allow an interrupt request to reach the processor. A bit value 1

indicates that the interrupt is masked. Once a bit is masked, the corresponding bit in

the status register is cleared. On reset, all interrupt input-sources are masked.

TMR

Trigger Mode Register (0x0900_1204 R/W)

b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

TMR

Reserved I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

Reset

0000000

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Initial value : 0x0100000

Bit field I0-I24

1 : Level Trigger Mode

0 : Edge Trigger Mode

The interrupt trigger mode register is used to configure the interrupts with the

interrupt trigger polarity register. Each interrupt can be configured to level or edge

triggered. A bit value 0 indicates that the interrupt is configured to edge triggered and

a bit value 1 indicates that the interrupt is configured to level triggered. On reset, all

interrupt input sources are configured to edge triggered.

Interrupt controller

Flash MCU(HMS39C7092)

Preliminary

TPR

Trigger Polarity Register (0x0900_1208 R/W)

b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

TPR

Reserved I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

Reset

0000000

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Initial value : 0x01000000

Bit field I0-I24

1 : High/Rising Edge

0 : Low/Falling Edge

The interrupt trigger polarity register is used to configure the interrupts with the

interrupt trigger mode register. Each interrupt can be configured to rising/high or

falling/low active. A bit value 0 indicates that the interrupt is configured to falling

active for edge trigger mode and to low active for level trigger mode. A bit value 1

indicates that the interrupt is configured to rising active for edge trigger mode and to

high active for level trigger mode. On reset, all interrupt input sources are configured

to falling/low active.

Table 6.3 Interrupt Source Trigger Mode

DETECTION MODE

TMR

TPR

Falling-Edge (Default)

Rising-Edge

Low-Level

High-Level

IDR

Interrupt Direction Register (0x0900_120C R/W)

b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

IDR

Reserved I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

Reset

0000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Initial value : 0x00000000

Bit field I0-I24

1 : Direction to FIQ

0 : Direction to IRQ

The interrupt direction register is used to determine whether each interrupt source

drives IRQ or FIQ. A bit value 0 indicates that the interrupt is driven to IRQ and a bit

value 1 indicates that the interrupt is driven to FIQ. On reset, all interrupt input

sources drive IRQ.

Flash MCU(HMS39C7092)

Interrupt controller

Preliminary

FSR

FIQ Status Register (0x0900_1210 Read Only)

b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

FSR

Reserved I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

Reset

0000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Initial value : 0x00000000

Bit field I0-I24

1 : FIQ Pending

0 : FIQ Idle

The FIQ status register is used to reflect the status of all channels set to produce an

FIQ interrupt (IDRn = 1). When an interrupt is set for an FIQ occurring, the

corresponding bit is set in FIQ status register. The interrupt handler will examine this

clear register is written to `1', the corresponding bit is cleared if that channel is

configured to edge trigger mode. A HIGH bit indicates that the interrupt is active and

will generate an interrupt to the processor.

ISR

IRQ Status Register (0x0900_1214 Read Only)

b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

ISR

Reserved I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

Reset

0000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Initial value : 0x00000000

Bit field I0-I24

1 : IRQ Pending

0 : IRQ Idle

The IRQ status register is used to reflect the status of all channels set to produce an

IRQ interrupt (IDR(i) = 0). When an interrupt is set for an IRQ occurring, the

corresponding bit is set in IRQ status register. The interrupt handler will examine this

clear register is written to `1', the corresponding bit is cleared if that channel is

configured to edge trigger mode. A HIGH bit indicates that the interrupt is active and

will generate an interrupt to the processor.

FMR

FIQ Mask Register (0x0900_1218 R/W)

b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

FMR

Reserved I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

Reset

0000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Initial value : 0x00000000

Bit field I0-I24

1 : Disable FIQ

0 : Enable FIQ

The FIQ request mask register is used to mask the request to generate an interrupt

to a processor. If certain bits within the interrupt controller are not implemented, the

corresponding bits in the FIQ request mask register must be masked. A bit value 0

indicates that the interrupt is unmasked and will allow an interrupt request to reach

the processor. A bit value 1 indicates that the interrupt is masked. On reset, all FIQ

requests are unmasked.

Interrupt controller

Flash MCU(HMS39C7092)

Preliminary

IMR

IRQ Mask Register (0x0900_121C R/W)

b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

IMR

Reserved I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

Reset

0000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Initial value : 0x00000000

Bit field I0-I24

1 : Disable IRQ

0 : Enable IRQ

The IRQ request mask register is used to mask the request to generate an interrupt

to a processor. If certain bits within the interrupt controller are not implemented, the

corresponding bits in the IRQ request mask register must be masked. A bit value 0

indicates that the interrupt is unmasked and will allow an interrupt request to reach

the processor. A bit value 1 indicates that the interrupt is masked. On reset, all IRQ

requests are unmasked.

ISCR

Interrupt Status Clear Register (0x0900_1220 Write Only)

b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 B9 b8 b7 b6 b5 B4 b3 b2 b1 b0

ISCR

Reserved I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

Reset

0000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Initial value : 0x00000000

Bit field I0-I24

1 : Clear Interrupt Status

0 : No action

The status clear register is used to clear bits in the status register configured to the

edge trigger mode. If the channels are configured to the level trigger mode, the

corresponding bits in the FIQ status register and the IRQ status register have no

effect. This register is cleared when this register is written to `1'. When writing to this

to be cleared. Data bits that are LOW have no effect on the corresponding bit in the

status register. Note that the status clear register has an effect on the status register

in the edge trigger mode.

Flash MCU(HMS39C7092)

Watchdog Timer

Preliminary

The Interval Timer Mode

To use the WDT as an interval timer, clear WT/nIT to 0 and set TMEN to 1. A

watchdog timer interrupt (INT_WDT) is generated each time the timer counter

overflows. This function can be used to generate interval timer interrupts at regular

intervals.

WTCNT

value

Time

0x00

0xFF

ITOVF = 1
WDTINT generated

TMEN = 1

WT/nIT = 0

Figure 7.3 Operation in the Interval Timer Mode

7.3.1

Timing of Setting and Clearing the Overflow Flag

Timing of setting the overflow flag

In the interval timer mode when the WTCNT overflows, the ITOVF flag is set to 1 and

watchdog timer interrupt (INT_WDT) is requested.

In the watchdog timer mode when the WTCNT overflows, the WTOVF bit of the SR is

set to 1 and a WDTOUT signal is output. When RSTEN bit is set to 1, WTCNT

overflow enables an internal reset signal to be generated for the entire chip.

Timing of clearing the overflow flag

When the Reset Status Register (WRSR) is read, the overflow flag is cleared.

Flash MCU(HMS39C7092)

Watchdog Timer

Preliminary

7.5

Watchdog Timer Register Descriptions

The following registers are provided for watchdog timer:

WTCR

Watchdog Timer Control Register ( 0x0900_1100 R/W )

b31 - b8

WTCR

Reserved

INTEN

WT/nIT

TMEN

RSTEN

RSTSEL

CKSEL

Reset

Initial value : 0x-00

CKSEL

: Clock select. Select one of eight internal

clock sources for input to the WTCNT.

000 BCLK / 2

001 BCLK / 8

010 BCLK / 32

011 BCLK / 64

100 BCLK / 256

101 BCLK / 512

110 BCLK / 2048

111 BCLK / 8192

RSTSEL

: Reset select register. Select the type of

generated internal reset if the WTCNT overflows in

the watchdog timer mode.

0 - Power-on reset

1- Manual reset

RSTEN

: Reset enable register. Select whether to

reset the chip internally of not if the WTCNT

overflows in the watchdog timer mode.

0 - Disable

1- Enable

TMEN

: Timer enable register. Enable or disable the

timer.

0 - Disable

1- Enable.

WT/nIT

: Timer mode select register. Select whether

to use the WDT as a watchdog timer or interval timer.

0 - Interval timer mode

1- Watchdog timer mode

INTEN

: Interrupt enable register. Enable or disable

the interrupt request, INT_WDT.

0 - Disable

1- Enable

8-bit readable and writable register. The start address of register is 0x0900_1100.

The following functions are provided :

Selecting the timer mode

Selecting the internal clock source

Watchdog Timer

Flash MCU(HMS39C7092)

Preliminary

Selecting the reset mode

Setting the timer enable bit

Being enable interrupt request

Being enable reset signal occurrence

The clock signals are obtained by dividing the frequency of the system clock.

Table 7.2 Internal Counter Clock Sources (SYSCLK = 40 MHz)

CKSEL

CLOCK SOURCE

OVERFLOW INTERVAL

000

SYSCLK / 2

12.8 us

001

SYSCLK / 8

51.2 us

010

SYSCLK / 32

204.8 us

011

SYSCLK / 64

409.6 us

100

SYSCLK / 256

1.64 ms

101

SYSCLK / 512

3.28 ms

110

SYSCLK / 2048

13.11 ms

111

SYSCLK / 8192

52.43 ms

WRSR

Reset Status Register ( 0x0900_1104 Read-Only )

b31 - b2

WRSR

Reserved

ITOVF

WTOVF

Reset

Initial value : 0x-0

1 : Overflowed

0 : Normal

WTOVF

: Watchdog timer overflow flag. Indicates

that the WTCNT has overflowed in the watchdog

timer mode.

ITOVF

: Interval timer overflow flag. Indicates that the

WTCNT

has overflowed in the watchdog timer

mode.

Two-bit read only register. The WRSR indicates whether WTCNT is overflowed or not.

The WRSR is initialized to 0x0 by the reset signal, nB_RES.

Bit 0 (WTOVF) indicates that the WTCNT has overflowed in the watchdog timer

mode. Bit 1 (ITOVF) indicates that the WTCNT has overflowed in the interval timer

mode.

Flash MCU(HMS39C7092)

General Purpose Timer

Preliminary

107

8.1.1

General Purpose Timer Unit Introduction

The HMS39C7092 has a general-purpose timer unit (GPTU) with six channels of 16-

bit timer. There are two counter operation modes: a free running mode and a periodic

mode. And each channel has independent operating modes. There are common

functions for each channel: counter operation, input capture, compare match, PWM,

and synchronized clear and write.

It is possible to select one of eight counter clock sources for all channels.

Internal clock : counting at falling edge

BCLK / 2

BCLK / 4

BCLK / 16

BCLK / 64

External clock: counting at falling edge.

There are five particular operation mode which can be configured respectively. The

operation modes are described below.

Free Running Mode

Compare Match Mode

Input Capture Mode

Synchronized Clear and Write Mode

PWM(Pulse Width Modulation) Mode

And there are four kinds of counter clear sources which can be selected by user's

setting.

None : never clear until overflow for free running mode

GRA match or TPA input capture

GRB match or TPB input capture

Synchronous clear

General Purpose Timer

Flash MCU(HMS39C7092)

108

Preliminary

8.2

General Purpose Timer Unit Memory Map

8.2.1

Register Assignment

The base address of the general-purpose timer unit is 0x0900_1300 and the offset of

any particular register from the base address is fixed.

Table 8.1 Timer Global Control Register Map

REG.

I/O

OFFSET

DIR.

DESCRIPTION

TSTARTR

0x1300

R/W

Timer Start Register

TSYNCR

0x1304

R/W

Timer Sync. Register

TPWMR

0x1308

R/W

Timer PWM Mode Register

0x130C

(test only)

0x1310

(test only)

0x1314

(test only)

0x1318

(test only)

Table 8.2 Timer Channel Control Register Map

REG.

I/O

OFFSET

DIR.

DESCRIPTION

TCR0

0x1320

R/W

Timer 0 Control Register

TIOCR0

0x1324

R/W

Timer 0 I/O Control Register

TIER0

0x1328

R/W

Timer 0 Interrupt Enable Register

TSR0

0x132C

Timer 0 Interrupt Status Register

TCNT0

0x1330

R/W

Timer 0 Counter Register

GRA0

0x1334

R/W

Timer 0 General Register A

GRB0

0x1338

R/W

Timer 0 General Register B

GP Timer Unit has consists of six unit timer channels and each address starts at

following address

Table 8.3 Timer Channel Starting Address

Timer No.

Starting Offsets

Timer 0

0x1320

Timer 1

0x1340

Timer 2

0x1360

Timer 3

0x1380

Timer 4

0x13A0

Timer 5

0x13D0

Flash MCU(HMS39C7092)

General Purpose Timer

Preliminary

109

8.2.2

General Purpose Timer Unit Register Descriptions

The base address of the general-purpose timer unit is 0x0900_1300. The following

registers are provided for general purpose timer unit :

8.2.2.1

Timer Global Control Registers

TSTARTR

Timer Start Register (0x0900_1300 R/W)

b31 b8

TSTARTR

Reserved

res

STR5

STR4

STR3

STR2

STR1

STR0

Reset

Initial value : 0xXXXXXXC0

STR

1 : Start Timer Channel n

0 : Stop Timer Channel n

8-bit readable and writable register that starts and stops the counter of each channel.

TSYNCR

Timer Sync. Register (0x0900_1304 R/W)

b31 b8

TSYNCR

Reserved

res

SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0

Reset

Initial value : 0xXXXXXXC0

SYNC

n 1 : Operate Synchronously with other sync.

channel

0 : Independent Counting

8-bit readable and writable register that selects timer synchronizing mode for each

channel.

TPWMR

Timer PWM Mode Register (0x0900_1308 R/W)

b31 b8

TPWMR

Reserved

res

PWM5

PWM4

PWM3

PWM2

PWM1

PWM0

Reset

Initial value : 0xXXXXXXC0

PWM

n 1 : PWM Mode

0 : Counter Mode

8-bit readable and writable registers that select the PWM mode for each channel.

Flash MCU(HMS39C7092)

General Purpose Timer

Preliminary

111

TIOCR0

Timer 0 I/O Control Register (0x0900_1324 R/W)

0x1344 for Timer 1,0x1364 for Timer 2, 0x1384 for Timer 3, 0x13A4 for Timer 4, 0x13D4 for Timer 5

b31 b8

TIOCR0

Reserved

res

IOB

res

IOA

Reset

000

Initial value : 0xXXXXXX88

IOB

Select GRB Function

000 : compare match with pin output disable

001 : 0 output at GRB compare match

010 : 1 output at GRB compare match

011 : toggle output at GRB compare match

100 : GRB captures the rising edge of input

101 : GRB captures the falling edge of input

110 : GRB captures both edge of input

111 : Don't care

IOA

Select GRA Function

000 : compare match with pin output disable

001 : 0 output at GRA compare match

010 : 1 output at GRA compare match

011 : toggle output at GRA compare match

100 : GRA captures the rising edge of input

101 : GRA captures the falling edge of input

110 : GRA captures both edge of input

111 : Don't care

8-bit readable and writable register that selects the output compare or input capture

function for GRA and GRB, and selects the function of the TIOCAn and TIOCBn pins.

TIOCRn controls the GRA and GRB.

General Purpose Timer

Flash MCU(HMS39C7092)

112

Preliminary

TIER0

Timer 0 Interrupt Enable Register (0x0900_1328 R/W)

0x1348 for Timer 1,0x1368 for Timer 2, 0x1388 for Timer 3, 0x13A8 for Timer 4, 0x13D8 for Timer 5

b31 b8

TIER0

Reserved

Res

res

OVFIE

MCIBE

MCIAE

Reset

Initial value : 0xXXXXXXF8

OVFIE

0 : Disable Overflow Interrupt

1 : Enable Overflow Interrupt

MCIBE

0 : Disable GRB Match or

GRB capture Interrupt

1 : Enable GRB Match or

GRB capture Interrupt

MCIAE

0 : Disable GRA Match or

GRA capture Interrupt

1 : Enable GRA Match or

GRA capture Interrupt

8-bit readable and writable register that controls the enabling/disabling of overflow

interrupt request and the general register compare match/input capture interrupt

requests. TIERn controls the interrupt enable/disable.

TSR0

Timer 0 Status Register (0x0900_132C Read Only)

0x134C for Timer 1,0x136C for Timer 2, 0x138C for Timer 3, 0x13AC for Timer 4, 0x13DC for Timer 5

b31 b8

TSR0

Reserved

res

OVFI

MCIB

MCIA

Reset

Initial value : 0xXXXXXXF8

OVFI

0 : no overflow occurs

1 : Overflow occurs

MCIB

0 : no GRB Match or Capture

occurs

1 : GRB Match or Capture

occurs

MCIA

0 : no GRA Match or Capture

occurs

1 : GRA Match or Capture

occurs

8-bit readable register contains the flags that indicate TCNT overflow and GRA/GRB

compare match or input capture. These flags are interrupt sources.

Flash MCU(HMS39C7092)

General Purpose Timer

Preliminary

113

TCNT0

Timer 0 Counter (0x0900_1330 R/W)

0x1350 for Timer 1,0x1370 for Timer 2, 0x1390 for Timer 3, 0x13B0 for Timer 4, 0x13E0 for Timer 5

b31 b16 B15 b14 b13 b12 b11 b10 b9 b8 B7 b6 b5 b4 b3 b2 b1 b0

TCNT0

Reserved

TCNT

Reset

Initial value : 0xXXXX0000

TCNT

16bit Counter Value

16-bit readable and writable counter. The clock source is selected by TCR of each

channel. TCNT is cleared to 0x0000 by compare match with the corresponding GRA

or GRB, or by input capture to GRA or GRB. When TCNT is overflow, OVFI in the

TSR is set to `1'.

General Register A,B

16-bit readable and writable register. There are 2 general registers for each channel

(total 12). Each general register can function as either an output compare register or

an input capture register by setting it in the TIOCR.

GRA0

General Register A (0x0900_1334 R/W)

0x1354 for Timer 1,0x1374 for Timer 2, 0x1394 for Timer 3, 0x13B4 for Timer 4, 0x13E4 for Timer 5

b31 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

GRA0

Reserved

GRA

Reset

Initial value : 0xXXXX0000

GRA

16bit Compare Match A Value

GRB0

General Register B (0x0900_1338 R/W)

0x1358 for Timer 1,0x1378 for Timer 2, 0x1398 for Timer 3, 0x13B8 for Timer 4, 0x13E8 for Timer 5

b31 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

GRB0

Reserved

GRB

Reset

Initial value : 0xXXXX0000

GRB

16bit Compare Match B Value

Flash MCU(HMS39C7092)

General Purpose Timer

Preliminary

115

8.3.1

Free Running Mode

A reset of the counters for channels 0 - 5 leaves them all in the free-running mode.

When a corresponding bit in the TSR is set to 1, the corresponding timer counter

operates as a free-running counter and begins to increment. When the count wraps

round from 0xFFFF - 0x0000, the overflow flag (OVFI) in the timer status register

(TSR) is set to 1. If the OVFIE bit in the timer's corresponding interrupt enable

overflows, counting continues from 0x0000. Figure 8.2 shows an example of free-

running counting.

Periodic counter operation is obtained for a given channel's TCNT by selecting

compare match as a TCNT clear source. (Set the GRA or GRB for period setting to

output compare register and select counter clear upon compare match using the

CCLR1 and CCLR0 bits of the timer control register (TCR). After setting, the TCNT

begins incrementing as a periodic counter when the corresponding bit of TSTARTR is

set to 1. When the count matches GRA or GRB, the MCIA/MCIB bit in the TSR is set

to 1 and the counter is automatically cleared to 0x0000. If the MCIAE/MCIBE bit of

the corresponding TIER is set to 1 at this point, the CPU will be asked for an interrupt.

After the compare match, TCNT continues counting from 0x0000. Figure 8.3 shows

an example of periodic counting.

Figure 8.2 Free-Running Counter Operation

Time

TCNT value

0xFFFF

STR0-STR4

OVF

0x0000

Flash MCU(HMS39C7092)

General Purpose Timer

Preliminary

121

8.3.5

PWM Mode

The PWM mode is controlled using both the GRA and GRB in pairs. The PWM

waveform is output from the TIOCA output pin. The PWM waveform's 1 output timing

is set in GRA and the 0 output timing is set in GRB. A PWM waveform with duty cycle

between 0% and 100% can be output from the TIOCA pin by having either compare

match GRA or GRB be the counter clear source for the timer counter. All five

channels can be set to PWM mode.

8.3.5.1

PWM Mode Operation

Figure 8.9 illustrates PWM mode operations. When the PWM mode is set, the

TIOCA pin becomes the output pin. Output is 1 when the TCNT matches the GRA,

and 0 when TCNT matches the GRB. The TCNT can be cleared by compare match

with either GRA or GRB. This can be used in both free-running and synchronized

operation.

Figure 8.9 PWM Mode Operation Example 1

Counter cleared at GRA compare match

TCNT value

GRA

GRB

TIOCA

Time

a. Counter cleared by GRA

Counter cleared at GRB compare match

TCNT value

GRB

GRA

TIOCA

Time

b. Counter cleared by GRB

UART

Flash MCU(HMS39C7092)

126

Preliminary

9.1

General Description

This module is an Universal Asynchronous Receiver/Transmitter(UART) with FIFOs,

and is functionally identical to the 16450 on power-up (CHARACTER mode). The

16550 can be put into an alternate mode (FIFO mode) to relieve the CPU of

excessive software overhead.

In this mode internal FIFOs are activated allowing 16 bytes plus 3 bit of error data per

byte in the RCVR FIFO, to be stored in both receive and transmit modes. All the logic

is on the chip to minimize the system overhead and maximize system efficiency.

The UART performs serial-to-parallel conversion on data characters received from a

peripheral device and parallel-to-serial conversion on data characters received from

the CPU. The CPU can read the complete status of the UART at any time during the

functional operation. Status information includes the type and condition of the

transfer operations performed by the UART, as well as any error conditions(parity,

overrun, framing, or break interrupt).

The UART includes a programmable baud rate generator that is capable of dividing

the timing reference clock input by divisors of 1 to 65535 and producing a 16x clock

for driving the internal transmitter logic. Provisions are also included to use this 16x

clock to drive the receiver logic. In addition to baud rate generate, the UART also

include clock divider which divide the input system clock by setting the 8-bit divider

The UART has a processor-interrupt system. Interrupts can be programmed to the

user's requirements, minimizing the computing required to handle the

communications link. The general 16450/16550 has MODEM control signals, and

thus this module also has a MODEM signals internally, but these signals are

concealed.

Figure 9.1 TOP BLOCK Diagram

P r e s c a l e r

C l o c k

G e n e r a t i o n

U A R T _ C L K

I n t e r n a l

b u s

U A R T 0

U A R T 1

I N T_U A R T [ 1 : 0 ]

UCLK0

Bus Interface

C o n t r o l

E N U C L K 0
E N U C L K 1

UCLK1

Flash MCU(HMS39C7092)

UART

Preliminary

127

9.2

Features

Capable of running all existing 16450 software.

After reset, all registers are identical to the 16450 register set.

The FIFO mode transmitter and receiver are each buffered with 16 byte FIFO's to

reduce the number of interrupts presented to the CPU.

Adds or deletes standard asynchronous communication bits (start, stop, and parity)

to or from the serial data.

Hold and shift registers in the 16450 mode eliminate the need for precise

synchronization between the CPU and serial data.

Independently controlled transmit, receive, line status and data set interrupts.

Programmable baud generator divides any input clock by 1 to 65535 and generates

16x clock

Input clock divider by setting 8-bit divider register.

Independent receiver clock input.

Fully programmable serial-interface characteristics:

5-, 6-, 7- or 8-bit characters

Even, odd, or no-parity bit generation and detection

1-, 1.5- or 2-stop bit generation and detection

Baud generation (DC to 256k baud)

False start bit detection.

Complete status reporting capabilities.

Line break generation and detection.

Internal diagnostic capabilities.

Loopback controls for communications link fault isolation

Full prioritized interrupt system controls.

9.3

Signal Description

Table 9.1 Signal Descriptions

Name

Type

Description

RXD0

Serial Input. Serial data input from the communications

link (peripheral device, MODEM or data set).

RXD1

Serial Input. Serial data input from the communications

link (peripheral device, MODEM or data set).

TXD0

Serial Output. Composite serial data output to the

communications link (peripheral, MODEM or data set).

The SOUT signal is set to the Marking (logic 1) state

upon a Master Reset operation.

TXD1

Serial Output. Composite serial data output to the

communications link (peripheral, MODEM or data set).

The SOUT signal is set to the Marking (logic 1) state

upon a Master Reset operation.

Flash MCU(HMS39C7092)

UART

Preliminary

129

9.5

Registers Description

There are two UARTs implemented in the design, the base addresses are

0x0900_1400 in UART0 and 0x0900_1500 in UART1.

Table 9.2 UART Register Address Map (0x1500 in UART1)

Reg.

Name

I/O

Offset

Dir,

Description

RBR

0x1400

Receiver Buffer (DLAB = 0)

THR

0x1400

Transmitter Holding (DLAB = 0)

IER

0x1404

R/W

Interrupt Enable

IIR

0x1408

Interrupt Identification

FCR

0x1408

FIFO Control

LCR

0x140C

R/W

Line Control

LTR

0x1410

R/W

Loop Test Control

LSR

0x1414

R/W

Line Status

0x1418

Reserved

SCR

0x141C

R/W

Scratch Register

DLL

0x1400

R/W

Divisor Latch LSB (DLAB = 1)

DLM

0x1404

R/W

Divisor Latch MSB (DLAB = 1)

CLKCR

0x1420

R.W

Clock Control

CLKDR

0x1424

R/W

Clock Divisor

Table 9.3 UART Register Reset Values

Reg.

Reset Values

IER

0x00

IIR

0x01

FCR

0x00

LCR

0x00

LTR

0x00

LSR

0x60

TxD

`1'

UART

Flash MCU(HMS39C7092)

130

Preliminary

CLKCR

Clock Control Register (0x1420 R/W)

b31 b8

CLKCR

Reserved

CKEN

Reset

Initial value : 0xXXXXXX00

CKEN

0: Disable UART Clock

1: Enable UART Clock

The system programmer starts and stops the UART clock generator the Clock

Control Register (CLKCR). The programmer can also read the contents of the Clock

Control Register. The CKEN bit is the start clock bit. When this bit is logic 1, the

UART clock is generated from the on-chip clock generator. If this bit is a logic 0, then

the clock generator stop to operate.

CLKDR

Clock Divisor Register (0x1424 R/W)

b31 b8

CLKDR

Reserved

CKDIV

Reset

Initial value : 0xXXXXXX00

CKDIV

8-bit UART Clock Divisor Value

The UART contains a programmable Clock Generator that is capable of taking any

clock input and dividing it by any divisor from 0 to 255. One 8-bit register stores the

divisor in a 8-bit binary format. This Divisor Register must be loaded before setting

the Clock Control Register to ensure the proper operation of the UART Clock

Generator.

Flash MCU(HMS39C7092)

UART

Preliminary

131

LCR

Line Control Register (0x1400 ReadOnly)

b31 b8

LCR

Reserved

DLAB

BREAK STICKP PARITY

PEN

STOPBIT

DLEN

Reset

Initial value : 0xXXXXXX00

DLEN

00: 5-bit Data

01: 6-bit Data

10: 7-bit Data

11: 8-bit Data

STOPBIT

0: 1 stop bit

1: 1.5/2 stop bits

PEN

0: Disable Parity

1: Enable Parity

PARITY

0: Odd Parity

1: Even Parity

STICKP

0: Stick Parity as `0'

1: Stick Parity as `1'

BREAK

0: Nomal Transmission

1: Send Break

DLAB

0: Nomal state

1: Divisor Latch Access Mode

The system programmer specifies the format of the asynchronous data

communications exchange and set the Divisor Latch Access bit (DLAB) via the Line

Control Register (LCR). The programmer can also read the contents of the Line

Control Register. The read capability simplifies the system programming and

eliminates the need for separate storage in system memory of the line characteristics.

Table 9.8 Summary of Registers shows the contents of the LCR. Details on each bit

are :

DLEN

These two bits specify the number of bits in each transmitted and received

serial character.

STOPBIT

This bit specifies the number of Stop bits transmitted and received in each

serial character. If bit 2 is a logic 0, one Stop bit is generated in the

transmitted data. If bit 2 is a logic 1 when a 5-bit word length is selected via

bits 0 and 1, One and a half Stop bits are generated. If bit 2 is a logic 1

when either a 6-, 7-, or 8-bit word length is selected, two Stop bits are

generated. The Receiver checks the first Stop-bit only, regardless of the

number of selected Stop bits.

PEN

This bit is the Parity Enable bit. When bit 3 is a logic 1, a Parity bit is

generated (transmit data) or checked (receive data) between the last data

word bit and Stop bit of the serial data. (The Parity bit is used to produce

an even or odd number of 1s when the data word bits and the Parity bit are

summed.)

PARITY

This bit is the Even Parity Select bit. When bit 3 is a logic 1 and bit 4 is a

logic 0, an odd number of logic 1s is transmitted or checked in the data

word bits and Parity bit. When bit 3 is a logic 1 and bit 4 is a logic 1, an

even number of logic 1s is transmitted or checked.

STICKP

This bit is the Stick Parity bit. When bits 3, 4, and 5 are logic 1, the Parity

bit is transmitted and checked as a logic 0. If bits 3 and 5 are 1 and bit 4 is
a logic 0, then the Parity bit is transmitted and checked as a logic 1. If bit 5

UART

Flash MCU(HMS39C7092)

132

Preliminary

is a logic 0 Stick Parity is disabled.

BREAK

This bit is the Break Control bit. It causes a break condition to be

transmitted to the receiving UART. When it is set to a logic 1, the serial
output (TxD) is forced to be the Spacing (logic 0) state. The break is
disabled by setting bit 6 to a logic 0. The Break Control bit acts only on TxD
and has no effect on the transmitter logic.

** Note : This feature enables the CPU to alert a terminal in a computer communications system. If the

following sequence is followed, no erroneous or extraneous characters will be transmitted because

of the break.

DLAB

This bit is the Divisor Latch Access Bit. It must be set to high (logic 1) to
access the Divisor Latches of the Baud Generator during a Read or Write
operation. It must be set to low (logic 0) to access the Receiver Buffer, the
Transmitter Holding Register, or the Interrupt Enable Register.

DLL/DLM

Divisor Latch Register (0x1400/0x1404 R/W)

b31 b8

DLL

Reserved

DLL

Reset

Initial value : 0xXXXXXX00

DLL

Divisor Latch Lower Byte

b31 b8

DLM

Reserved

DLM

Reset

Initial value : 0xXXXXXX00

DLM

Divisor Latch Upper Byte

The UART contains a programmable Baud Generator that is capable of taking any

clock input from DC to 8.0 MHz and dividing it by any divisor from 2 to 65535. 4MHz

is the highest input clock frequency recommended when the divisor=1. The output

frequency of the Baud Generator is 16 x the Baud [divisor # = (frequency input) /

(baud rate x 16)]. Two 8-bit latches store the divisor in a 16-bit binary format. These

Divisor Latches must be loaded during initialization to ensure the proper operation of

the Baud Generator. Upon loading either of the Divisor Latches, a 16-bit Baud

counter is immediately loaded.

Table 12-5 Baud rates provide decimal divisors to use with crystal frequencies of

1.8432 MHz and 3.6864 MHz. For baud rates of 38400 and below, the error obtained

is minimal. The accuracy of the desired baud rate depends on the chosen crystal

frequency. Using a divisor of zero is not recommended.

UART

Flash MCU(HMS39C7092)

134

Preliminary

LSR

Line Status Register (0x1414 ReadOnly)

b31 b8

LSR

Reserved

FIFOE

TEMT

THRE

Reset

Initial value : 0xXXXXXX60

0: No data received

1: Received Data Ready

0: No overrun error

1: Overrun Error

0: No parity error

1: Parity Error

0: No framing error

1: Framing Error

0: No break detected

1: Break Interrupted

THRE

0: THR not empty

1: THR Empty

TEMT

0: Transmitter not empty

1: Transmitter Empty

FIFOE

0: FIFO is valid

1: FIFO has Invalid data

This register provides status information to the CPU concerning the data transfer.

Table 5 Summary of Registers shows the contents of the Line Status Register.

Details on each bit are :

This bit is the receiver Data Ready indicator. Bit 0 is set to a logic 1

whenever a complete incoming character has been received and

transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a

logic 0 by reading all of the data in the Receiver Buffer Register or the

FIFO.

This bit is the Overrun Error indicator. Bit 1 indicates that data in the

Receiver Buffer Register was not read by the CPU before the next

character was transferred into the Receiver Buffer Register, thereby

destroying the previous character. The OE indicator is set to a logic 1 upon

the detection of an overrun condition, and reset whenever the CPU reads

the contents of the Line Status Register. If the FIFO mode data continues

to fill the FIFO beyond the trigger level, an overrun error will occur only

after the FIFO is full and the next character has been completely received

in the shift register. OE is indicated to the CPU as soon as it happens. The

character in the shift register is overwritten, but it is not transferred to the

FIFO.

This bit is the Parity Error indicator. Bit 2 indicates that the received data

character does not have the correct even or odd parity, as selected by the

even-parity-select bit. The PE bit is set to a logic 1 upon the detection of a

parity error and is reset to a logic 0 whenever the CPU reads the contents

of the Line Status Register. In the FIFO mode this error is associated with

the particular character in the FIFO where it applies to. This error is

revealed to the CPU when its associated character is at the top of the FIFO.

This bit is the Framing Error indicator. Bit 3 indicates that the received

character did not have a valid stop bit. Bit 3 is set to a logic 1 whenever the

Stop bit following the last data bit or parity bit is detected as a logic 0 bit

Flash MCU(HMS39C7092)

UART

Preliminary

135

(Spacing level). The FE indicator is reset whenever the CPU reads the

contents of the Line Status Register. In the FIFO mode this error is

associated with the particular character in the FIFO where it applies to.

This error is revealed to the CPU when its associated character is at the

top of the FIFO. The UART will try to resynchronize after a framing error. To

do this, it assumes that the framing error was due to the next start bit, so it

samples this "start" bit twice and then takes it in the "data".

This bit is the Break Interrupt indicator. Bit 4 is set to a logic 1 whenever the

received data input is held in the Spacing (logic 0) state for longer than a

full word transmission time (that is, the total time of Start bit + data bits +

Parity + Stop bits). The BI indicator is reset whenever the CPU reads the

contents of the Line Status Register. In the FIFO mode this error is

associated with the particular character in the FIFO where it applies to.

This error is revealed to the CPU when its associated character is at the

top of the FIFO. When break occurs only one zero character is loaded into

the FIFO. The next character transfer is enabled after SIN goes to the

marking state and receives the next valid start bit.

** Note : Bits 1 through 4 are the error conditions that produce a Receiver Line Status interrupt whenever any

of the corresponding conditions is detected and the interrupt is enabled.

THRE

This bit is the Transmitter Holding Register Empty indicator. Bit 5 indicates

that the UART is ready to accept a new character for transmission. In

addition, this bit causes the UART to issue an interrupt to the CPU when

the Transmit Holding Register Empty Interrupt enable is set to high. The

THRE bit is set to a logic 1 when a character is transferred from the

Transmitter Holding Register into the Transmitter Shift Register. The bit is

reset to logic 0 concurrently with the loading of the Transmitter Holding

is empty; it is cleared when at least 1 byte is written to the XMIT FIFO.

TEMT

This bit is the Transmitter Empty indicator. Bit 6 is set to a logic 1 whenever

the Transmitter Holding Register (THR) and the Transmitter Shift Register

(TSR) are both empty. It is reset to a logic 0 whenever either the THR or

TSR contains a data character. In the FIFO mode this bit is set to one

whenever the transmitter FIFO and register are both empty.

FIFOE

In the 16450 mode, this is 0. In the FIFO mode, FIFOE is set when there is

at least one parity error, framing error or break indication in the FIFO.

LSR7 is cleared when the CPU reads the LSR, if there are no subsequent

errors in the FIFO.

** Note : The Line Status Register is intended for read operations only.

UART

Flash MCU(HMS39C7092)

136

Preliminary

FCR

FIFO Control Register (0x1408 WriteOnly)

b31 b8

FCR

Reserved

FIFODEPTH

Res

FCR2

FCR1

FIFOEN

Reset

Initial value : 0xXXXXXX00

FIFOEN

0: Disable FIFO

1: Enable Both Tx/Rx FIFO

FCR1

0: shift register not cleared

1: Self-clear shift register

FCR2

0: shift register not cleared

1: Self-clear shift register

FIFODEPTH

Receive FIFO Trigger Level

00: 1 Byte

01: 4 Bytes

10: 8 Bytes

11: 14 Bytes

This is a write only register at the same location as the IIR (the IIR is a read only

RCVR FIFO to trigger level.

FIFOEN

Writing a 1 to FCR0 enables both the XMIT and RCVR FIFOs. Resetting

FCR0 will clear all bytes in both FIFOs. When changing from FIFO Mode to

16C450 Mode and vice versa , data is automatically cleared from the

FIFOs. This bit must be a 1 when other FCR bits are written to or they will

not be programmed.

FCR1

Writing a 1 to FCR1 resets its counter logic to 0. The shift register is not

cleared. The 1 that is written to this bit position is self-cleared.

FCR2

Writing a 1 to FCR2 resets its counter logic to 0. The shift register is not

cleared. The 1 that is written to this bit position is self-cleared.

FIFODEPTH

These bits are used to set the trigger level for the RCVR FIFO interrupt.

Flash MCU(HMS39C7092)

UART

Preliminary

137

IIR

Interrupt Identification Register (0x1408 ReadOnly)

b31 b8

IIR

Reserved

FIFO

Res

FID

IID

IPEN

Reset

Initial value : 0xXXXXXX01

IPEN

0: Interrupt Pending

1: No Interrupt pending

IID/FID

Interrupt Identification Value

(refer Table 9.5)

FIFO

Indicate FIFO mode

00: None-FIFO mode

11: FIFO mode

In order to provide minimum software overhead during data character transfers, the

UART prioritizes interrupts into four levels and records them in the Interrupt

Identification Register. The three levels of interrupt conditions are as follows in order

of priority:

Receiver Line Status

Received Data Ready

Transmitter Holding Register Empty

When the CPU accesses the IIR, the UART freezes all interrupts and indicates the

highest priority pending interrupt to the CPU. While this CPU access occurs, the

UART records new interrupts, but does not change its current indication until the

access is complete. Table 9.6 Summary of Registers shows the contents of the IIR.

Details on each bit are :

IPEN

This bit can be used in a prioritized interrupt environment to indicate

whether an interrupt is pending or not. When bit 0 is a logic 0, an interrupt

is pending and the IIR contents may be used as a pointer for the

appropriate interrupt service routine. When bit 0 is a logic 1, no interrupt is

pending.

IID

These two bits of the IIR are used to identify the highest priority interrupt

pending as indicated in Table 9.5 Interrupt control functions.

FID

In the 16450 mode this bit is 0. In the FIFO mode this bit is set along with

bit 2 when a time-out interrupt is pending.

FIFO

These two bits are set when FIFOEN = 1.

UART

Flash MCU(HMS39C7092)

138

Preliminary

Table 9.5 Interrupt Control Functions

FIFO

Mode

Only

Interrupt

Identification Register

Interrupt Set and Reset Functions

Priority

Level

Bit 3

Bit 2

Bit 1 Bit 0

Interrupt

Type

Interrupt Source

Interrupt

Reset Control

None

Highest

Receiver

Line Status

Overrun Error, Parity

Error, Framing Error or

Break Interrupt

Reading the Line Status

Second

Receiver

Data

Available

Receiver Data Available or

Trigger Level Reached

Reading the Receiver

Buffer Register or the

FIFO drops below the

trigger level

Second

Character

Time-out

Indication

No Characters have been

removed from or input to

the RCVR FIFO during the

last 4 Char. times and

there is at least 1 Char. in

it during this time

Reading the Receiver

Buffer Register

Third

Transmitter

Holding

Empty

Transmitter Holding

Reading the IIR Register

(if it is the source of

interrupt) or writing it into

the Transmitter Holding

Fourth

MODEM

Status

Clear to Send, Data Set

Ready, Ring Indicator, or

Data Carrier Detect

Reading the MODEM

Status Register

IEN

Interrupt Enable Register (0x1404 R/W)

b31 b8

IEN

Reserved

Res

RLSIE

THREIE

DRIE

Reset

Initial value : 0xXXXXXX00

DRIE

0: No data received

1: Received Data Ready

THREIE

0: No overrun error

1: Overrun Error

RLSIE

0: No parity error

1: Parity Error

This register enables the five types of UART interrupts. Each interrupt can

individually activate the interrupt output signal. It is possible to totally disable the

interrupt Enable Register (IER). Similarly, setting bits of the IER register to a logic 1

enable the selected interrupt(s). Disabling an interrupt prevents it from being

indicated as active in the IIR and from activating the UART interrupt output signal. All

other system functions operate in their normal manners, including the setting of the

Line Status Registers. Table 9.6 the Summary of Registers shows the contents of

the IER. Details on each bit are :

DRIE

This bit enables the Received Data Available Interrupt (and time-out

interrupts in the FIFO mode) when it is set to logic 1.

THREIE

This bit enables the Transmitter Holding Register Empty Interrupt when set

Flash MCU(HMS39C7092)

UART

Preliminary

139

to logic 1.

RLSIE

This bit enables the Receiver Line Status Interrupt when it is set to logic 1.

LTR

Loop Test Control Register (0x1410 R/W)

b31 b8

LTR

Reserved

Res

LBON

Res

Reset

Initial value : 0xXXXXXX00

LBON

0: Normal Transmission

1: Loopback mode

This register controls the interface with the MODEM or data set (or a peripheral

device emulating a MODEM). The contents of the MODEM Control Register are

indicated in Table 9.6 Summary of Registers, and are described below.

LBON

This bit provides a local loopback feature for diagnostic testing of the UART.

When bit 4 is set to logic 1, the transmitter Serial Output (SOUT) is set to

the Marking (logic 1) state. The receiver Serial Input (SIN) is disconnected;

the output of the Transmitter Shift Register is "looped back" into the

Receiver Shift Register input. The four MODEM Control inputs (NCTS,

NDSR, NDCD, and NRI) are disconnected. The two MODEM Control

outputs (NDTR and NRTS) and two internal nodes (OUT1 and OUT2) are

internally connected to the four MODEM Control inputs and the MODEM

Control output pins are forced to be their inactive state (high). On the

diagnostic mode, the transmitted data is immediately received. This feature

allows the processor to verify the transmit- and received-data paths of the

UART.

In the diagnostic mode, the receiver and transmitter interrupts are fully operational.

SCR

Scratch Register (0x141C R/W)

b31 b8

SCR

Reserved

SCR

Reset

Initial value : 0xXXXXXX00

SCR

Scratch Register

This 8-bit Read/Write Register does not control the UART in any way. It is intended to

be used as a scratchpad register by the programmer to hold data temporarily.

UART

Flash MCU(HMS39C7092)

140

Preliminary

9.6

UART Operations

9.6.1

FIFO Interrupt Mode Operation

When the RCVR FIFO and receiver interrupts are enabled (FIFOEN = 1, DRIE =
1), RCVR interrupts occur as follows :

The received data available interrupt will be issued to the CPU when the FIFO has

reached its programmed trigger level; it will be cleared as soon as the FIFO drops

below its programmed trigger level.

The IIR receive data available indication also occurs when the FIFO trigger level is

reached, and like the interrupt it is cleared when the FIFO drops below the trigger

level.

The receiver line status interrupt (IIR=0x06), as before, has higher priority than the

received data available (IIR=0x04) interrupt.

The data ready bit (DR) is set as soon as a character is transferred from the shift

When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout
interrupts occurs as follows :

1. A FIFO timeout interrupt occurs in the following conditions :

- at least one character is in the FIFO

- the latest serial character received was longer than 4 continuous character

times (if 2 stop bits are programmed, the second one is included in this time

delay).

- the latest CPU read of the FIFO was longer than 4 continuous character times.

This will cause a maximum character received to interrupt issued delay of 160 ms at 300

baud with a 12 bit character.

2. Character times are calculated by using the RCLK input for a clock signal (this

makes the delay proportional to the baud rate).

3. When a timeout interrupt has occurred, it is cleared and the timer is reset when

the CPU reads one character from the RCVR FIFO.

4. When a timeout interrupt has not occurred the timeout timer is reset after a new

character is received or after the CPU reads the RCVR FIFO.

When the XMIT FIFO and transmitter interrupts are enabled (FIFOEN = 1,
THREIE = 1), XMIT interrupts occur as follows :

1. The transmitter holding register interrupt (IIR=0x02) occurs when the XMIT FIFO is

empty; it is cleared as soon as the transmitter holding register is written to. (1 to 16

characters may be written to the XMIT FIFO while this interrupt is serviced or the

IIR is read.)

2. The transmitter FIFO empty indications will be delayed 1 character time minus the

last stop bit time whenever the following occurs: THRE = 1 and there has not been

GPIO

Flash MCU(HMS39C7092)

144

Preliminary

10.1

General Description

The GPIO is an APB peripheral which provides 79 bits of programmable input /output

divided into 11 ports ; port A, port B, port 1, port 2, port 3, port 4, port 5, port 6, port 7,

port 8 and port 9. Each pin is configurable as either input or output except port7 [4:0].

At system reset, port A, 1, 3, 5, 8, 9 set their defaults to input and port B, 2, 4, 6, 7

set their defaults to output.

A P B I / F

P o r t

D a t a

R e g .

P o r t

Dir.

R e g .

P o r t

D a t a

R e g .

P o r t

Dir.

R e g .

Port B

Port A

E P A [ 7 : 0 ]

P A [ 7 : 0 ]

P A O E [ 7 : 0 ]

E P B [ 7 : 0 ]

P B [ 7 : 0 ]

P B O E [ 7 : 0 ]

P D [ 7 : 0 ]

P A [ 7 : 2 ]

B n R E S

P S E L

P S T B

P W R I T E

Figure 10.1 GPIO Block Diagram and PADS Connections(example for Port A and Port B)

Each port has a data register and a data direction register. The data direction register

defines whether each individual pin is an input or an output. The data register is used

to read the value of the GPIO pins, both input and output, as well as to set the values

of pins that are configured as outputs.

Flash MCU(HMS39C7092)

GPIO

Preliminary

145

10.2

GPIO Registers

The following user registers are provided:

nDR*

Port n Data Register. Values written to this read/write register will be input

on port A pins if the corresponding data direction bits are set to HIGH (port

input). Values read from this register reflect the external states of port n,

not necessarily the value should be written to it. All bits are cleared by a

system reset.

nDDR* Port n Data Direction Register. Bits set in this read/write register will select

the corresponding pins in port n to become an input, clearing a bit sets the

pin to output. All bits are cleared by a system reset.

*n is: A, B, 1, 2, 3, 4, 5, 6, 7, 8 or 9

10.2.1

Register Memory Map

The start address of the GPIO is 0x0900_1600 and the offset of any particular

Table 10.1 GPIO Register Memory Map

REG.

I/O

OFFSET

DIR

DESCRIPTION

PADR

0x1600

R/W

8-bit Port A Data register

PADDR

0X1604

R/W

Port A Data Direction register

PBDR

0X1608

R/W

8-bit Port B Data register

PBDDR

0X160C

R/W

Port B Data Direction register

P1DR

0X1610

R/W

8-bit Port 1 Data register

P1DDR

0X1614

R/W

Port 1 Data Direction register

P2DR

0X1618

R/W

8-bit Port 2 Data register

P2DDR

0X161C

R/W

Port 2 Data Direction register

P3DR

0X1620

R/W

8-bit Port 3 Data register

P3DDR

0X1624

R/W

Port 3 Data Direction register

P4DR

0X1628

R/W

8-bit Port 4 Data register

P4DDR

0X162C

R/W

Port 4 Data Direction register

P5DR

0X1630

R/W

4-bit Port 5 Data register

P5DDR

0X1634

R/W

Port 5 Data Direction register

P6DR

0X1638

R/W

8-bit Port 6 Data register

P6DDR

0X163C

R/W

Port 6 Data Direction register

P7DR

0X1640

R/W

8-bit Port 7 Data register

P7DDR

0X1644

R/W

Port 7 Data Direction register

P8DR

0X1648

R/W

5-bit Port 8 Data register

P8DDR

0X164C

R/W

Port 8 Data Direction register

P9DR

0X1650

R/W

8-bit Port 9 Data register

P9DDR

0X1654

R/W

Port 9 Data Direction register

On-Chip SRAM

Flash MCU(HMS39C7092)

150

Preliminary

11.1

General Description

The HMS39C7092 has 4-kbytes of high speed static RAM on-chip. The RAM is

connected to the CPU by a 32-bit ASB (Advanced System Bus) bus. The CPU

accesses byte data, half-word data, and word data in one cycle, making the RAM

useful for rapid data transfer.

11.2

Function Description

On-Chip SRAM can read data from SRAM and can write data into SRAM in a single

clock cycle through ASB bus. And SRAM is single module which have 32-bit data bus

and control lines.

The data in the On-chip RAM can always be accessed in one cycle that make the

RAM ideal for use as a program area, stack area, or data area, which requires high-

speed access. The contents of the on-chip RAM are held in both standby and power-

down modes.

Since the on-chip RAM is connected to the CPU by an internal 32-bit data bus, it can

be written and read by word access. It can also be written and read by half-word or

byte access.

Memory area 0x0803_0000 to 0x0803_FFFF is allocated to the on-chip SRAM as

default. The memory area of the on-chip SRAM is allocated 0x0000_0000 to

0x0000_0FFF

in Remap mode. This Remap mode is entered by setting the REMAP

flag in MEM_CR of PMU(see Chapter 5 Power Management Unit for detail).

On-chip Flash memory

Flash MCU(HMS39C7092)

152

Preliminary

12.1

General Description

The HMS39C7092 has 192-Kbytes of on-chip flash memory. The flash memory is

connected to the CPU by a 16-bit data bus. The CPU accesses both half-word and

word data in several states depending on the wait register value.

The on-chip flash memory booting option is enabled and disabled by setting the

mode pins (MD

to MD

) as shown in Table 12.1.

12.2

Features

The features of the flash memory are summarized below.

Memory organization : 96K x 16 (1.5Mbit)

Operating Voltage : dual power 3.0V ~ 3.6V(Vcc), 4.5~5.5V(FTVPPD)

Random access time : 90nsec

Program time : typ. 100usec/word

Erase block size : 32KB x 4, 24KB x 2, 8KB x 2

Block erase time : typ. 1.5sec/32KB (pre program + erase)

Multiple block erase command support (maximum 4 blocks)

Endurance : Min. 100 cycles

Both on-chip (user/boot mode) and on-board (PROM mode) program/erase

support

Bi-directional Data IO

Operation current : Standby mode : 10uA

Read/Program/Erase mode : max. 20mA

Flash MCU(HMS39C7092)

On-chip Flash memory

Preliminary

155

Table 12.2 Signal description of Figure 12.1(BUS Interface)

Name

I/O

Function

BnRES

These signal indicate the reset status of the ASB

BCLK

The ASB clock timing all bus transfers

DSELREG

When this signal is HIGH, it indicates that the Flash Memory
configuration Internal registers are selected. (When BA[31:0] is set to
FMI Region, 0x09000200~0x090002ff, of Memory Map)

DSEL

When this signal is HIGH, it indicates that the Flash Memory Array
address is selected. (When BA[31:0] is set to Flash Memory Region of
Memory Map.)

BWRITE

When this signal is HIGH, it indicates a write transfer and when LOW a
read.

BSIZE[1:0]

These signals indicate the size of the transfer that may be byte, half-
word, or word.

BA[31:0]

System address bus.
BA[[31:17] is used for selection between Internal Register Block and
Flash Memory. BA[16:0] is used for selection of Specific Internal
Register or Flash Memory Address.

BD[31:0]

I/O Bi-directional system data bus.

BWAIT

Wait slave response signal. It is driven to phase 1 when Flash
Memory
Read operation is selected. It is asserted while the Flash Memory
Read operation is uncompleted.

BERROR

When BEEOR is HIGH, a transfer error has occurred. When BERROR
is LOW, then the transfer is successful

BLAST

When BLAST is HIGH, the system decoder must allow sufficient time
for address decoding. When BLAST is LOW, the next transfer may
continue a burst sequence.

MODE
[2:0]

These signals are directly connected to external pins(MD

~ MD

), and

represent

operating mode at table12.1

FTVPPD

It is external power that is used to flash memory program and directly
Connected to external pin at all operating mode.

On-chip Flash memory

Flash MCU(HMS39C7092)

156

Preliminary

12.4

Flash Memory Register Description

The registers used to control the on-chip flash memory when enabled are shown in

Table 12.3. The base address of the flash memory register(FMU_base) is

0x0900_0200

Table 12.3 Flash Memory Registers

Reg.

I/O

Offset

Dir.

Description

Initial
Value

WAITREG

0x0200

R/W

Wait Register

0x000F

ADDREG

0x0204

R/W

Address Register

0x0000

DATAREG

0x0208

R/W

Data Register

0xFFFF

CONTREG

0x020C

R/W

Control Register

0x0000

EBR

0x0210

R/W

Erase Block Select Register

0x0000

STATPWR

0x0214

R/W

Status & Power Register

0x0000

TESTR

0x0218

R/W

Test Register

0x0400

WAITREG

Wait Control Register (WAITREG)

Bit

Initial Value

Read/Write

R/W

WAITREG

is an 8-bit register used for bus access wait time control. The initial value

is 0xF. Once Read command is executed, the next command execution is delayed for

the number of bus clocks(BCLK) that the WAITREG is set.

So, Flash Memory Read Operation is performed during the time of WAITREG value *

period of BCLK. For the successful execution of Flash Memory Read Operation

without interruption, this time must be longer then a Flash Memory Access

time(TACC). The typical value of WAITREG using 33 MHz-clock input is 03H, which

means that the delay time is 90nsec.

Flash MCU(HMS39C7092)

On-chip Flash memory

Preliminary

157

ADDREG

Address Register

Bit

A16

A15

A14

A13

A12

A11

A10

Init. Val. 0

RD/WR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Address of 16-bit word to be programmed or verified is stored in this register in the

Program mode(including Pre-Program) and the Verify mode (program/erase verify).

In Normal Read Mode, FA[16:0] is passed directly in address decoding block without

passing through ADDREG.

In Erase Mode, selecting block in `block select register' causes the specified Flash

Memory block to be erased.

Users can write this register directly at mode1(PROM Mode) by setting FR_SEL

signal, and usable address range are 96K x16 bits, 0x00000 ~ 0x17FFF. In this

Mode, if FR_SEL[2:0] is `001' and FWEB is rising_edge, FA[16:0] is passed into

ADDREG. If FR_SEL[2:0] is `001', FWEB is `1' and FOEB='0', users are able to

read 16-bit of ADDREG[16:1] through FD[15:0] in this Mode.

In other mode except mode1, ADDRREG are written via decoded value from

BA[16:0] of the Flash Memory address write command (not the ADDRREG write) and

read directly through ADDRREG read.

DATREG

Data Register

Bit

D15 D14

D13

D12

D11

D10

Init. Val. 1

RD/WR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

value in Program mode. Each bit is corresponded to each cell one by one and if it's

0, cell can be programmed, else not programmed. Flash Memory of HMS39C7092

can be programmed 16 bits at one time.

After reset, Data register output value is all reset to 0xFFFF and the other registers

are reset to `0'.

Users can write this register directly at mode1(PROM Mode). In this Mode, if

FR_SEL[2:0] = `001' and FWEB = rising_edge, FD[15:0] is passed into DATAREG. If

FR_SEL[2:0] = `010', FWEB = `1' and FOEB='0', users are able to read 16-bit of

DATAREG[15:0] through FD[15:0] .

In other mode except mode1, DATARREG are written via BD[16:0] of the Flash

Memory address write command (not the DATARREG write) and read directly using

DATAREG read.

On-chip Flash memory

Flash MCU(HMS39C7092)

158

Preliminary

CONTREG

Control Register

Bit

ER_VFY

PGM_VFY

ERSE

PGM

ER_PWR

PGM_PWR

Initial Value

Read/Write

R/W

CONTREG

is an 8-bit register used for flash memory operating mode control. It can

be read and written in all modes. It controls transition to state of flash memory array

read, program and erase operation, and charge pump operation mode. Table 12.4

shows the function of each bit of Control register.

Program process has one modes(PGM) and Verify process has two modes

(PGM_VFY,ER_VFY)

Table 12.4 Control Register

Name

Function

PGM_PWR

Program Power Setup (Drain/Positive Gate Pump Enable)

ER_PWR

Erase Power Setup (Negative/Positive Gate Pump Enable)

PGM

Program Start bit. Program Pulse Supply to Addressed Cell
(Drain/Gate Pulse)

ERSE

Erase Start bit. Erase Pulse Supply to Addressed Block
(Gate/Bulk Pulse)

PGM_VFY

Program Verify Read Enable (Positive Gate Pump Enable)

ER_VFY

Erase Verify Read Enable (Positive Gate Pump Enable)

Controlling control bit of Control register in table 12.4 can perform Program/Erase

/Verify process.

PGM_PWR/ER_PWR sets up the pump before Program and Erase. To make high

voltage necessary to program or erase Flash memory address, set the PGM_PWR

for program or ER_PWR for erase and wait for the pump setup time. After setting

up the pump, set the PGM for program or ERSE for erase to start program or erase.

In verify mode, without setting bit0 and bit1, setting one bit corresponds to each verify

modes (PGM_VFY,ER_VFY) set up the pump and perform verify read.

In Mode1, if FR_SEL[2:0] is `011' and FWEB is rising_edge, FD[7:0] is passed into

CONTREG. If FR_SEL[2:0] is `011', FWEB is `1' & FOEB='0', users are able to

read 8-bit of CONTREG through FD[7:0] .

In other mode except mode1, CONTREG register write and read are both possible.

Flash MCU(HMS39C7092)

On-chip Flash memory

Preliminary

159

EBR

Erase Block Select Register

Bit

SEC7

SEC6

SEC5

SEC4

SEC3

SEC2

SEC1

SEC0

Initial Value

Read/Write

R/W

The Bits of this register is used as selector for `Erase block(sector)' and each bit of

this register is matched to each erase block(sector). After setting CONTREG for

erase, block erase is performed by setting each corresponding block number bit in

EBR to 1. Table 12.5 depicts bit-corresponding sector number and the size of

sector and their address of lower 18bits. Capable of multiple block erase by setting

multiple bits of this register. (Maximum 4 blocks at a time)

In Mode1, if FR_SEL[2:0] is `100' & FWEB is rising_edge, FD[7:0] is passed into EBR.

If FR_SEL[2:0] is `100', FWEB is `1'& FOEB is '0', users are able to read 8-bit value

of EBR[16:1] through FD[7:0] .

In other mode except mode1, EBR register write and read are both possible.

Table 12.5 Erase Block Register

Sector #

Sector Size

Address Range

Sector 0

8KB (4K-word)

0x00000 ~ 0x01FFF

Sector 1

8KB

0x02000 ~ 0x03FFF

Sector 2

24KB

0x04000 ~ 0x0BFFF

Sector 3

24KB

0x0B000 ~ 0x0FFFF

Sector 4

32KB

0x10000 ~ 0x17FFF

Sector 5

32KB

0x18000 ~ 0x1FFFF

Sector 6

32KB

0x20000 ~ 0x27FFF

Sector 7

32KB

0x28000 ~ 0x2FFFF

STATPWR

Status & Power Register

Bit

5 4

3 2

1 0

HVEEI

LVEEI

LVCC

VEEI[1:0]

reserved

VPPI[1:0]

Initial Value

Read/Write

R/W

This is register regulates high voltage pump output voltage and indicates status of

pump in Program mode and Erase mode. In the following table, bit[8:6] are status

bits to indicate status of pump and bit[5:0] are power control bits to regulate high

voltage pump output voltage. Bit[5:0] are read/write register that controls voltage

of wordline/ bulk needed in Program, erase and verify mode.

In Mode1, if FR_SEL[2:0] is `101' & FWEB is rising_edge, FD[5:0] is passed into

STATPWR[5:0] (STATPWR[8:6] are read only). If FR_SEL[2:0] is `101' and FWEB

is `1', users are able to read 9-bit of STATPWR through FD[8:0] .

In other mode except mode1, STATPWR write and read are both possible.

Flash MCU(HMS39C7092)

On-chip Flash memory

Preliminary

161

12.5

On-Board Programming Mode

When pins are set to on-board programming mode and a reset-start is executed, the

chip enters the on-board programming state in which on-chip flash memory

programming, erasing, and verifying can be carried out. There are two operating

modes in this boot mode and user program mode set by the mode pins.

Boot mode is for use when user program mode is not available, such as the first time

on-board programming is performed, or if the program activated in user program

mode is accidentally erased.

12.5.1 Boot Mode

When mode pins are set to 6 or 7 and reset-start is executed, the HMS39C7092

enters the Boot Mode programming state in which on-chip flash memory

programming, erasing, verifying can be carried out. There are two operating modes

in this mode mode6 is extended mode, mode7 is one-chip micro-controller mode.

This device has Internal ROM area for booting. This ROM area locates in

0x00000000 , when SBM(Serial Boot Mode) = `1' (i.e. boot mode (Mode6 or 7)), and

used for Serial Boot when device is reset.

If boot mode is used, a flash memory programming control program must be

prepared beforehand in the host, and UART channel 0 is to be used.

When a reset-start is executed after setting the HMS39C7092 to mode6 or mode7,

the boot program in is activated the bit rate register value determined to 38400

bps(in 33.86MHz), then on-chip UART receives a user program (flash memory

programming control program) from off-chip. The received user program is written

into RAM (0x08030000 ~ 0x0803FFFF).

Figure 12.2 shows a system configuration diagram when using mode6 or mode7, and

figure 12.3 show the boot program mode execution procedure.

H o s t

( P C )

H M S 3 9 C 7 0 9 2

S R A M

B o o t R O M

R X D

T X D

A R M

F l a s h

M e m o r y

Figure 12.2 System Configuration When Using On-Board Boot Mode

On-chip Flash memory

Flash MCU(HMS39C7092)

162

Preliminary

Figure 12.3 Boot Mode Execution Procedure

When boot mode is initiated, the HMS39C7092 measures the low period of the

asynchronous communication data transmitted continuously from the host. The

UART transmit/receive format should be set as 8-bit data, 1 stop bit, no parity. To

ensure correct UART operation, the host's transfer bit rate should be set to 38400

bps, and the operating frequency for this process should be 33.86MHz.

Set Mode pins to mode6,7

Reset-Start

UCLK0 Setting (CLKDR=0Bh)

& UCLK0 Start (CLKCR=01h)

Set UART0 to

8-bit/1-Stop/NoParity
(LCR0=03h)

1.Set the mode pins to an on-chip flash

memory enable mode & programming

control program should be prepared

beforehand (mode6,7)

2.Start the HMS39C7092 with a reset.

3.Set UART0 input clock(UCLK0) to

3.07818MHz from Source Clock

(33.86MHz), and start UCLK0

4.Set Divisor Latch Mode (LCR0 =80h),

and set Divisor Latch to 38400bps

(DLL0=05h, DLM0 =00h)

5. Set UART0 to 8-bit/1-Stop/NoParity

(LCR0=03h)

6.Wait for Receiver Data Ready

(LSR0==1)

7.Get 1byte from Receiver Buffer

8.Store the user program , which is from

RBR, to SRAM and increase SRAM

Address pointer by 1

9.If not finished writing to 4Kbyte SRAM,

return to 6.

10.Branch to SRAM Start address and

execute user program (flash memory
programming control program)

Set Baud Rate to 38400bps

(LCR0=80h,DLL0=05h
,DLM0=00h)

Get 1-byte from

RxBuffer

Store to SRAM

Increase SRAM ptr

RxSize = 4096?

Branch to Start of SRAM

Yes

RXRdy(LSR0=1)

Yes

Flash MCU(HMS39C7092)

On-chip Flash memory

Preliminary

163

Application example (Boot Mode)

Data

1. Download Application Program

2. Run Downloaded Application Program

Step 1. Set Serial Boot Mode to `1'

(flash download algorithm

program should be prepared in

the host beforehand)

Step 2. Reset system

Step 3. ARM runs Boot Program in

internal ROM.

Step 4. Boot program receives flash

download algorithm program

through UART from Host.

Step 5. Store the flash download

algorithm program into the

internal SRAM.

Step 6. ARM branches to the start

address of the flash download

algorithm program.

Step 7. The algorithm program gets

flash ROM code from host

through UART and executes

flash ROM Write operation with

the code.

Step 8. End the flash ROM Write

operation and Host changes

system mode to Normal.

Step 9. Reset

Step 10. ARM Execute New Program

in the flash ROM.

BOOT

ROM

ARM

CORE

UART

SRAM

Flash

ROM

Flash Download

Algorithm

BOOT

ROM

ARM

CORE

UART

SRAM

(flash

download
program)

Flash

ROM

(flash

ROM

code)

Flash ROM Code

On-chip Flash memory

Flash MCU(HMS39C7092)

164

Preliminary

12.5.2 User Program Mode

When set to user program mode, the HMS39C7092 can program and erase its flash

memory by executing a user program/erase control program. Therefore, on-board

reprogramming of the on-chip flash memory can be carried out by providing

programming data and program/erase control program at the host, and storing

transfer program of a program/erase control program in flash memory area

beforehand.

To select user program mode, select a mode that enable the on-chip flash memory

(mode 4 or 5). Mode4 is extended mode, and mode5 is one-chip micro-controller

mode. The flash memory itself cannot be read while being programmed or erased,

so the control program that performs program/erase should transferred from external

memory to RAM and executed in RAM. Figure 12.4 shows the execution procedure

when user program mode is entered during program execution in RAM.

Figure 12.4 User Mode Execution Procedure

Set Mode pins to mode4,5

Reset-Start

Transfer program/erase
control program to RAM

Execute program/erase

control program in RAM
(flash memory rewriting)

Execute user application
program in flash memory

1.Set the mode pins to an on-chip

flash memory enable mode

(mode4,5)

2.Start the HMS39C7092 with a

reset.

3.Execute transfer program in flash

memory. program/erase control

program is transferred from host

to on-chip RAM through UART.

4. Branch to program/erase control

program in RAM.

5.Excute the program/erase control

program in RAM. As a result, re-

writing of the user application pro-

gram in flash memory is

performed.

6.On completion of rewrite, branch to

new user application program

Branch to Program in RAM

Flash MCU(HMS39C7092)

On-chip Flash memory

Preliminary

165

Application example (User Program Mode)

Data

1. Download Application Program

2. Run Downloaded Application Program

Step 1. Set Serial Boot Mode to `1'

Boot mode (mode 4 or 5)

Step 2. Reset system

Step 3. ARM runs Transfer Program in

the flash memory, and transfer

the program/erase control

program to internal SRAM.

Step 4. ARM branches to the start

address of the Program/erase

control program in SRAM

Step 5. If flash memory has been

programmed, Program/erase

control program erase flash

memory in block Units before

program

Step 6. Program/erase control program

gets

user application program

from

host through UART and executes

flash memory program operation

with the code in the erased flash

memory block.

Step 7. End the flash memory program

operation and Host changes

system mode to Normal.

Step 8. Reset

Step 9. ARM Execute New Program in

the flash ROM.

BOOT

ROM

ARM

CORE

UART

SRAM

Program

/erase

control

program

Flash

ROM

User application program

BOOT

ROM

ARM

CORE

UART

SRAM

Transfer

program

Flash

ROM

Program/erase

Control program

On-chip Flash memory

Flash MCU(HMS39C7092)

166

Preliminary

12.6

Flash Memory Programming/Erasing

A software method, using the CPU, is employed to program and erase flash memory
in the on-board programming modes. There are five flash memory operation modes:
pre-program/program mode, post-program mode, erase mode, pre-program/program -
verify mode, and erase verify mode. The transitions to these modes are made by
setting CONTREG register.
The flash memory cannot be read while being programmed or erased. Therefore,
the program (user program) that controls flash memory program/erase should be
located and executed in on-chip RAM or external memory.

12.6.1

Program & Program-Verify Mode

When writing data or programs to flash memory, the program flowchart shown in

figure 12.5 should be followed. Flash Memory of HMS39C7092 can be programmed

16bits at one time. In Program Verify, the data written in program mode is read to

check whether it has been correctly written in the flash memory. If result of verify

read at a certain address is not same as the progammed data of this address,

progam must be retried to the time when Verify read result and the progammed data

are matched.

However, if the program/program verify sequence is repeated N times and verify read

result is not same as programmed data, it is program fail.

On-chip Flash memory

Flash MCU(HMS39C7092)

168

Preliminary

12.6.2 Pre-program & Pre-program Verify Mode

This is the first step of flash memory erase algorithm. Pre-program & Pre-program

Verify must be done before block erase.

The difference between Program and Pre-program is that the purpose of Pre-

program is programming not-programmed cell in a certain block that will be erased.

Due to Pre-programming before block erase, every cell in the block that will be

erased goes to program state , so it is possible to prevent cell from being over-erased

after block erase.

When Pre-program mode, program address must start at first address of block to be

erased, and increase by 2 to the last address of that block.

The relation between each erase block and corresponding flash memory address is

shown at the Table 12.5 of chapter 12.3.

Pre-program needs to do pre-program verify read to ensure that every cell in the

block are programmed successfully.

The CONTREG setting are the same as program & program verify mode.

The Flow of pre-program and pre-program verify is shown at Figure 12.6

On-chip Flash memory

Flash MCU(HMS39C7092)

170

Preliminary

12.6.3 Erase & Erase Verify Mode

Flash memory erase operation are performed block by block. To erase flash

memory, make a setting for the flash memory area to be erased in erase block

one time. The Maximum number of blocks that can be erased at one time is four.

After Erase, it is necessary to do Erase verify read to ensure that every cell in the

block are erased successively. When Erase verify read mode, verify address must

start at first address of block to be erased, and increase by 2 to the last address of

that block. The relation between each erase block and corresponding flash memory

address is shown at the table 12.5 of chapter 12.3.

If the result of verify read at a certain address is not 0xFFFF, erase must be retried

until the result of Verify read is 0xFFFF. However, if the erase/erase verify sequence

is repeated N times and the result of verify read is not 0xFFFF, device is erase fail.

The Flow of erase & erase verify is shown at Figure 12.7.

Flash MCU(HMS39C7092)

On-chip Flash memory

Preliminary

173

12.7

Flash Memory PROM Mode

The HMS39C7092 has a PROM mode as well as the on-board programming modes

for programming and erase flash memory. In PROM mode, the on-chip flash

memory can be freely programmed using a PROM writer.

12.7.1 PROM Mode Setting

By setting FR_SEL signal, internal register of flash memory are directly write or read

through FD[15:0] as table 12.7. When value of FR_SEL[2:0] is set and FWEB =

rising_edge, FD[15:0] signals are passed into the register that FR_SEL select.

When value of FR_SEL[2:0] is set and FOEB is low, the register's value is read

through the FD[15:0].

Table 12.8 shows how the different external pins are set to write and read internal

Table 12.7 FR_SEL Value for access to internal Register

FR_SEL[2:0]

Register Read

Register Write

000

Read Data

Reserved

001

ADDREG

ADDREG & DATAREG

010

DATAREG

Reserved

011

CONTREG

100

EBR

101

STATPWR[8:0]

STATPWR[5:0]

Table 12.8 Setting for Register read/write

Pin Name

FRSTB

FCEB

FWEB

FOEB

FD[15:0]

FA[16:0]

Read

High

Low

High

Low

Read value
output

Address input

Write

High

Low

Rising
edge

High

Write Value
input

Address input

On-chip Flash memory

Flash MCU(HMS39C7092)

174

Preliminary

12.7.2 Memory Map

The memory map of PROM mode are shown at Table 12.9

At PROM mode, on-chip flas h is 96K x 16 memory. Therefore, In order to access

very next 16bit data to the currently accessed address, address should be changed

by `1'(not by `2'), Erase operation is performed by sector, and corresponding

address of each sector are shown.

Table 12.9 Erase Block Register

Sector #

Sector Size

FA [16:0]

Sector 0

8KB (4K-word)

0x00000 ~ 0x00FFF

Sector 1

8KB

0x01000 ~ 0x01FFF

Sector 2

24KB

0x02000 ~ 0x04FFF

Sector 3

24KB

0x05000 ~ 0x07FFF

Sector 4

32KB

0x08000 ~ 0x0BFFF

Sector 5

32KB

0x0C000 ~ 0x0FFFF

Sector 6

32KB

0x10000 ~ 0x13FFF

Sector 7

32KB

0x14000 ~ 0x17FFF

12.7.3 PROM Mode Operation

Each flash memory operation, such as program, erase, read are made by writing and

reading the flash memory internal register. Table 12.10 shows different flash

memory operation and register read/write sequence of each operation. Every

operation except for memory normal read and erase, the 1'st and 2'nd cycles are

deciding which operation will be performed, and 3'rd cycle is setting flash memory

address to be programmed or verified. Therefore, only 3'rd cycle need to be

repeated if another flash memory address is programmed or verified repeatedly after

first address. At Erase operation, 2'nd and 3'rd cycle have to be repeated.

At Verify read operation (Pre-Program/program Verify and erase verify), In order to

get the result of verify read, it is necessary to execute memory normal read operation

after 3'rd cycle.

Flash MCU(HMS39C7092)

On-chip Flash memory

Preliminary

175

Table 12.10 Setting for Flash PROM read/write

1'st Cycle

2'nd Cycle

3'rd Cycle

Address

Operation

FR_SEL

Mode

Data

FR_SEL

Mode

Data

FR_SEL

Mode

Data

Memory
Normal Read

000

Dout

Memory
Program
/Pre-program

011

0X0001

011

0X0005

001

Din

Memory
Post-program

011

0X0001

011

0X0041

001

Din

Memory
Erase

011

0X0002

100

011

0X000A

Program/Pre-
program
verify

101

0X0001

011

0X0010

001

Erase Verify
read

101

0X0000

011

0X0020

001

< Legend >

RA: Read Address WA: Write address Dout: Read data Din: Program data

X: don't care R: Read W: Write BN: Erase Block Number(see Table 12.6)

12.7.4 Timing Diagram and AC/DC Characteristics

This timing diagram follows the sequence that is shown on Table 12.11.

Figure 12.9 Timing Diagram of Read

TCEB

FWEB

FRSTB

FCEB

FADDR<16:0>

FR_SEL<2:0>

FD<15:0>

Dout

T A C C

XXX

000

TR_SEL

FOEB

TOEB

T O E B H

On-chip Flash memory

Flash MCU(HMS39C7092)

178

Preliminary

Table 12.11 DC Characteristics

- Preliminary

( V

= 3.3V±10%, Vss = 0V, Vss = 0V, FTVPPD = 5V±10%, Ta = 25°C ±10% )

Item

Symbol

Min

Typ

Max

Unit

Test

Condition

Input high voltage

Vih

0.7x

---

+0.5

Input low voltage

Vil

-0.5

---

0.3x V

Output high voltage

Voh

2.4

---

Ioh=0.8mA

Output low voltage

Vol

---

0.4

Iol=0.8mA

Reading

Idd

---

Programming

Idd

---

Vcc
current

Erasing

Idd

---

FXTVPPD
Current

Programming

lppd

---

Table 12.12 AC Characteristics

- Preliminary

= 3.3V±10%, Vss = 0V, Vss = 0V, FXTVPPD = 5V±10%, Ta = 25°C ±10% )

Item

Symbol

Min

Typ

Max

Unit

CEB output delay time

TCEB

---

OEB output delay time

TOEB

---

Output disable delay time

TOEBH

---

R_SEL output delay time

TR_SEL

---

Access time

TACC

---

Reset Pulse Width

Trst

300

500

---

Power up time

Tpup

---

Discharge
time(Program,Verify)
Discharge time(Erase)

Tpdw

10
20

---

us
us

Program time

Tpgm

---

CEB Setup time

Tces

100

200

---

WEB Pulse Width

Twep

100

200

---

WEB rise time

---

WEB fall time

---

Data Setup time

Tds

150

---

Data Hold time

Tdh

---

Erase time

Tera

Verify Setup time

Tvfy

---

Verify data out time

Tdout

---

A/D Converter

Flash MCU(HMS39C7092)

180

Preliminary

13.1

Overview

The HMS39C7092 has a 10-bit successive-approximations A/D converter with a

selection of up to five analog input channels. The A/D converter has multiplexed five

input channels. The serial output is configured to interface with standard shift

registers. The differential analog voltage input allows for common-mode rejection or

offset of the analog zero input voltage value. The voltage reference input can be

adjusted to allow encoding any smaller analog voltage span to the full 10bits of

resolution.

13.1.1

Features

A/D converter features are listed below.

10-bit resolution

5 input channels

Selectable analog conversion voltage range:

The analog voltage conversion range can be programmed by input of an

analog reference voltage at the V

REF

pin.

High-speed conversion:

Conversion time: minimum 2us per channel (with 8Mhz ADC clock)

Analog input range: GND ~ AVREF

Five 10-bit data registers

A/D conversion results are transferred for storage into data registers

corresponding to the channels.

Sample-and-hold function

A/D interrupt requested at end of conversion:

At the end of A/D conversions, an A/D End Interrupt (ADI) can be

requested.

Figure 13.1 Block Diagram of A/D Converter

DVSS

DVDD

AVREF

AVSS

AVDD

AN0

AN1
AN2
AN3
AN4

ACLK

AIOSTOP

Auto -zero

Comparator

11bit SAR

DA1 DA2 DA3

Format

Converter

A/D Conversion Section

Clock & Phase

Generator

Mux

ACH[4]

ACH[0]
ACH[1]
ACH[2]
ACH[3]

Reference Ladder

& Calibrator

ADST

BUS

Interface/

Controller

ADCSR

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADCCR

Internal

signals

A/D Converter

Flash MCU(HMS39C7092)

182

Preliminary

13.2

A/D Converter Registers

The registers used to control the A/D converter when enabled are shown in Table

13.2. The base address of the A/D converter is 0x0900_1700.

Table 13.2 Summarizes the A/D converter's registers.

Reg.Name

I/O

Offset

R/W

Name

Initial Value

ADCSR

0x1700

R/W Control & Status Register

0x00

ADCCR

0x1704

R/W Control Register

0x1

ADDR0

0x1708

Data Register 0

0x0000

ADDR1

0x170C

Data Register 1

0x0000

ADDR2

0x1710

Data Register 2

0x0000

ADDR3

0x1714

Data Register 3

0x0000

ADDR4

0x1718

Data Register 4

0x0000

13.2.1

Register Descriptions

ADCSR

AD Control & Status Register (0x0900_1700 R/W

)

Bit

ADCSR

ADF

ADST

ADIE

ACKS

ACHS

Init. Val.

RD/WR

R/W

Initial Value: 0x00

ACHS

Channel select (Select the analog input channel)

000 : Analog input channel 0

001 : Analog input channel 1

010 : Analog input channel 2

011 : Analog input channel 3

100 : Analog input channel 4

ACKS

Clock select (Select the A/D conversion time)

00 : 1/8 times of the ADC input clock (ADCLK)

01 : 1/4 times of the ADC input clock (ADCLK)

10 : 1/2 times of the ADC input clock (ADCLK)

11 : ADC input clock is from the timer block

ADIE

A/D interrupt enable (Enables and disables A/D

conversion)

0 : A/D end interrupt request (INT_ADC) is disabled.

1 : A/D end interrupt request (INT_ADC) is enabled.

ADST

A/D start (Starts or stops A/D conversion)

0 : A/D conversion is stopped

1 : A/D conversion start; ADST is automatically

cleared to 0 when conversion end.

Flash MCU(HMS39C7092)

A/D Converter

Preliminary

183

ADF

A/D end flag (Indicates end of A/D conversion)

0 : [Clearing condition] Read when ADF=1,

then write 0 in ADF.

1 : [Setting condition] Automatically set when

conversion end

ADCSR is the control and status register for AD converter. ACH[2:0] is used for

selection of the analog input channel. CKS[1:0] is used for selection of the AD

converter input clock. When these signals are `00', the main clock of the A/D

converter is 1/8 times of input clock (ADCLK), which is the same cycle with the

system operation clock.. When these signals are `01', then the main clock of the A/D

converter is 1/4 times of ADCLK. When these signals are `10', then the main clock of

the A/D converter is 1/2 times of ADCLK. When these signals are `11', then the main

clock of the A/D converter is external clock from Timer block. ADIE bit is interrupt

enable signal. When this signal is `0', then A/D converter does not generate the

interrupt of the end of A/D conversion. When this signal is `1', then A/D converter

generates the end of conversion interrupt. ADST bit indicate the start of A/D

conversion. When this signal is `1', the A/D converter start the A/D conversion and

remain high during A/D conversion. ADF indicate the end of A/D conversion. When

this bit is `1', then A/D converter indicates the end of A/D conversion. This signal is

auto-cleared by reading this bit.

ADCCR

AD Control Register (0X0900_1704 R/W)

Bit

b15-b2

ADCCR

Reserved

CALEND

AIOSTOP

Init. Val.

RD/WR

R/W

Initial value: 0x01

bit field: I0-I1

CALEND

Calibration end (Indicate the calibration end time)

0 : Indicate not end of calibration time.

1 : Indicate the end of calibration time.

AIOSTOP

Power save mode

0 : A/D converter is normal operation mode

1 : A/D converter is power save mode, so not

operate

CALEND indicate the end of calibration time (T

cal

). This signal is read only. AIOSTOP

is used to set the power save mode of A/D converter. When this signal is `0', then A/D

converter is entering normal operation mode after calibration time, or power up time.

See Figure 13.2 A/D converter operation for detailed timing diagram.

Flash MCU(HMS39C7092)

A/D Converter

Preliminary

187

13.5

Usage Notes

When using the A/D converter, note the following points:

1. Analog Input Voltage Range: During A/D conversion, the voltages input to the

analog input pins AN

should be in the range AV

REF

2. Relationships of AV

and AV

to V

and V

: AV

, AV

, V

, and V

should

be related as follows: AV

= V

. AV

and AV

must not be left open, even if the

A/D converter is not used.

3. V

REF

Programming Range: The reference voltage input at the V

REF

pin should be in

the range V

REF

4. Note on Board Design: In board layout, separate the digital circuits from the analog

circuits as much as possible. Particularly avoid layouts in which the signal lines of

digital circuits cross or closely approach the signal lines of analog circuits.

Induction and other effects may cause the analog circuits to operate incorrectly, or

may adversely affect the accuracy of A/D conversion. The analog input signals

(AN

to AN

), analog reference voltage (V

REF

), and analog supply voltage (AV

)

must be separated from digital circuit by the analog ground (AV

). The analog

ground (AV

) should be connected to a stable digital ground (V

) at one point on

the board.

5. Note on Noise: To prevent damage from surges and other abnormal voltages at

the analog input pins (AN

to AN

) and analog reference voltage pin (V

REF

connect a protection circuit like the one in figure 13.3 between AV

and AV

. The

bypass capacitors connected to AV

and V

REF

and the filter capacitors connected

to AN

must be connected to AV

6. A/D Conversion Accuracy Definitions: A/D conversion accuracy in the

HMS39C7092 is defined as follows:

Resolution:

Digital output code length of A/D converter

Offset error:

Deviation from ideal A/D conversion characteristic of analog

input voltage required to raise digital output from minimum

voltage value 0000000000 to 0000000001 (figure 13.4)

Full-scale error:

Deviation from ideal A.D conversion characteristic of analog

input voltage required to raise digital output from 1111111110

to 1111111111 (figure 13.4)

Quantization error: Intrinsic error of the A/D converter;1/2 LSB (figure 13.5)

Nonlinearity error: Deviation from ideal A/D conversion characteristic in range

from zero volts to full scale, exclusive of offset error, full-

scale error, and quantization error.

Absolute accuracy: Deviation of digital value from analog input value, including

offset error, full-scale error, quantization error, and

nonlinearity error.

Electrical Characteristics

Flash MCU(HMS39C7092)

192

Preliminary

14.1

Absolute Maximum Ratings

Table 14.1 lists the absolute maximum ratings(Note1 and 2).

Table 14.1 Absolute Maximum Ratings - Preliminary -

Item

Symbol

Value

Power supply voltage

-0.5V to 4.6V

DC Input Voltage (except I/O pins)

-0.5V to 6.0V

DC Output Voltage (Output in high or low state)

OUT

-0.5V to V

+0.5V

DC Output Voltage (output in 3-state)

OUT

-0.5V to +6.0V

Reference Voltage

REF

-0.3V to AV

+0.3

Analog Power supply voltage

-0.3V to 3.6V

Analog Input Voltage

-0.3V to AV

+0.3

Storage Temperature range

-65 to +150°C

Note1: Absolute maximum continuous ratings are those values which damage to the

device may occur. Exposure to these conditions or conditions beyond those

indicated may adversely affect device reliability. Functional operation under

absolute-maximum-rated conditions is not implied.

Note2: Under transient conditions these ratings may be exceeded as elsewhere in

this specification.

14.2

Recommended Operating Conditions:

Table 14.2 lists the recommended operating conditions.

Table 14.2 Recommended Operating Conditions - Preliminary-

Symbol

Parameter

MIN

MAX

UNIT

Supply voltage

3.0

3.6

Input voltage

5.5

OUT

Output voltage outputs active

OUT

Output voltage outputs disabled

5.5

PPD

Flash program/erase voltage

4.5

5.5

Operating free-air temperature

°C

Flash MCU(HMS39C7092)

Electrical Characteristics

Preliminary

193

14.3

DC Characteristics

Table 14.3 lists the DC characteristics.

Table 14.3 DC Characteristics - Preliminary-

ITEM

SYM
BOL

MIN

MAX

UNIT

TEST Conditions

Input Low Voltage

-0.5

0.3XV

VDD=3.0V to 3.6V

Input High Voltage

0.7XV

+0.5

VDD=3.0V to 3.6V

Output Low Voltage

0.4

VDD=3.0V
I

=0.8mA

Output High

Voltage

2.4

VDD=3.0V
I

=-0.8mA

Input current at

maximum voltage

VDD=3.0V to 3.6V
Input=5.5V

Table 14.4 lists the IO circuit with pull-ups

Table 14.4 IO Circuits with pull-ups - Preliminary-

Min Current(at PAD = 0V)

Max Current (at PAD = 0V)

3.3V Pull-up

30uA

-146uA

Equivalent

resistance

88.3kOhms

24.7kOhms

Table 14.5 lists the IO circuit with pull-downs

Table 14.5 IO Circuits with pull-downs - Preliminary-

Min Current(at PAD =

2.65V)

Max Current (at PAD = 3.6V)

Pull-down

31uA

159uA

Equivalent

resistance

85.5kOhms

22.6kOhms

Electrical Characteristics

Flash MCU(HMS39C7092)

194

Preliminary

14.4

AC Characteristics

Timing measurement conditions is following that

Unless otherwise specified:

VDD = 3.3V

Junction Temperature = 25 degrees C

Process = Typical

Low voltage input signal input signal rising and falling edges switching time

= 0.3ns

Clock timing parameters are listed in table 14.6, control signal timing parameters in

table 14.7, and bus timing parameters in table 14.8.

Table 14.6 Clock Timing - Preliminary-

Item

Symbol

Min.

Max.

Units

Test
Conditions

Clock cycle time

CYC

1000

Clock pulse low width

Clock pulse high width t

Clock rise time

Clock fall time

Figure 14.3

Clock oscillator

Settling time at reset

OSC1

Figure 14.1

Table 14.7 Control Signal Timing - Preliminary-

Item

Symbol

Min.

Max.

Units

Test
Conditions

XnRES setup time

RESS

200

XnRES pulse width

RESW

CYC

Mode programming

setup time

MDS

200

Figure 14.2

Flash MCU(HMS39C7092)

Electrical Characteristics

Preliminary

195

Table 14.8 Bus Timing - Preliminary-

Item

Symbol

Min.

Max.

Units

Test
Conditions

Address delay time

Address hold time

Read strobe delay time

RSD

Address strobe delay time t

ASD

Write strobe delay time

WSD

Strobe delay time

Write strobe pulse width 1

WSW1

Address setup time 1

AS1

Read data setup time

RDS

Read data hold time

RDH

Write data delay time

WDD

Write data setup time 1

WDS1

Write data hold time

WDH

Read data access time 1

ACC1

Read data access time 3

ACC3

Figure 14.3

Figure 14.4

Precharge time 1

PCH1

Precharge time 2

PCH2

Wait setup time

WTS

Wait hold time

WTH

Figure 14.5

Bus request setup time

BRQS

Bus acknowledge time 1

BACD1

Bus acknowledge time 2

BACD2

Bus-floating time

BZD

Figure 14.6

Electrical Characteristics

Flash MCU(HMS39C7092)

196

Preliminary

14.4

AD Conversion characteristics (Preliminary)

Table 14.9 lists the operation conditions of the AD Conversion

Table 14.9 Operating Conditions of the AD Conversion - Preliminary-
Parameter

Symbol

Min.

Max.

Units

Power Supply

AVDD

3.0

3.6

Analog Input

GND+0.2

AVREF-0.2

Clock Pulse Width

PWL

62.5

Operating

Temperature

100

°C

Table 14.10 lists the electrical characteristics of the AD converter

Table 14.10 Electrical characteristics of the AD converter - Preliminary-

Conditions : Analog input frequency F

=1.26KHz, ADCLK=7.5MHz,

=DV

=AV

REF

=3.3V T=25°C

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

Normal

ADCLK=7.5MHz

Input=AV

REF

=1.26KHz ramp

2.0

Power Down

ADCLK=7.5MHz

Analog input

voltage

GND+

0.2

REF

-0.2

Accuracy

Resolution

bits

INL

Integral Non-

linearity

ADCLK=7.5MHz

Input=0-AVREF(V)

=1.26KHz)

2.0

LSB

DNL

Differential Non-

linearity

ADCLK=7.5MHz

Input=0-AV

REF

=1.26KHz ramp)

1.0

LSB

SNR

Signal-to-Noise

Ratio

Fsample=500Ksps,

=1.26KHz

SNDR

Signal-to-Noise

Distortion Ratio

ADCLK

MHz

Conversion time

Output

capacitance

Rref

Reference

resistance

10K

REF

Analog

Reference

Voltage

CAL

Power up time

Calibration time

THD

Total harmonic

distortion

AVDD

Analog power

3.0

3.3

3.6

DVDD

Digital power

3.0

3.3

3.6

Analog input

frequency

KHz

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