MIC4807
Micrel
October 1998
7-3
7
CS
Data-in
18
HVOUT
0
HVOUT
1
HVOUT
2
HVOUT
3
HVOUT
4
HVOUT
5
HVOUT
6
HVOUT
7
V
DD
OE
Ground
Clear
A
IN
C
IN
B
IN
V
DD
MIC4807
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
General Description
The MIC4807 is an 80V, 8-channel, addressable low side
driver with latches and TTL/CMOS compatible logic inputs.
Each logic input is composed of a comparator with a 1.4V
bandgap-derived reference serving as the trip point. The
addresses (A
IN
, B
IN
, and C
IN
) and Data-in logic inputs have an
internal 50
A pull-up current source, while the Output Enable
(OE), Chip Select (CS), and Clear logic inputs have an
internal 75
A pull-down sink. If the logic lines to the MIC4807
are severed, these currents guarantee that the outputs will
turn OFF.
Individual latches in the MIC4807 are selected by a binary
address presented at inputs A
IN
, B
IN
, and C
IN
. Data-in is
directed to the addressed latch while CS is held low, allowing
an individual output to be pulse-width modulated. When CS
is set high again, the last Data-in is stored in the latch. If Data-
in = "1", the addressed output is turned on, and if Data-in = "0",
the addressed output is turned off.
Information presented to Data-in and the address inputs is
transferred to the latches while CS is pulled low. For
application, where several outputs must be (Continued)
Features
4.5V to 16V Operation
Eight 80V 100mA Outputs
Off-state Leakage less than 10
A at 25
C
Short-Circuit Proof
Thermal Shutdown with Hysteresis
DMOS Output Devices (R
ON
7
at 25
C)
Applications
Lamp Drivers
Solenoid Drivers
Display Drivers
-Electroluminescent
-Vacuum Fluorescent
-Plasma
Relay Drivers
Print Head Drivers
Heater Drivers
Power Semiconductor Drivers
Security Systems
Environmental Controls
Process Controllers
MIC4807
80V 8-Channel Addressable Low-Side Driver
Part
Operating
Package
Number
Temperature-Range
MIC4807BN
-40
C to 85
C
18-Pin Plastic DIP
Block Diagram
Ordering Information
Pin Diagram
Latches
Driver
Address
Decoder
Driver
15
14
13
16
12
5
6
4
7
17
18
11
1
2
10
9
8
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
0
1
2
3
4
5
6
7
V
DD
A
IN
B
IN
C
IN
Data-in
Ground
OE
Clear
CS
Addressing
{
Thermal
Shutdown
Current
Limit
MIC4807
Micrel
7-4
October 1998
Electrical Characteristics:
(Note 6) MIC4807BN, T
A
= 25
C, V
DD
= 15V unless otherwise specified (see
Test Circuit).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
DD
Supply Voltage
4.5
16
V
I
DD
Supply Current
OE = L (Note 3)
5.5
10
mA
OE = H (Note 4)
1.5
3
mA
V
IN
(0)
Logic Input Voltage
4.5V
V
DD
16V
0.8
V
V
IN
(1)
2.0
V
I
IN
(0)
Logic Input Current for A
IN
,
V
IN
= 0V
150
70
25
A
B
IN
, C
IN
, and Data-in
I
IN
(1)
Logic Input Current for CS,
V
IN
= V
DD
25
130
250
A
OE, and Clear
I
OUT
Output Leakage Current
OE = 0V, V
OUT
= 80V
1
10
A
R
ON
Output "ON" Resistance
Output is ON, V
OUT
= 0.7V,V
DD
= 10V
5.1
7
I
SC
Short Circuit Current
Output is ON< V
OUT
= 50V
140
190
250
mA
10V
V
DD
15V (Note 5)
V
OUT
Output Voltage (OFF)
80
V
V
OUT
Output Voltage (ON)
I
OUT
= 50mA,V
DD
= 10V
0.26
0.35
V
I
OUT
= 100mA, V
DD
= 10V
0.51
0.7
V
Data and Address
V
DD
= 10V for all timing tests
400
ns
Set-up Time
(A, see Timing Diagram)
Data and Address
(B)
50
ns
Hold Time
CS Pulse Width
(C)
500
ns
Turn-on Delay
(D)
2.5
ns
General Description
(Continued)
turned on simultaneously, Gray Code address sequencing
can be applied to Ain, Bin, Cin, while Data-in is held high and
CS is held low. Data-in will be transferred to each address in
turn, without the need to toggle CS. Similarly, a set of outputs
could be simultaneously turned off by setting Data-in low.
Gray Code ensures that no intermediate addresses are
inadvertently accessed. A typical Gray Code is 0, 1, 3, 2, 6,
7, 5, 4.
Each output drive circuit has a high-voltage, power DMOS
device configured as a transconductance loop. This loop
limits the output current to typically 200mA. While current
limiting keeps the output device within its allowable safe-
operating area (SOA), the power dissipation may be exces-
sive. Long-term survival is guaranteed by thermal shutdown.
When operated below current limit, the outputs appear as
small-valued resistors (typically 5.1
at 25
C) connected to
ground. The "ON" resistance (R
ON
) has a strong, positive
temperature coefficient (approximately 7500 ppm/
C) which
promotes current sharing if two or more outputs are paral-
leled.
Absolute Maximum Ratings
(Notes 1, 2 and 3)
Output Voltage (V
OUT
, OFF)
100V
Supply Voltage (V
DD
)
16.5V
Logic Input Voltage (V
IN
)
0.3V TO V
DD
+ 0.3
Continuous Output Current (I
OUT
)
Internally Limited
Power Dissipation (P
D
, Note 2)
Internally Limited
Ambient Temperature (T
A
):
40
C to +85
C
Maximum Junction Temperature (T
JMAX
)
150
C
Storage Temperature
65
C to +150
C
JA
- Plastic DIP
130
C/W
MIC4807
Micrel
October 1998
7-5
7
Electrical Characteristics:
(Note 6) T
A
= 25
C, V
DD
= 15V unless otherwise specified (see Test Circuit).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Turn-Off Delay
(E)
2.5
s
Output Disable
(F)
2
s
Response Time
Output Enable
(G)
2
s
Response Time
Clear Response Time
(H)
2.5
s
Clear Pulse Width
(I)
500
ns
Electrical Characteristics:
(Note 6) T
A
= 55
C to +125
C, V
DD
= 15V unless otherwise specified (see Test
Circuit).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
DD
Supply Voltage
4.5
16
V
I
DD
Supply Current
OE = L (Note 3)
15
mA
OE = H (Note 4)
4
mA
V
IN
(0)
Logic Input Voltage
4.5V
V
DD
16V
0.8
V
V
IN
(1)
2.0
V
I
IN
(0)
Logic Input Current for A
IN
,
V
IN
= 0V
250
10
A
B
IN
, C
IN
, and Data-in
I
IN
(1)
Logic Input Current for CS,
V
IN
= V
DD
25
400
A
OE, and Clear
I
OUT
Output Leakage Current
OE = 0V, V
OUT
= 80V
5.1
7
A
R
ON
Output "ON" Resistance
Output is ON, V
OUT
=0.7V,V
DD
=10V
12
I
SC
Short Circuit Current
Output is ON< V
OUT
= 50V
100
300
mA
10V
V
DD
15V (Note 5)
V
OUT
Output Voltage (OFF)
80
V
V
OUT
Output Voltage (ON)
I
OUT
= 50mA,V
DD
= 10V
0.6
V
I
OUT
= 100mA, V
DD
= 10V
1.2
V
Data and Address
V
DD
= 10V for all timing tests
700
ns
Set-up Time
(A, see Timing Diagram)
Data and Address
(B)
50
ns
Hold Time
CS Pulse Width
(C)
1000
ns
Turn-on Delay
(D)
5
s
MIC4807
Micrel
7-6
October 1998
Electrical Characteristics:
(Note 6) T
A
= 25
C, V
DD
= 15V unless otherwise specified (see Test Circuit).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Turn-Off Delay
(E)
5
s
Output Disable
(F)
4
s
Response Time
Output Enable
(G)
4
s
Response Time
Clear Response Time
(H)
5
s
Clear Pulse Width
(I)
1000
ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not
apply when operating the device beyond its specified operating ratings.
Note 2: The junction temperature is internally limited by a thermal shutdown circuit. The maximum power dissipation is a function of
T
JMAX
,
JA
, and T
A
. The maximum allowable power dissipation at any ambient temperature is P
D
= (T
JMAX
- T
A
) /
JA
. If this dissipation
is exceeded, the die temperature will rise above 150
C, and the MIC4807 will go into thermal shutdown.
Note 3: All outputs are off when OUTPUT ENABLE is pulled low.
Note 4: All outputs are turned on during this test.
Note 5: Pulse testing is used to avoid thermal shutown.
Note 6: Minimum and Maximum limits are tested and 100% guaranteed over the temperature range specified. Typicals are measured
at 25
C and represent the most likely parametric norm.
Timing Diagram
C
CS
Data-in
A
B
A
IN
B
IN
C
IN
Logic "1"
Logic "0"
Clear
H
F
D
OFF
ON
HVOUT
0
G
OE
H
HVOUT
1
E
D
HVOUT
2
HVOUT
3
HVOUT
4
MIC4807
Micrel
October 1998
7-7
7
Test Circuit and AC Waveform Measurement Standards
V
OUT
7
V
DD
V
IN
V
IN
V
IN
V
DD
=10V
t
Delay
5V
0V
V
IN
10V
0V
V
OUT
All reference times are taken
from the 50% transition point.
V
OUT
3
V
OUT
2
V
OUT
1
V
OUT
0
V
OUT
6
V
OUT
5
V
OUT
4
C = 35pF
R = 10k
R
C
R
C
R
C
R
C
R
C
R
C
R
C
R
C
18
MIC4807
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
MIC4807
Micrel
7-8
October 1998
Truth Table
CS
Clear
Data-In C
IN
B
IN
A
IN
OE
HVOUT
0
HVOUT
1
HVOUT
2
HVOUT
3
HVOUT
4
HVOUT
5
HVOUT
6
HVOUT
7
Functional Mode
X
L
X
X
X
X
X
H
H
H
H
H
H
H
H
Clear
H
H
X
X
X
X
H
P
P
P
P
P
P
P
P
Memory
L
H
D
L
L
L
H
D
P
P
P
P
P
P
P
Address HVOUT
0
L
H
D
L
L
H
H
P
D
P
P
P
P
P
P
Address HVOUT
1
L
H
D
L
H
L
H
P
P
D
P
P
P
P
P
Address HVOUT
2
L
H
D
L
H
H
H
P
P
P
D
P
P
P
P
Address HVOUT
3
L
H
D
H
L
L
H
P
P
P
P
D
P
P
P
Address HVOUT
4
L
H
D
H
L
H
H
P
P
P
P
P
D
P
P
Address HVOUT
5
L
H
D
H
H
L
H
P
P
P
P
P
P
D
P
Address HVOUT
6
L
H
D
H
H
H
H
P
P
P
P
P
P
P
D
Address HVOUT
7
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
Blanking
L = Low Logic Level
X = Don't Care
H = High Logic Level
P = Previous State
D = Data (High or Low)
Equivalent Logic Diagram
+
-
+
-
1.4V
C
IN
B
IN
A
IN
CS
Data-in
Clear
OE
50A
75A
V
DD
Drive
Circuit
Address
Decoder
Drive
Circuit
OVER
TEMP
Total of
8 Channels
C
IN
B
IN
A
IN
CS
Data-in
Clear
OE
HVOUT
7
HVOUT
0
MIC4807
Micrel
October 1998
7-9
7
Typical DC Output Characteristics for the "On" State:
(V
DD
= 10V and T
A
= 25
C unless other wise specified)
V
DD
= 10V
V
DD
= 15V
120
100
80
60
40
20
0
0.5
1.0
I
OUT
FOR SEPARATE V
DD
V
OUT
(V)
I
OUT
(mA)
0
400
300
200
100
0
80
60
40
20
0
SHORT CIRCUIT CURRENT
V
OUT
(V)
I
OUT
(mA)
400
300
200
100
0
0
1
2
3
4
5
EXPANDED VERSION OF SHORT
CIRCUIT CURRENT FOR LOW
OUTPUT VOLTAGE (V
OUT
)
V
OUT
(V)
I
OUT
(mA)
15.0
10.0
5.0
0.0
0.0
5.0
10.0
V
DD
(V)
ON RESISTANCE (R
ON
)
R
ON
(
)
0.0
5.0
10.0
V
OUT
(V)
120
100
80
60
40
20
I
OUT
AT 3 TEMPERATURES
I
OUT
(mA)
0
T = 55
C
T = 25
C
T = 125
C
200
100
0.0
5.0
10.0
V
DD
(V)
SHORT CIRCUIT CURRENT LIMIT (I
SC
)
I
SC
(mA)
0
MIC4807
Micrel
7-10
October 1998
Pin Description
Pin No.
Pin Name
Functional Description
5
Ground
Electrical ground to chip substrate.
12
V
DD
Positive logic supply voltage (10V-15V).
1, 2, 8,
HVOUT
0
through HVOUT
7
These are the high voltage (HV) open outputs, each of which is capable of
9,10, 11,
sinking 100mA when switched on, and standing off 80V when switched off.
17,18
In addition, each output channel is equipped with an analog current limiter
to protect it from shorts to the positive high voltage supply. When an output
is shorted (up to 80V), a maximum of 225mA (200mA nominal) will flow
through it to ground.
13, 14, 15
C
IN
, B
IN
, &A
IN
When these inputs are combined together they form the BCD address used
to select the desired output. Each input is TTL compatible with an internal
pull-up current source of 50mA.
6
CS
When CS is at logic "0" the device is actively addressed, and when CS is
at logic "1" the decoded address and input Data are inhibited, making
the part unaddressable. CS is TTL compatible with an internal pull-down
current sink of 75
A.
7
Clear
Clear resets all the outputs to the off state when pulled to logic "0", and is
TTL compatible with an internal pull-down current sink of 75
A.
16
Data-in
Data-in determines the state of the output being addressed. When Data-
in is at logic "0" the addressed output is turned off, and when Data-in is at
logic "1" the addressed output is turned on. Data-in is TTL compatible with
an internal pull-up current source of 50
A.
4
OE
OE allows the bank of eight outputs to be duty cycled together. When OE
is at logic "1" the outputs are enabled to follow their respective latches, and
when OE is at logic "0" all the outputs are turned off. OE is TTL Compatible
with a pull-down current sink of 75
A.
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