DESCRIPTION
FEATURES
3.3V SINGLE SUPPLY QUAD
PECL-TO-TTL W/LATCHED
OUTPUT ENABLE
Pin
Function
G
T
TTL Ground (0V)
V
T
TTL V
CC
(+3.3V)
V
E
ECL V
CC
(+3.3V)
G
E
ECL Ground (0V)
D, D
Signal Input (PECL)
V
BB
V
BB
Reference Output (PECL)
Q
0
- Q
3
Signal Outputs (TTL)
EN
Enable Input (PECL)
LEN
Latch Enable Input
ClockWorksTM
PRELIMINARY
SY10H841L
SY100H841L
Rev.: C
Amendment: /0
Issue Date: May, 1999
The SY10/100H841L are single supply, low skew
translating 1:4 clock drivers.
The devices feature a 24mA TTL output stage, with
AC performance specified into a 20pF load capacitance.
A latch is provided on-chip. When LEN is LOW (or left
open, in which case it is pulled low by the internal pull-
downs) the latch is transparent. A HIGH on the enable
pin (EN) forces all outputs LOW.
As frequencies increase to 40MHz and above, precise
timing and shaping of clock signals becomes extremely
important. The H841 solves several clock distribution
problems such as minimizing skew (300ps), maximizing
clock fanout (24mA drive), and precise duty cycle control
through a proprietary differential internal design.
The 10K version is compatible with 10KH ECL logic
levels. The 100K version is compatible with 100K levels.
s
3.3V power supply
s
Translates positive ECL to TTL (PECL-to-TTL)
s
300ps pin-to-pin skew
s
500ps part-to-part skew
s
Differential internal design for increased noise
immunity and stable threshold inputs
s
V
BB
reference output
s
Single supply
s
Enable input
s
Latch enable input
s
Extra TTL and ECL power/ground pins to reduce
cross-talk/noise
s
High drive capability: 24mA each output
s
Fully compatible with industry standard 10K, 100K
I/O levels
s
Available in 16-pin SOIC package
BLOCK DIAGRAM
D
Q
0
Q
1
Q
2
Q
3
V
BB
EN
D
D
Q
LEN
PIN CONFIGURATION
PIN NAMES
LEN
Q
3
SOIC
Z16-1
1
16
G
T
2
15
G
E
Q
2
3
14
V
E
V
T
4
13
V
T
5
12
Q
1
6
11
V
BB
G
T
7
10
G
T
Q
0
8
9
EN
D
D
1
2
ClockWorksTM
PRELIMINARY
SY10H841L
SY100H841L
Micrel
TRUTH TABLE
D
LEN
EN
Q
L
L
L
L
H
L
L
H
X
X
H
L
X
H
L
Latch
Pin
Symbol
Description
1
LEN
Latch Enable Input
2
EN
Enable Input (PECL)
3
G
E
ECL Ground (0V)
4
V
E
ECL V
CC
(+3.3V)
5
D
ECL Signal Input (Non-inverting)
6
D
ECL Signal Input (Inverting)
7
V
BB
V
BB
Reference Output (PECL)
8
G
T
TTL Ground (0V)
9
Q
0
Signal Output (TTL)
10
G
T
TTL Ground (0V)
11
Q
1
Signal Output (TTL)
12
V
T
TTL V
CC
(+3.3V)
13
V
T
TTL V
CC
(+3.3V)
14
Q
2
Signal Output (TTL)
15
G
T
TTL Ground (0V)
16
Q
3
Signal Output (TTL)
PIN DESCRIPTION
DC CHARACTERISTICS
V
T
= V
E
= +3.0V to +3.6V
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
I
EE
Power Supply Current
ECL
--
40
--
40
--
40
mA
V
E
Pin
I
CCH
Power Supply Current
TTL
--
20
--
20
--
20
mA
Total all V
T
pins
I
CCL
--
25
--
25
--
25
TTL DC ELECTRICAL CHARACTERISTICS
V
T
= V
E
= +3.0V to +3.6V
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
V
OH
Output HIGH Voltage
2.0
--
2.0
--
2.0
--
V
I
OH
= 3.0mA
V
OL
Output LOW Voltage
--
0.5
--
0.5
--
0.5
V
I
OL
= 24mA
I
OS
Output Short Circuit Current
80
--
80
--
80
--
mA
V
OUT
= 0V
Symbol
Rating
Value
Unit
V
E
(ECL)
Power Supply
0.5 to +7.0
V
V
T
(TTL)
Voltage
0.5 to +7.0
V
I
(ECL)
Input Voltage
0.0 to V
EE
V
V
OUT
(TTL)
0.0 to V
T
T
store
Storage Temperature
65 to +150
C
T
A
Operating Temperature
0 to +85
C
ABSOLUTE MAXIMUM RATINGS
(1)
NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS
are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections
of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions
for extended periods may affect device reliability.
3
ClockWorksTM
PRELIMINARY
SY10H841L
SY100H841L
Micrel
10H ECL DC ELECTRICAL CHARACTERISTICS
(1)
V
T
= V
E
= +3.0V to +3.6V
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
I
IH
Input HIGH Current
--
225
--
175
--
175
A
--
I
IL
Input LOW Current
0.5
--
0.5
--
0.5
--
A
--
V
IH
Input HIGH Voltage
2.130
2.460
2.170
2.490
2.240
2.580
V
V
E
= 3.3V
V
IL
Input LOW Voltage
1.350
1.820
1.350
1.820
1.350
1.855
V
V
E
= 3.3V
V
BB
Output Reference Voltage
1.920
2.030
1.950
2.050
1.990
2.110
V
V
E
= 3.3V
NOTE:
1. ECL V
IH
, V
IL
and V
BB
are referenced to V
CCE
and will vary 1:1 with the power supply. The levels shown are for IVT = IVO = V
CCE
= +3.3V.
V
T
= V
E
= +3.0V to +3.6V
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
I
IH
Input HIGH Current
--
225
--
175
--
175
A
--
I
IL
Input LOW Current
0.5
--
0.5
--
0.5
--
A
--
V
IH
Input HIGH Voltage
2.135
2.420
2.135
2.420
2.135
2.420
V
V
E
= 3.3V
V
IL
Input LOW Voltage
1.490
1.825
1.490
1.825
1.490
1.825
V
V
E
= 3.3V
V
BB
Output Reference Voltage
1.920
2.040
1.920
2.040
1.920
2.040
V
V
E
= 3.3V
100H ECL DC ELECTRICALCHARACTERISTICS
(1)
NOTE:
1. ECL V
IH
, V
IL
and V
BB
are referenced to V
CCE
and will vary 1:1 with the power supply. The levels shown are for IVT = IVO = V
CCE
= +3.3V.
V
T
= V
E
= +3.0V to +3.6V
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
t
PLH
Propagation Delay
Q
0
Q
3
2.2
3.2
2.1
3.1
2.0
3.0
ns
C
L
= 20pF
t
PHL
D to Output
t
skpp
Part-to-Part Skew
(1,4)
Q
0
Q
3
--
0.5
--
0.5
--
0.5
ns
C
L
= 20pF
t
skew++
Within-Device Skew
(2,4)
Q
0
Q
3
--
0.3
--
0.3
--
0.3
ns
C
L
= 20pF
t
skew
Within-Device Skew
(3,4)
Q
0
Q
3
--
0.3
--
0.3
--
0.3
ns
C
L
= 20pF
t
PLH
Propagation Delay
Q
0
Q
3
2.2
3.2
2.1
3.1
2.0
3.0
ns
C
L
= 20pF
t
PHL
LEN to Q
t
PLH
Propagation Delay
Q
0
Q
3
2.2
3.2
2.1
3.1
2.0
3.0
ns
C
L
= 20pF
t
PHL
EN to Output
t
r
Output Rise/Fall Time
Q
0
Q
3
--
1.5
--
1.5
--
1.5
ns
C
L
= 20pF
t
f
1.0V to 2.0V
f
MAX
Max. Input Frequency
(5,6)
Q
0
Q
3
160
--
160
--
160
--
MHz
C
L
= 20pF
--
Pulse Width
Q
0
Q
3
1.5
--
1.5
--
1.5
--
ns
--
--
Recovery Time EN
Q
0
Q
3
1.0
--
1.0
--
1.0
--
ns
--
t
S
Set-up Time D, EN
Q
0
Q
3
0.75
--
0.75
--
0.75
--
ns
--
t
H
Hold Time D, EN
Q
0
Q
3
0.75
--
0.75
--
0.75
--
ns
--
AC CHARACTERISTICS
NOTES:
1. Device-to-Device Skew considering HIGH-to-HIGH transitions at common
V
CC
level.
2. Within-Device Skew considering HIGH-to-HIGH transitions at common
V
CC
level.
3. Within-Device Skew considering LOW-to-LOW transitions at common
V
CC
level.
4. All skew parameters are guaranteed but not tested.
5. Frequency at which output levels will meet a 0.8V to 2.0V minimum swing.
6. The f
MAX
value is specified as the minimum guaranteed maximum
frequency. Actual operational maximum frequency may be greater.
4
ClockWorksTM
PRELIMINARY
SY10H841L
SY100H841L
Micrel
TTL SWITCHING CIRCUIT
PULSE
GENERATOR
IN
OUT
PECL
V
EE
V
CC
& V
CCO
TTL
DEVICE
UNDER
TEST
CH A
OSCILLOSCOPE
CH B
50
COAX
450
USE 0.1
F CAPACITORS
FOR DECOUPLING.
USE OSCILLOSCOPE
INTERNAL 50
LOAD
FOR TERMINATION.
50
COAX
50
COAX
ECL/TTL PROPAGATION DELAY -- SINGLE ENDED
ECL/TTL WAVEFORMS: RISE AND FALL TIMES
V
OUT
T
rise
T
fall
2.0V
0.8V
LOGIC DIAGRAM
PRODUCT ORDERING CODE
Ordering
Package
Operating
Code
Type
Range
SY10H841LZC
Z16-1
Commercial
SY10H841LZCTR
Z16-1
Commercial
SY100H841LZC
Z16-1
Commercial
SY100H841LZCTR
Z16-1
Commercial
V
IN
V
OUT
50%
1.5V
T
pd++
T
pd
5
ClockWorksTM
PRELIMINARY
SY10H841L
SY100H841L
Micrel
16 LEAD SOIC .300" WIDE (Z16-1)
Rev. 03
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
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