TL F 11332

PC8477B

(SuperFDC)

Advanced

Floppy

Disk

Controller

August 1993

PC8477B (SuperFDC

)

Advanced Floppy Disk Controller

General Description

The PC8477B CMOS advanced floppy disk controller is an
enhanced version of National's DP8473 floppy controller
The PC8477B is software compatible with the DP8473 and
NEC mPD765 floppy disk controllers In addition it is pin and
software compatible with the Intel 82077AA floppy control-
ler The PC8477B a 24 MHz crystal a device chip select
and a resistor package are all that is needed for a complete
PC-AT

PS 2

or EISA floppy controller solution

The PC8477B includes advanced features such as a
16 byte FIFO (Burst and Non-Burst modes) support of Per-
pendicular Recording Mode disk drives PS 2 diagnostic
registers for Model 30 and Models 50 60 80 standard
CMOS disk I O and additional commands to control these
new features The 16 byte FIFO will increase system per-
formance at higher data rates and with multi-tasking bus
structures This controller is designed to fit into all PC-AT
EISA and PS 2 designs as well as other advanced applica-
tions

Features

Pin and software compatible with Intel 82077AA FDC

Software compatible with NSC's DP8473

16 byte FIFO (default disabled)

Burst and Non-Burst modes
Programmable threshold

Perpendicular Mode Recording drive support

High performance internal analog data separator (no
external filter components required)

Low power CMOS with manual power down mode

Automatic power down mode for complete software
transparency

Integrates all PC-AT and PS 2 logic

On chip Oscillator
PC compatible FDC address decode
PS 2 Model 30 and Model 50 60 80 diagnostic
registers
DMA control circuitry
High current CMOS disk interface outputs
Data Rate and Digital Output registers
12 mA mP bus interface buffers

Data Rate Support 250 300 kb s 500 kb s
and 1 Mb s

Write precompensation software programmable

68 pin PLCC package

60 pin PQFP package
Ideal for space limited applications

Functional Block Diagram

TL F 11332 3

FIGURE 1-1

SuperFDC

is a trademark of National Semiconductor Corporation

TRI-STATE

is a registered trademark of National Semiconductor Corporation

IBM

PC-AT

and PS 2

are registered trademarks of International Business Machines Corp

C1995 National Semiconductor Corporation

RRD-B30M75 Printed in U S A

Table of Contents

1 0 INTRODUCTION

2 0 PIN DESCRIPTION

3 0 REGISTER DESCRIPTION

3 1 Status Register A (SRA)

3 1 1 SRA

PS 2 Mode

3 1 2 SRA

Model 30 Mode

3 2 Status Register B (SRB)

3 2 1 SRB

PS 2 Mode

3 2 2 SRB

Model 30 Mode

3 3 Digital Output Register (DOR)

3 4 Tape Drive Register (TDR)

3 5 Main Status Register (MSR)

3 6 Data Rate Select Register (DSR)

3 7 Data Register (FIFO)

3 8 Digital Input Register (DIR)

3 8 1 DIR

PC-AT Mode

3 8 2 DIR

PS 2 Mode

3 8 3 DIR

Model 30 Mode

3 9 Configuration Control Register (CCR)

3 9 1 CCR

PC-AT and PS 2 Modes

3 9 2 CCR

Model 30 Mode

3 10 Result Phase Status Registers

3 10 1 Status Register 0 (ST0)

3 10 2 Status Register 1 (ST1)

3 10 3 Status Register 2 (ST2)

3 10 4 Status Register 3 (ST3)

4 0 COMMAND SET DESCRIPTION

4 1 Command Set Summary

4 2 Command Description

4 2 1 Configure Command

4 2 2 Dumpreg Command

4 2 3 Format Command

4 2 4 Invalid Command

4 2 5 Lock Command

4 2 6 Mode Command

4 2 7 NSC Command

4 2 8 Perpendicular Mode Command

4 2 9 Read Data Command

4 2 10 Read Deleted Data Command

4 2 11 Read ID Command

4 2 12 Read A Track Command

4 2 13 Recalibrate Command

4 2 14 Relative Seek Command

4 2 15 Scan Commands

4 2 16 Seek Command

4 2 17 Sense Drive Status Command

4 2 18 Sense Interrupt Command

4 2 19 Set Track Command

4 2 20 Specify Command

4 2 21 Verify Command

4 2 22 Version Command

4 2 23 Write Data Command

4 2 24 Write Deleted Data Command

5 0 FUNCTIONAL DESCRIPTION

5 1 Microprocessor Interface

5 2 Modes of Operation

5 3 Controller Phases

5 3 1 Command Phase

5 3 2 Execution Phase

5 3 2 1 DMA Mode

FIFO Disabled

5 3 2 2 DMA Mode

FIFO Enabled

5 3 2 3 Interrupt Mode

FIFO Disabled

5 3 2 4 Interrupt Mode

FIFO Enabled

5 3 2 5 Software Polling

5 3 3 Result Phase

5 3 4 Idle Phase

5 3 5 Drive Polling Phase

5 4 Data Separator

5 5 Crystal Oscillator

5 6 Dynamic Window Margin Performance

5 7 Perpendicular Recording Mode

5 8 Data Rate Selection

5 9 Write Precompensation

5 10 Low Power Mode Logic

5 11 Reset Operation

6 0 DEVICE DESCRIPTION

6 1 DC Electrical Characteristics

6 2 AC Electrical Characteristics

6 2 1 AC Test Conditions

6 2 2 Clock Timing

6 2 3 Microprocessor Read Timing

6 2 4 Microprocessor Write Timing

6 2 5 DMA Timing

6 2 6 Reset Timing

6 2 7 Write Data Timing

6 2 8 Drive Control Timing

6 2 9 Read Data Timing

7 0 REFERENCE SECTION

7 1 Mnemonic Definitions for PC8477B Commands

7 2 PC8477B Enhancements vs 82077AA

7 3 PC8477B Interface in a PC-AT

7 4 Software Initialization Sequence

7 5 PC8477B PC8477A differences

7 6 Revision History

List of Figures

PC8477B Functional Block Diagram

1-1

PC8477B Pin Diagram for 68 Pin PLCC and 60 Pin PQFP

1-2

IBM

Perpendicular and ISO Formats Supported by Format Command

4-1

PC8477B Data Separator Block Diagram

5-1

Read Data Algorithm

State Diagram

5-2

PC8477B Dynamic Window Margin Performance

5-3

PC8477B Dynamic Window Margin Performance with

3% ISV

5-4

Perpendicular Recording Drive R W Head and Pre-Erase Head

5-5

Clock Timing

6-1

Microprocessor Read Timing

6-2

Microprocessor Write Timing

6-3

DMA Timing

6-4

Reset Timing

6-5

Write Data Timing

6-6

Drive Control Timing

6-7

Read Data Timing

6-8

PC8477B in a PC-AT System

7-1

PC84777B Initialization

7-2

List of Tables

3-1

Drive Enable Values

3-2

Tape Drive Assignment Values

3-3

Write Precompensation Delays

3-4

Default Precompensation Delays

3-5

Data Rate Select Encoding

3-6

Typical Format Gap Length Values

4-1

DENSEL Encoding

4-2

DENSEL Default Encoding

4-3

Effects of WGATE and GAP

4-4

Sector Size Selection

4-5

SK Effect of Read Data Command

4-6

Result Phase Termination Values with No Error

4-7

SK Effect on Read Deleted Data Command

4-8

Maximum Recalibrate Step Pulses Based on R255 and ETR

4-9

Scan Command Termination Values

4-10

Status Register 0 Termination Codes

4-11

Set Track Register Address

4-12

Step Rate (SRT) Values

4-13

Motor Off Time (MFT) Values

4-14

Motor On Time (MNT) Values

4-15

Verify Command Result Phase Table

4-16

Nominal t

ICP

DRP

Values

6-1

Minimum t

WDW

Values

6-2

PC8477B 82077 Parameter Comparison

7-1

Density Encoding

7-2

1 0 Introduction

The PC8477B advanced floppy disk controller is suitable for
all PC-AT EISA PS 2 and general purpose applications
The operational mode (PC-AT PS 2 and Model 30) of the
PC8477B is determined by hardware strapping of the IDENT
and MFM pins DP8473 and Intel 82077AA software com-
patibility is provided Key features include the 16 byte FIFO
PS 2 diagnostic register support the perpendicular record-
ing mode CMOS disk interface and a high performance
analog data separator

The PC8477B supports the standard PC data rates of 250
300 500 kb s and 1 Mb s in MFM encoded data mode but
is no longer guaranteed through functional testing to sup-
port the older FM encoded data mode References to the
older FM mode remain in this document to clarify the true
functional operation of the device

The 1 Mb s data rate is used by new high performance tape
and floppy drives emerging in the PC market today The new
floppy drives utilize high density media which requires the
PC8477B supported perpendicular recording mode format
When used with the 1 Mb s data rate this new format allows
the use of 4 Mb floppy drives which format ED media to
2 88 MB data capacity

The high performance internal analog data separator needs
no external components It improves on the window margin
performance standards of the DP8473 and is compatible
with the strict data separator requirements of floppy and
floppy-tape drives

The PC8477B contains write precompensation and circuitry
that will default to 125 ns for 250 300 and 500 kb s
41 67 ns at 1 Mb s These values can be overridden
through software to disable write precompensation or to
provide levels of precompensation up to 250 ns The
PC8477B has internal 12 mA data bus buffers which allow
direct connection to the system bus The internal 48 mA
totem-pole disk interface buffers are compatible with both
CMOS drive inputs and 150X resistor terminated disk drive
inputs

The PC8477B is available in a 68 pin Plastic Leaded Chip
Carrier (PLCC) package and in a 60 pin Plastic Quad Flat
Package (PQFP)

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