1.
General description
The LPC2101/2102/2103 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S
CPU with real-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB
of embedded high-speed flash memory. A 128-bit wide memory interface and a unique
accelerator architecture enable 32-bit code execution at the maximum clock rate. For
critical performance in interrupt service routines and DSP algorithms, this increases
performance up to 30 % over Thumb mode. For critical code size applications, the
alternative 16-bit Thumb mode reduces code by more than 30 % with minimal
performance penalty.
Due to their tiny size and low power consumption, the LPC2101/2102/2103 are ideal for
applications where miniaturization is a key requirement. A blend of serial communications
interfaces ranging from multiple UARTs, SPI to SSP and two I
2
C-buses, combined with
on-chip SRAM of 2 kB/4 kB/8 kB, make these devices very well suited for communication
gateways and protocol converters. The superior performance also makes these devices
suitable for use as math coprocessors. Various 32-bit and 16-bit timers, an improved
10-bit ADC, PWM features through output match on all timers, and 32 fast GPIO lines with
up to nine edge or level sensitive external interrupt pins make these microcontrollers
particularly suitable for industrial control and medical systems.
2.
Features
2.1 Key features
s
16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP48 package.
s
2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip flash program
memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation.
s
ISP/IAP via on-chip bootloader software. Single flash sector or full chip erase in
100 ms and programming of 256 bytes in 1 ms.
s
EmbeddedICE RT offers real-time debugging with the on-chip RealMonitor software.
s
The 10-bit A/D converter provides eight analog inputs, with conversion times as low as
2.44
s per channel and dedicated result registers to minimize interrupt overhead.
s
Two 32-bit timers/external event counters with combined seven capture and seven
compare channels.
s
Two 16-bit timers/external event counters with combined three capture and seven
compare channels.
s
Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz
clock input.
s
Multiple serial interfaces including two UARTs (16C550), two Fast I
2
C-buses
(400 kbit/s), SPI and SSP with buffering and variable data length capabilities.
LPC2101/2102/2103
Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB
flash with ISP/IAP, fast ports and 10-bit ADC
Rev. 01 -- 18 January 2006
Preliminary data sheet
LPC2101_02_03_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 January 2006
2 of 32
Philips Semiconductors
LPC2101/2102/2103
Single-chip 16-bit/32-bit microcontrollers
s
Vectored interrupt controller with configurable priorities and vector addresses.
s
Up to thirty-two 5 V tolerant fast general purpose I/O pins.
s
Up to 13 edge or level sensitive external interrupt pins available.
s
70 MHz maximum CPU clock available from programmable on-chip PLL with a
possible input frequency of 10 MHz to 25 MHz and a settling time of 100
s.
s
On-chip integrated oscillator operates with an external crystal in the range from 1 MHz
to 25 MHz.
s
Power saving modes include Idle mode, Power-down mode with RTC active, and
Power-down mode.
s
Individual enable/disable of peripheral functions as well as peripheral clock scaling for
additional power optimization.
s
Processor wake-up from Power-down mode via external interrupt or RTC.
3.
Ordering information
3.1 Ordering options
Table 1:
Ordering information
Type number
Package
Name
Description
Version
LPC2101FBD48
LQFP48
plastic low profile quad flat package; 48 leads;
body 7
7
1.4 mm
SOT313-2
LPC2102FBD48
LQFP48
plastic low profile quad flat package; 48 leads;
body 7
7
1.4 mm
SOT313-2
LPC2103FBD48
LQFP48
plastic low profile quad flat package; 48 leads;
body 7
7
1.4 mm
SOT313-2
LPC2103FA44
PLCC44
plastic leaded chip carrier; 44 leads
SOT187-2
Table 2:
Ordering options
Type number
Flash
memory
RAM
ADC
Temperature
range (
C)
LPC2101FBD48
8 kB
2 kB
8 inputs
-
40 to +85
LPC2102FBD48
16 kB
4 kB
8 inputs
-
40 to +85
LPC2103FBD48
32 kB
8 kB
8 inputs
-
40 to +85
LPC2103FA44
32 kB
8 kB
8 inputs
-
40 to +85
LPC2101_02_03_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 January 2006
3 of 32
Philips Semiconductors
LPC2101/2102/2103
Single-chip 16-bit/32-bit microcontrollers
4.
Block diagram
(1) Pins shared with GPIO.
Fig 1.
Block diagram
002aab814
system
clock
TRST
TMS
TCK
TDI
TDO
XTAL2 V
DD(3V3)
XTAL1
AMBA AHB
(Advanced High-performance Bus)
MEMORY
ACCELERATOR
AHB BRIDGE
TEST/DEBUG
INTERFACE
AHB TO APB
BRIDGE
VECTORED
INTERRUPT
CONTROLLER
SYSTEM
FUNCTIONS
PLL
8 kB/16 kB/
32 kB FLASH
ARM7TDMI-S
LPC2101/2102/2103
INTERNAL
SRAM
CONTROLLER
2 kB/4 kB/
8 kB SRAM
ARM7 local bus
APB (ARM
peripheral bus)
SCL0, SCL1
(1)
SDA0, SDA1
(1)
3
CAP0
(1)
4
CAP1
(1)
3
CAP2
(1)
3
MAT0
(1)
4
MAT1
(1)
3
MAT2
(1)
4
MAT3
(1)
AD0[7:0]
I
2
C-BUS SERIAL
INTERFACES 0 AND 1
CAPTURE/COMPARE
EXTERNAL COUNTER
TIMER 0/TIMER 1/
TIMER 2/TIMER 3
EINT2 to
EINT0
(1)
EXTERNAL
INTERRUPTS
SCK0, SCK1
(1)
MOSI0, MOSI1
(1)
MISO0, MISO1
(1)
SSEL0, SSEL1
(1)
SPI AND SSP
SERIAL INTERFACES
ADC
TXD0, TXD1
(1)
RXD0, RXD1
(1)
UART0/UART1
RTXC2
RTXC1
VBAT
REAL-TIME CLOCK
WATCHDOG
TIMER
SYSTEM CONTROL
P0[31:0]
P0[31:0]
GENERAL
PURPOSE I/O
HIGH SPEED
GENERAL
PURPOSE I/O
RST
V
SS
8 kB
BOOT ROM
V
DD(1V8)
DSR1, CTS1,
RTS1, DTR1
DCD1, RI1
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