LPC2212/LPC2214
16/32-bit ARM microcontrollers; 128/256 kB ISP/IAP Flash
with 10-bit ADC and external memory interface
Rev. 02 -- 23 December 2004
Product data
1.
General description
The LPC2212/LPC2214 are based on a 16/32 bit ARM7TDMI-STM CPU with real-time
emulation and embedded trace support, together with 128/256 kilobytes (kB) of
embedded high speed flash memory. A 128-bit wide memory interface and a unique
accelerator architecture enable 32-bit code execution at maximum clock rate. For
critical code size applications, the alternative 16-bit Thumb
Mode reduces code by
more than 30 % with minimal performance penalty.
With their 144 pin package, low power consumption, various 32-bit timers, 8-channel
10-bit ADC, PWM channels and up to 9 external interrupt pins these microcontrollers
are particularly suitable for industrial control, medical systems, access control and
point-of-sale. Number of available GPIOs ranges from 76 (with external memory)
through 112 pins (single-chip). With a wide range of serial communications
interfaces, they are also very well suited for communication gateways, protocol
converters and embedded soft modems as well as many other general-purpose
applications.
2.
Features
2.1 Key features
s
16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package.
s
16 kB on-chip Static RAM and 128/256 kB on-chip Flash Program Memory.
128-bit wide interface/accelerator enables high speed 60 MHz operation.
s
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
boot-loader software. Flash programming takes 1 ms per 512 byte line. Single
sector or full chip erase takes 400 ms.
s
EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with
the on-chip RealMonitorTM software as well as high speed real-time tracing of
instruction execution.
s
Eight channel 10-bit A/D converter with conversion time as low as 2.44
s.
s
Two 32-bit timers (with 4 capture and 4 compare channels), PWM unit (6 outputs),
Real Time Clock and Watchdog.
s
Multiple serial interfaces including two UARTs (16C550), Fast I
2
C (400 kbits/s)
and two SPIs.
s
Vectored Interrupt Controller with configurable priorities and vector addresses.
s
Configurable external memory interface with up to four banks, each up to 16 Mb
and 8/16/32 bit data width.
s
Up to 112 general purpose I/O pins (5 V tolerant). Up to 9 edge or level sensitive
external interrupt pins available.
Philips Semiconductors
LPC2212/LPC2214
16/32-bit ARM microcontrollers with external memory interface
Product data
Rev. 02 -- 23 December 2004
2 of 40
9397 750 13149
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
s
60 MHz maximum CPU clock available from programmable on-chip
Phase-Locked Loop with settling time of 100
s.
s
On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
s
Two low power modes, Idle and Power-down.
s
Processor wake-up from Power-down mode via external interrupt.
s
Individual enable/disable of peripheral functions for power optimization.
s
Dual power supply:
x
CPU operating voltage range of 1.65 V to 1.95 V (1.8 V
0.15 V).
x
I/O power supply range of 3.0 V to 3.6 V (3.3 V
10 %) with 5 V tolerant I/O
pads. 16/32-bit ARM7TDMI-S processor.
3.
Ordering information
3.1 Ordering options
Table 1:
Ordering information
Type number
Package
Name
Description
Version
LPC2212FBD144 LQFP144
plastic low-profile quad flat package; 144
leads; body 20
20
1.4 mm
SOT486-1
LPC2214FBD144 LQFP144
plastic low-profile quad flat package; 144
leads; body 20
20
1.4 mm
SOT486-1
Table 2:
Part options
Type number
Flash memory
RAM
CAN
Temperature
range (
C)
LPC2212FBD144
128 kB
16 kB
-
-
40 to +85
LPC2214FBD144
256 kB
16 kB
-
-
40 to +85
Philips Semiconductors
LPC2212/LPC2214
16/32-bit ARM microcontrollers with external memory interface
Product data
Rev. 02 -- 23 December 2004
3 of 40
9397 750 13149
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
4.
Block diagram
(1) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
Fig 1.
Block diagram.
INTERNAL
FLASH
CONTROLLER
002aaa732
AHB BRIDGE
EMULATION TRACE
MODULE
TEST/DEBUG
INTERFACE
AHB
DECODER
AHB TO VPB
BRIDGE
VPB
DIVIDER
VECTORED INTERRUPT
CONTROLLER
SYSTEM
FUNCTIONS
PLL
system
clock
SCL
P0.30:0
P1.31:16, 1:0
P2.31:0
P3.31:0
PWM6:1
SDA
TRST
(1)
TMS
(1)
TCK
(1)
TDI
(1)
TDO
(1)
XTAL2
XTAL1
RESET
SCK0,1
MOSI0,1
MISO0,1
EINT3:0
8 x CAP0
8 x MAT
Ain3:0
Ain7:4
SSEL0,1
TxD0,1
RxD0,1
DSR1,CTS1,
DCD1, RI1
SPI SERIAL
INTERFACES 0 & 1
I2C SERIAL
INTERFACE
CS3:0*
A23:0*
BLS3:0*
OE, WE*
D31:0*
EXTERNAL MEMORY
CONTROLLER
UART 0 & 1
WATCHDOG
TIMER
SYSTEM
CONTROL
EXTERNAL
INTERRUPTS
GENERAL
PURPOSE I/O
CAPTURE/
COMPARE
TIMER 0 & 1
A/D
CONVERTER
PWM0
REAL TIME
CLOCK
AMBA AHB
(Advanced High-performance Bus)
128/256 kB
FLASH
ARM7TDMI-S
INTERNAL SRAM
CONTROLLER
16 kB
SRAM
ARM7 LOCAL BUS
VPB (VLSI
peripheral bus)
*Shared with GPIO
Philips Semiconductors
LPC2212/LPC2214
16/32-bit ARM microcontrollers with external memory interface
Product data
Rev. 02 -- 23 December 2004
4 of 40
9397 750 13149
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5.
Pinning information
5.1 Pinning
Fig 2.
LQFP144 pinning.
handbook, full pagewidth
002aaa733
LPC2212/LPC2214
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
P2.22/D22
V3
VSS
P0.21/PWM5/CAP1.3
P0.22/CAP0.0/MAT0.0
P0.23
P1.19/TRACEPKT3
P0.24
VSS
P2.23/D23
P2.24/D24
P2.25/D25
P2.26/D26/BOOT0
V3A
P1.18/TRACEPKT2
P2.27/D27/BOOT1
P2.28/D28
P2.29/D29
P2.30/D30/AIN4
P2.31/D31/AIN5
P0.25
NC
P0.27/AIN0/CAP0.1/MAT0.1
P1.17/TRACEPKT1
P0.28/AIN1/CAP0.2/MAT0.2
VSS
P3.29/BLS2/AIN6
P3.28/BLS3/AIN7
P3.27/WE
P3.26/CS1
V3
P0.29/AIN2/CAP0.3/MAT0.3
P0.30/AIN3/EINT3/CAP0.0
P1.16/TRACEPKT0
P3.25/CS2
P3.24/CS3
P2.3/D3
VSS
P2.2/D2
P2.1/D1
V3
VSS
P1.20/TRACESYNC
P0.17/CAP1.2/SCK1/MAT1.2
P0.16/EINT0/MAT0.2/CAP0.2
P0.15/RI1/EINT2
P2.0/D0
P3.30/BLS1
P3.31/BLS0
P1.21/PIPESTAT0
V3
VSS
P0.14/DCD1/EINT1
P1.0/CS0
P1.1/OE
P3.0/A0
P3.1/A1
P3.2/A2
P1.22/PIPESTAT1
P0.13/DTR1/MAT1.1
P0.12/DSR1/MAT1.0
P0.11/CTS1/CAP1.1
P1.23/PIPESTAT2
P3.3/A3
P3.4/A4
VSS
P0.10/RTS1/CAP1.0
V3
P0.9/RxD1/PWM6/EINT3
P0.8/TxD1/PWM4
P3.5/A5
P3.6/A6
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
P1.27/TDO
V
18A
XTAL1
XTAL2
P1.28/TDI
V
SSA
V
SSA_PLL
P2.21/D21
P2.20/D20
RESET
P2.19/D19
P2.18/D18
P2.17/D17
P2.16/D16
P2.15/D15
P2.14/D14
V
SS
P2.13/D13
P1.29/TCK
P2.12/D12
P2.11/D11
P0.20/MAT1.3/SSEL1/EINT3
P0.19/MAT1.2/MOSI1/CAP1.2
P0.18/CAP1.3/MISO1/MAT1.3
P2.10/D10
V
3
P2.9/D9
P2.8/D8
P2.7/D7
P2.6/D6
P2.5/D5
P1.30/TMS
V
3
V
SS
V
18
P2.4/D4
V
18
V
SS
V
3
P3.23/A23/XCLK
P3.22/A22
P0.0/TxD0/PWM1
P1.31/TRST
P3.21/A21
P3.20/A20
P3.19/A19
P3.18/A18
P3.17/A17
P0.1/RxD0/PWM3/EINT0
P0.2/SCL/CAP0.0
V
3
P1.26/RTCK
P3.16/A16
V
SS
P3.15/A15
P3.14/A14
V
3
P0.3/SDA/MAT0.0/EINT1
P0.4/SCK0/CAP0.1
P1.25/EXTIN0
P0.5/MISO0/MAT0.1
P3.13/A13
P3.12/A12
P3.11/A11
P3.10/A10
P3.9/A9
V
SS
P0.6/MOSI0/CAP0.2
P0.7/SSEL0/PWM2/EINT2
P1.24/TRACECLK
P3.8/A8
P3.7/A7
Philips Semiconductors
LPC2212/LPC2214
16/32-bit ARM microcontrollers with external memory interface
Product data
Rev. 02 -- 23 December 2004
5 of 40
9397 750 13149
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5.2 Pin description
Table 3:
Pin description
Symbol
Pin
Type
Description
P0.0 to P0.31
I/O
Port 0: Port 0 is a 32-bit bi-directional I/O port with individual direction
controls for each bit. The operation of port 0 pins depends upon the pin
function selected via the Pin Connect Block.
Pins 26 and 31 of port 0 are not available.
P0.0
42
O
TxD0 -- Transmitter output for UART0.
O
PWM1 -- Pulse Width Modulator output 1.
P0.1
49
I
RxD0 -- Receiver input for UART0.
O
PWM3 -- Pulse Width Modulator output 3.
I
EINT0 -- External interrupt 0 input
P0.2
50
I/O
SCL -- I
2
C clock input/output. Open drain output (for I
2
C compliance).
I
CAP0.0 -- Capture input for Timer0, channel 0.
P0.3
58
I/O
SDA -- I
2
C data input/output. Open drain output (for I
2
C compliance).
O
MAT0.0 -- Match output for Timer0, channel 0.
I
EINT1 -- External interrupt 1 input.
P0.4
59
I/O
SCK0 -- Serial clock for SPI0. SPITM clock output from master or input to
slave.
I
CAP0.1 -- Capture input for Timer0, channel 1.
P0.5
61
I/O
MISO0 -- Master In Slave OUT for SPI0. Data input to SPI master or data
output from SPI slave.
O
MAT0.1 -- Match output for Timer0, channel 1.
P0.6
68
I/O
MOSI0 -- Master Out Slave In for SPI0. Data output from SPI master or data
input to SPI slave.
I
CAP0.2 -- Capture input for Timer0, channel 2.
P0.7
69
I
SSEL0 -- Slave Select for SPI0. Selects the SPI interface as a slave.
O
PWM2 -- Pulse Width Modulator output 2.
I
EINT2 -- External interrupt 2 input.
P0.8
75
O
TxD1 -- Transmitter output for UART1.
O
PWM4 -- Pulse Width Modulator output 4.
P0.9
76
I
RxD1 -- Receiver input for UART1.
O
PWM6 -- Pulse Width Modulator output 6.
I
EINT3 -- External interrupt 3 input.
P0.10
78
O
RTS1 -- Request to Send output for UART1.
I
CAP1.0 -- Capture input for Timer1, channel 0.
P0.11
83
I
CTS1 -- Clear to Send input for UART1.
I
CAP1.1 -- Capture input for Timer1, channel 1.
P0.12
84
I
DSR1 -- Data Set Ready input for UART1.
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