Document Outline
- FEATURES
- STRUCTURE
- PIN CONFIGURATION
- DESCRIPTION
- ARCHITECTURE
- ORDERING INFORMATION
- DESIGN DEVELOPMENT TOOLS
- SNAP
- DESIGN SECURITY
- PROGRAMMING/SOFTWARE SUPPORT
- PLHS501 FUNCTIONAL BLOCK DIAGRAM
- FUNCTIONAL DIAGRAM
- ABSOLUTE MAXIMUM RATINGS
- THERMAL RATINGS
- VIRGIN STATE
- DC ELECTRICAL CHARACTERISTICS
- TEST LOAD CIRCUITS
- VOLTAGE WAVEFORMS
- SNAP RESOURCE SUMMARY DESIGNATIONS
- MACRO CELL SPECIFICATIONS
- PLHS501 GATE AND SPEED ESTIMATE TABLE
- APPLICATIONS
47
48
49
50
51
52
33
32
31
29 30
28
27
26
25
24
23
22
21
2
3
4
5
6
7
20
19
18
17
16
15
14
13
12
11
10
9
8
34
35
36
37
38
39
40
41
42
43
44
45
46
1
A Package
(52-pin PLCC)
I11
I12
I10
I13
I14
I15
I16
I17
I9 I8 I7 I6 I5
VCC
I4
I3
I2
I1
I0
B3
B2
B1
B0
X7
X6
GND
GND
X5
X4
X3
X2
X1
X0
O7
O6
O5
O4
O3
O2
O1
O0
B7
B6
B5
B4
I23
I22
I21
I20
I19
I18
VCC
Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501
I
Programmable macro logic
PML
TM
1
October 22, 1993
8531207 11164
FEATURES
Programmable Macro Logic device
Full connectivity
TTL compatible
SNAP development system:
Supports third-party schematic entry
formats
Macro library
Versatile netlist format for design
portability
Logic, timing, and fault simulation
Delay per internal NAND function = 6.5ns
(typ)
Testable in unprogrammed state
Security fuse allows protection of
proprietary designs
STRUCTURE
NAND gate based architecture
72 foldback NAND terms
136 input-wide logic terms
44 additional logic terms
24 dedicated inputs (I
0
I
23
)
8 bidirectional I/Os with individual 3-State
enable:
4 Active-High (B
4
B
7
)
4 Active-Low (B
0
B
3
)
16 dedicated outputs:
4 Active-High outputs
O
0
, O
1
with common 3-State enable
O
2
, O
3
with common 3-State enable
4 Active-Low outputs:
O
4
, O
5
with common 3-State enable
O
6
, O
7
with common 3-State enable
8 Exclusive-OR outputs:
X
0
, X
1
with common 3-State enable
X
2
, X
3
with common 3-State enable
X
4
, X
5
with common 3-State enable
X
6
, X
7
with common 3-State enable
PIN CONFIGURATION
DESCRIPTION
The PLHS501 is a high-density Bipolar
Programmable Macro Logic device. PML
incorporates a programmable NAND
structure. The NAND architecture is an
efficient method for implementing any logic
function. The SNAP software development
system provides a user friendly environment
for design entry. SNAP eliminates the need
for a detailed understanding of the PLHS501
architecture and makes it transparent to the
user. PLHS501 is also supported on the
Philips Semiconductors SNAP software
development systems.
The PLHS501 is ideal for a wide range of
microprocessor support functions, including
bus interface and control applications.
The PLHS501 is also processed to industrial
requirements for operation over an extended
temperature range of 40
C to +85
C and
supply voltage of 4.5V to 5.5V.
ARCHITECTURE
The core of the PLHS501 is a programmable
fuse array of 72 NAND gates. The output of
each gate folds back upon itself and all other
NAND gates. In this manner, full connectivity
of all logic functions is achieved in the
PLHS501. Any logic function can be created
within the core of the device without wasting
valuable I/O pins. Furthermore, a speed
advantage is acquired by implementing
multi-level logic within a fast internal core
without incurring any delays from the I/O
buffers.
PML is a trademark of Philips Semiconductors
Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501
I
Programmable macro logic
PML
TM
October 22, 1993
2
ORDERING INFORMATION
DESCRIPTION
OPERATING CONDITIONS
ORDER CODE
DRAWING NUMBER
52-Pin Plastic Leaded Chip Carrier
Commercial Temperature Range
5% Power Supply
PLHS501A
0397E
52-Pin Plastic Leaded Chip Carrier
Industrial Temperature Range
10% Power Supply
PLHS501
I
A
0397E
DESIGN DEVELOPMENT TOOLS
SNAP
The SNAP Software Development System
provides the necessary tools for designing
with PML. SNAP provides the following:
Schematic entry netlist generation from
third-party schematic design packages
such as OrCAD/SDT III
TM
and
FutureNet
TM
.
Macro library for standard TTL functions
and user defined functions
Boolean equation entry
State equation entry
Syntax and design entry checking
Simulator includes logic simulation, fault
simulation and timing simulation.
SNAP operates on an IBM
PC/XT, PC/AT,
PS/2, or any compatible system with DOS
2.1 or higher. The minimum system
configuration for SNAP is 640K bytes of RAM
and a hard disk.
SNAP provides primitive PML function
libraries for third-party schematic design
packages. Custom macro function libraries
can be defined in schematic or equation form.
After the completion of a design, the software
compiles the design for syntax and
completeness. Complete simulation can be
carried out using the different simulation tools
available.
The programming data is generated in
JEDEC format. Using the Device
Programmer Interface (DPI) module of SNAP,
the JEDEC fusemap is sent from the host
computer to the device programmer.
DESIGN SECURITY
The PLHS501 has a programmable security
fuse that controls the access to the data
programmed in the device. By using this
programmable feature, proprietary designs
implemented in the device cannot be copied
or retrieved.
PROGRAMMING/SOFTWARE
SUPPORT
Refer to Section 9
(Development Software)
and Section 10
(Third-party Programmer/
Software Support) of this data handbook for
additional information.
FutureNet is a trademark of FutureNet Corporation.
OrCAD/SDT is a trademark of OrCAD, Inc.
IBM is a registered trademark of International Business Machines Corporation.
Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501
I
Programmable macro logic
PML
TM
October 22, 1993
3
PLHS501 FUNCTIONAL BLOCK DIAGRAM
I
N
T
E
R
C
O
N
N
E
C
T
24
DEDICATED
INPUTS
NAND
ARRAY
16
DEDICATED
OUTPUTS
8
BIDIRECTIONAL
I/OS
Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501
I
Programmable macro logic
PML
TM
October 22, 1993
4
FUNCTIONAL DIAGRAM
I0
I23
71
0
x4
x4
x4
x2
x2
B0 B3
B4 B7
X0, X2, X4, X6
X1, X3, X5, X7
O0, O2
O1, O3
O4, O6
O5, O7
x4
x2
x2
x4
x4
x4
x4
x4
x4
x4
x2
x2
x2
x2
x2
x2
x4
DETAIL A
Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501
I
Programmable macro logic
PML
TM
October 22, 1993
5
DETAIL A
40
39
38
37
15
16
17
18
28
29
30
31
32
33
35
36
19
21
22
23
24
25
26
27
B3
B2
B0
B1
B4
B5
B7
B6
X0
X1
X2
X3
X4
X5
X7
X6
O0
O1
O2
O3
O4
O5
O7
O6
Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501
I
Programmable macro logic
PML
TM
October 22, 1993
6
ABSOLUTE MAXIMUM RATINGS
1
RATINGS
SYMBOL
PARAMETER
MIN
MAX
UNIT
V
CC
Supply voltage
+7
V
DC
V
IN
Input voltage
+5.5
V
DC
V
OUT
Output voltage
+5.5
V
DC
I
IN
Input currents
30
+30
mA
I
OUT
Output currents
+100
mA
T
amb
Operating temperature range
0
+75
C
T
stg
Storage temperature range
65
+150
C
NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device.
This is a stress rating only. Functional operation at these or any other condition above
those indicated in the operational and programming specification of the device is not
implied.
THERMAL RATINGS
TEMPERATURE
Maximum junction
150
C
Maximum ambient
75
C
Allowable thermal rise
ambient to junction
75
C
VIRGIN STATE
A factory shipped virgin device contains all
fusible links open, such that:
1. All product terms are enabled.
2. All bidirectional (B) pins are outputs.
3. All outputs are enabled.
4. All outputs are Active-High except
B
0
B
3
(fusible I/O) and O
4
O
7
which
are Active-Low.
+5V
CL
R1
R2
S1
GND
BZ
BY
INPUTS
I0
I10
BW
BX
OUTPUTS
C2
C1
DUT
NOTE:
C1 and C2 are to bypass VCC to GND.
VCC
OX
Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501
I
Programmable macro logic
PML
TM
October 22, 1993
7
DC ELECTRICAL CHARACTERISTICS
Commercial= 0
C
T
amb
+75
C, 4.75V
V
CC
5.25V
Industrial
= 40
C
T
amb
+85
C, 4.5V
V
CC
5.5V
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP
1
MAX
UNIT
Input voltage
2
V
IL
Low
V
CC
= MIN
0.8
V
V
IH
High
V
CC
= MAX
2.0
V
V
IC
Clamp
2, 3
V
CC
= MIN, I
IN
= 12mA
0.8
1.2
V
Output voltage
V
CC
= MIN
V
OL
Low
2, 4
I
OL
= 10mA
0.45
V
V
OH
High
2, 5
I
OH
= 2mA
2.4
V
Input current
V
CC
= MAX
I
IL
Low
V
IN
= 0.45V
100
A
I
IH
High
V
IN
= 5.5V
40
A
Output current
V
CC
= MAX
I
O(OFF)
Hi-Z state
9
V
OUT
= 5.5V
80
A
V
OUT
= 0.45V
140
I
OS
Short circuit
3, 5, 6
V
OUT
= 0V
15
70
mA
I
CC
V
CC
supply current
8
V
CC
= MAX
225
295
mA
Capacitance
V
CC
= 5V
C
IN
Input
V
IN
= 2.0V
8
pF
C
B
I/O
V
OUT
= 2.0V
15
pF
NOTES:
1. All typical values are at V
CC
= 5V, T
amb
= +25
C.
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. For Pins 15 19, 21 27 and 37 40, V
OL
is measured with Pins 5 and 41 = 8,75V, Pin 43 = 0V and Pins 42 and 44 = 4.5V.
For Pins 28 33 and 35 36, V
OL
is measured under same conditions EXCEPT Pin 44 = 0V.
5. V
OH
is measured with Pins 5 and 41 = 8.75V, Pins 42 and 43 = 4.5V and Pin 44 = 0V.
6. Duration of short circuit should not exceed 1 second.
7. I
CC
is measured with all dedicated inputs at 0V and bidirectional and output pins open.
8. Measured at V
T
= V
OL
+ 0.5V.
9. Leakage values are a combination of input and output leakage.
TEST LOAD CIRCUITS
VOLTAGE WAVEFORMS
MEASUREMENTS:
All circuit delays are measured at the +1.5V level
of inputs and outputs, unless otherwise specified.
Input Pulses
90%
10%
2.5ns
90%
10%
+3.0V
+3.0V
0V
0V
tR
tF
2.5ns
2.5ns
2.5ns
Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501
I
Programmable macro logic
PML
TM
October 22, 1993
8
SNAP RESOURCE SUMMARY DESIGNATIONS
I0
I23
71
0
x4
x4
x4
x2
x2
B0 B3
B4 B7
X0, X2, X4, X6
X1, X3, X5, X7
O0, O2
O1, O3
O4, O6
O5, O7
x4
x2
x2
x4
x4
x4
x4
x4
x4
x4
x2
x2
x2
x2
x2
x2
x4
DIN501
NIN501
FBNAND
NAND
OUT501
NOU501
EXO501
NOU501
TOU501
Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501
I
Programmable macro logic
PML
TM
October 22, 1993
9
MACRO CELL SPECIFICATIONS
1
(SNAP Resource Summary Designations in Parantheses)
Commercial:T
amb
= 0
C to +75
C, 4.75V
V
CC
5.25V, C
L
= 30pF, R
2
= 1000
, R
1
= 470
Industrial:
T
amb
= 40
C to +85
C, 4.5V
V
CC
5.5V, C
L
= 30pF, R
2
= 1000
, R
1
= 470
Input Buffer
(DIN501 [Non-inverting], NIN501 [Inverting])
I
X
Y
LIMITS
SYMBOL
MIN
TYP
MAX
UNIT
t
HL
0.05
0.1
0.15
ns/p-term
t
LH
0.02
0.05
0.08
ns/p-term
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
MIN
TYP
MAX
UNIT
NOTES
t
PHL
t
PLH
X
X
I
I
4.5
5
5.5
6
6.5
7.5
ns
ns
With 0 p-terms load
t
PHL
t
PLH
Y
Y
I
I
2.5
4
3
4
3.5
4.5
ns
ns
With 0 p-terms load
Input Pins: 1 7, 9 14, 41 45, 48 52.
Bidirectional Pins: 15 18, 37 40.
Maximum internal fan-out: 16 p-terms on X or Y.
NAND Output Buffer with 3-State Control
(TOU501)
TriCtrl
In
Out
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
MIN
TYP
MAX
UNIT
t
PHL
t
PLH
Out
Out
In
In
8.5
8.5
14.0
14.0
17.5
16
ns
ns
t
OE
2
t
OD
2
Out
Out
Tri-Ctrl
Tri-Ctrl
8.5
8.5
15
12.5
18.5
17.0
ns
ns
Output Pins: 24 27.
Internal Foldback NAND
(FBNAND)
Output
Input
LIMITS
SYMBOL
MIN
TYP
MAX
UNIT
t
PHL
0.05
0.1
0.15
ns/p-term
t
PLH
0.0
0.05
0.1
ns/p-term
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
MIN
TYP
MAX
UNIT
NOTES
t
PHL
t
PLH
Out
Any
4.0
5.5
4.5
6.5
6.8
8
ns
ns
With 0 p-terms load
Maximum internal loading of 16 terms.
Notes are on following page.
Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501
I
Programmable macro logic
PML
TM
October 22, 1993
10
MACRO CELL SPECIFICATIONS
1
(Continued)
(SNAP Resource Summary Designations in Parantheses)
Commercial:T
amb
= 0
C to +75
C, 4.75V
V
CC
5.25V, C
L
= 30pF, R
2
= 1000
, R
1
= 470
Industrial:
T
amb
= 40
C to +85
C, 4.5V
V
CC
5.5V, C
L
= 30pF, R
2
= 1000
, R
1
= 470
AND Output Buffer with 3-State Control
(NOU501)
TriCtrl
In
Out
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
MIN
TYP
MAX
UNIT
t
PHL
t
PLH
Output
Output
In
In
8.0
8.0
11
11
13
13
ns
ns
t
OE
2
t
OD
2
Out
Out
Tri-Ctrl
Tri-Ctrl
8.5
8.5
15
12.5
18.5
17.0
ns
ns
Bidirectional and Output Pins: 19, 21, 22, 23, 15 18.
NAND Output Buffer
(OUT501)
In
Out
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
MIN
TYP
MAX
UNIT
t
PHL
t
PLH
Out
Out
In
In
8.5
8.5
14
14
17.5
16.0
ns
ns
Bidirectional Pins: 37 40.
ExOR Output Buffer
(EXO501)
Out
A
B
TriCtrl
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
MIN
TYP
MAX
UNIT
t
PHL
t
PLH
Out
Out
A or B
A or B
8.5
8.5
14
14
17.5
16.0
ns
ns
t
OE
2
t
OD
2
Out
Out
Tri-Ctrl
Tri-Ctrl
8.5
8.5
15
12.5
18.5
17.0
ns
ns
Ex-OR Output Pins: 28 33.
NOTES:
1. Limits are guaranteed with internal feedback buffers simultaneously switching cumulative maximum of eight outputs.
2. For 3-State output; output enable times are tested with C
L
= 30pF to the 1.5V level, and S
1
is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C
L
= 5pF. High-to-High impedance tests are made to an output
voltage of V
T
= (V
OH
0.5V) with S
1
open, and Low-to-High impedance tests are made to the V
T
= (V
OL
+ 0.5V) level with S
1
closed.
Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501
I
Programmable macro logic
PML
TM
October 22, 1993
11
PLHS501 GATE AND SPEED ESTIMATE TABLE
FUNCTION
INTERNAL NAND
EQUVALENT
TYPICAL t
PD
f
MAX
COMMENTS
Gates
NANDs
1
6.5ns
For 1 to 32 input variables
ANDs
1
6.5ns
For 1 to 32 input variables
NORs
1
6.5ns
For 1 to 32 input variables
ORs
1
6.5ns
For 1 to 32 input variables
Decoders
3-to-8
8
11ns
Inverted inputs available
4-to-16
16
11ns
Inverted inputs available
5-to-32
32
11ns
Inverted inputs available (24 chip outputs only)
Encoders
8-to-3
15
11ns
Inverted inputs, 2 logic levels
16-to-4
32
11ns
Inverted inputs, 2 logic levels
32-to-5
41
11ns
Inverted inputs, 2 logic levels, factored solution.
Multiplexers
4-to-1
5
11ns
Inverted inputs available
8-to-1
9
11ns
16-to-1
17
11ns
27-to-1
28
11ns
Can address only 27 external inputs - more if internal
Flip-Flops
D-type Flip-Flop
6
30MHz
With asynchronous S-R
T-type Flip-Flop
6
30MHz
With asynchronous S-R
J-K-type Flip-Flop
10
30MHz
With asynchronous S-R
Adders
8-bit
45
15.5ns
Full carry-lookahead (four levels of logic)
Barrel Shifters
8-bit
72
11ns
2 levels of logic
Latches
D-latch
3
2 levels of logic with one shared gate
Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501
I
Programmable macro logic
PML
TM
October 22, 1993
12
APPLICATIONS
MASTER
SLAVE
MODULE
SPECIFIC
MODULE
SPECIFIC
BUS
CONTROL
PLHS501
CLOCK
ADDRESS, DATA,
CONTROL AND PARITY
ARBITRATION
ARBITRATION
CLOCK
ORIGINATION
N U B U S
SLOT ID
SLOT ID
Simplified N
U
B
US
TM
Diagram (10MHz Operating Frequency)
ADL
CDSETUP
M/IO
S1
S0
A2
A1
A0
CMD
D07
|
D00
CHRESET
7-BIT
LATCH
8-BIT
LATCH
POS
BYTE
2
CARD
I.D.
POS
BYTE
1
CARD
I.D.
POS
BYTE
0
OCTAL
3 to 1
MULTIPLEXER
3-STATE
DRIVER
TRANSCEIVER
CONTROL
BUFEN
DIR
POS
BYTE 2
DATA OUTPUT
8
8
8
8
8
8
7
Block Diagram of Basic POS Implementation in PLHS501
NuBus is a trademark of Texas Instruments, Inc.
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