1999 Nov 05

Philips Semiconductors

Product specification

QPSK transmitter

TDA8050A

FEATURES

Programmable gain

PLL controlled carrier frequency

3-wire transmission bus

5 V supply voltage.

APPLICATIONS

QPSK modulation.

GENERAL DESCRIPTION

The Quadrature Phase Shift Keying (QPSK) transmitter IC
is a monolithic bipolar IC dedicated to quadrature
modulation of the I and Q signals. It includes:

Two double balanced mixers

A balanced voltage controlled oscillator (VCO) with
0 to 90 degrees signal generation for modulation

A phase locked loop (PLL) for IF frequency control

A conversion mixer

A PLL for RF frequency control

A gain controlled output amplifier

A 3-wire bus and an output buffer.

Two PLLs are incorporated, the first PLL includes:

A fixed main divider

A crystal oscillator and its programmable reference
divider

A phase/frequency detector, combined with a fixed
charge pump.

The second PLL includes:

A divide-by-four preamplifier

A 12-bit programmable divider

A crystal oscillator and its programmable reference
divider

A phase/frequency detector, combined with a
programmable charge pump which drives the tuning
amplifier, including 30 V output.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

supply voltage

4.75

5.00

5.25

output centre frequency

MHz

o(max)

maximum output level

dBmV

xtal

crystal frequency

MHz

ref(MOD)

reference frequency for modulator synthesizer

250

kHz

step

frequency step size for converter synthesizer

100

500

kHz

amb

ambient temperature

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA8050A

SO32

plastic small outline package; 32 leads; body width 7.5 mm

SOT287-1

1999

Nov

Philips Semiconductors

Product specification

QPSK tr

ansmitter

TD
A8050A

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BLOCK DIA

GRAM

FCE433

1/2

90 0

TDA8050A

MODULATOR

CONVERTER

RF_OUT

OUTEN

BUF_OUT

BUF_OUTC

AVCC1

AGND2

AGND1

SW_CAP

AVCC2

CLK

I_IN

I_INC

Q_IN

Q_INC

DATA

RF_OUTC

RF_IN

IF_FILT

RF_INC

IF_FILTC

FIXED

MAIN DIVIDER

DAC

3-WIRE BUS TRANCEIVER

DIGITAL

PHASE

COMPARATOR

DIGITAL

PHASE

COMPARATOR

CHARGE

PUMP

PROGRAM-

MABLE

CHARGE

PUMP

PROGRAMMABLE

REF DIVIDER

PROGRAMMABLE

MAIN DIVIDER

PROGRAMMABLE

REF DIVIDER

CP_MOD

TKAMOD

TKBMOD

TKACONV

OSC_IN

TKBCONV

TUNECONV

CP_CONV

LOCK

DVCC

DGND

Fig.1 Block diagram.

1999 Nov 05

Philips Semiconductors

Product specification

QPSK transmitter

TDA8050A

PINNING

SYMBOL

PIN

DESCRIPTION

OUTEN

output enable

BUF_OUT

output amplifier balanced output

BUF_OUTC

output amplifier balanced output

AGND2

converter analog ground 2

I_IN

I balanced input

I_INC

I balanced input

Q_IN

Q balanced input

Q_INC

Q balanced input

AGND1

modulator analog ground 1

TKA_MOD

modulator VCO tank circuit input 2

TKB_MOD

modulator VCO tank circuit input 1

CP_MOD

modulator charge pump output for PLL loop filter

CCD

digital supply voltage

CLK

3-wire bus serial control clock

DATA

3-wire bus serial control data

3-wire bus serial control enable

OSC_IN

crystal oscillator input

DGND

digital ground

CP_CONV

converter charge pump output for PLL loop filter

TUNE_CONV

tuning voltage output for converter VCO

TKB_CONV

converter VCO tank circuit input 1

TKA_CONV

converter VCO tank circuit input 2

LOCK

lock detect signal

IF_FILT

IF balanced output to filter

IF_FILTC

IF balanced output to filter

CCA1

modulator analog supply voltage

RF_OUTC

RF balanced output to filter

RF_OUT

RF balanced output to filter

CCA2

converter analog supply voltage

RF_IN

RF balanced input to programmable amplifier

RF_INC

RF balanced input to programmable amplifier

SW_CAP

switch capacitor

1999 Nov 05

Philips Semiconductors

Product specification

QPSK transmitter

TDA8050A

FUNCTIONAL DESCRIPTION

The I and Q signals are balanced analog signals of
400 mV (p-p). These are mixed by two double balanced
mixers with the output signal generated by a first local
oscillator, to provide the modulated signal.

The modulated signal is then filtered by an IF filter. This
filtered signal, together a signal generated by a second
local oscillator, is converted by a balanced mixer to
produce the QPSK signal.

The QPSK signal is amplified by a gain controlled output
amplifier to a level suitable for transmission. The gain of
the amplifier is bus controlled and this amplifier can be
disabled when not transmitting, to provide signal
attenuation.

The amplified signal is applied to an on-chip amplifier with
two balanced outputs (open collector) connected to two
off-chip resistors (values 150

), in turn connected to 9 V.

The balanced outputs drive a 2 : 1 transformer (Siemens
V944) loaded with 75

, which gives an output level of

55 dBmV. The output frequency range of the transmitter is
5 to 65 MHz.

The frequency of the first local oscillator operates at twice
the frequency (i.e. 280 MHz), fixed by a PLL implemented
in the circuit.

The frequency of the second local oscillator operates in the
145 to 205 MHz bandwidth and can be programmed
through the PLL implemented in the circuit.

The VCOs of both the first and second local oscillators
need an external LC tank circuit with two varicap diodes.

The data sent to the PLL is loaded in bursts framed by
signal EN. Programming rising clock edges and their
appropriate data bits are ignored until EN goes active
(LOW). The internal latches are updated with the latest
programming data when EN returns to inactive (HIGH).
Only the last 14 bits are stored in the programming
register.

No check is made on the number of clock pulses received
during the time that programming is enabled. If EN goes
high while CLK is still LOW, a wrong active clock edge will
be generated, causing a shift of the data bits. At power up,
EN should be HIGH. The lock detector output LOCK is
HIGH when both PLLs are in lock.

The main divider ratio and the reference divider ratios are
provided via the serial bus. A control register controls the
Digital-to-Analog-Converter (DAC), the output amplifier
and the charge pump currents (see Tables 1, 2 and 3).

TDA8050A

FCE434

OUTEN

BUF_OUT

BUF_OUTC

AGND2

I_IN

I_INC

Q_IN

Q_INC

AGND1

TKAMOD

TKBMOD

CP_MOD

DVCC

CLK

SW_CAP

RF_INC

RF_IN

AVCC2

RF_OUTC

AVCC1

RF_OUT

IF_FILTC

IF_FILT

LOCK

TKACONV

TKBCONV

TUNECONV

CP_CONV

DATA

DGND

OSC_IN

Fig.2 Pin configuration.

1999 Nov 05

Philips Semiconductors

Product specification

QPSK transmitter

TDA8050A

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).

HANDLING

Human Body Model (HBM): The IC pins withstand 2 KV, except pins 27 and 28 (1750 V).
Machine Model (MM): The IC pins withstand 100 V.

THERMAL CHARACTERISTICS

CHARACTERISTICS
Measured in application circuit with the following conditions; V

= 5 V, T

amb

= 25

C; all AC units are RMS values,

unless otherwise specified.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage

0.3

+6.0

short-circuit time (every pin to V

or GND)

MAX

voltage on all pins except BUF_OUT, BUF_OUTC and TUNE_CONV

0.3

o(tune)

output tuning voltage

0.3

+30

O(buf)

output buffer voltage on pins BUF_OUT and BUF_OUTC

tot

maximum power dissipation

940

amb

ambient temperature

stg

storage temperature

+150

j(max)

maximum junction temperature

150

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient in free air

K/W

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

CCA1

modulator analog supply
voltage

4.75

5.25

CCA1

modulator analog supply
current

CCA2

converter analog supply voltage

4.75

5.25

CCA2

converter analog supply current

CC(buf)

buffer output supply current

CCD

digital supply voltage

4.75

5.25

CCD

digital supply current

20.5

23.5

26.5

CC(tune)

tuning supply voltage

1999 Nov 05

Philips Semiconductors

Product specification

QPSK transmitter

TDA8050A

Quadrature modulator

I and Q inputs

i(DC)

input DC level

0.5

i(p-p)

signal input level (balanced)
(peak-to-peak)

indicative

400

500

i(max)

I and Q maximum input
frequency

indicative

MHz

i(dif)

differential input impedance

4.4

(1 dB)

1 dB bandwidth amplifier

indicative

MHz

Modulator

output centre frequency

140

MHz

amplitude imbalance

see Fig.3

phase imbalance

deg

(sup)

LO suppression

see Fig.3

dBc

o(dif)

differential output impedance

1.8

Modulator VCO

OSC(mod)

oscillation frequency

280

MHz

Converter output

output level

f = 5 MHz; V

= 100 mV

dif

I and Q inputs

37.5

42.5

dBmV

output flatness

f = 5 to 65 MHz; V

= 100 mV

dif

at I and Q inputs

output centre frequency

MHz

o(dif)

differential output impedance

150

3rd order interception point at
I input

see Fig.4

dBmV

2nd order harmonic of
5 to 65 MHz signal

f = 10 to 130 MHz;
V

= 100 mV

dif

at I and Q inputs

dBc

3rd order harmonic of
5 to 65 MHz signal

f = 15 to 195 MHz;
V

= 100 mV

dif

at I and Q inputs

dBc

mixer spurious outputs of
5 to 65 MHz signal

f = 5 to 65 MHz; V

= 100 mV

dif

at I and Q inputs

dBc

Converter VCO

osc(min)

minimum oscillation frequency

145

MHz

osc(max)

maximum oscillation frequency

205

MHz

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999 Nov 05

Philips Semiconductors

Product specification

QPSK transmitter

TDA8050A

Programmable gain and output buffer; note 1

i(dif)

differential input impedance

5.6

output level step size

buf

output level adjust range

= 30 dBmV sine wave

65 MHz at pins
RF_IN and RF_INC;
DAC = 0 to 31

operational output level

dBmV

output flatness

f = 5 to 65 MHz; V

= 30 dBmV

sine wave; DAC = 28

IL(ENL)

output controlled enable low

output buffer on

0.8

IH(ENH)

output controlled enable high

output buffer off

2.4

ISO

disable isolation

= 100 mV

dif

; DAC = 28;

f = 65 MHz; OE = 0,5 V

dBc

V(max)

maximum gain

see Fig.5

18.5

o(1dB)

1 dB compression point

see Fig.5

dBmV

2nd order harmonic of
5 to 65 MHz signal

f = 10 to 65 MHz; see Fig.6

dBc

f = 65 to 120 MHz; see Fig.6

dBc

3rd order harmonic
of 5 to 65 MHz signal

f = 15 to 65 MHz; see Fig.6

dBc

f = 65 to 120 MHz; see Fig.6

dBc

Overall; note 1

osc

phase noise

at 10 kHz; note 2

dBc/Hz

at 100 kHz; note 2

dBc/Hz

2nd order harmonic of
5 to 65 MHz signal

f = 10 to 130 MHz;
V

= 100 mV

dif

at I and Q

inputs; V

out

= 55 dBmV

dBc

3rd order harmonic
of 5 to 65 MHz signal

f = 15 to 195 MHz;
V

= 100 mV

dif

at I and Q

inputs; V

out

= 55 dBmV

dBc

spurious signals of 5 to 65 MHz
signal

f = 5 to 65 MHz; V

= 100 mV

dif

at I and Q inputs;
V

out

= 55 dBmV

dBc

3rd order interception point at
I input

dBmV

ISO

tot

total isolation at I/Q midrange

see Fig.7

dBc

C/N

carrier to noise ratio at final
output at 2 MHz from carrier

= 100 mV

dif

;

out

= 35 to 55 dBmV;

f = 65 MHz

113

dBc/Hz

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999 Nov 05

Philips Semiconductors

Product specification

QPSK transmitter

TDA8050A

Notes

1. All specification points of the output section and the overall circuit are measured after the 2 : 1 transformer (Siemens

V944) loaded with 75

2. Overall phase noise:

a) Converter: I

(cp)

= 0.36 mA; f

ref

= 25 kHz.

b) I and Q = 100 mV

dif

c) DAC = 28.

d) f = 65 MHz.

3. The crystal oscillator uses a 4, 2 or 1 MHz crystal in series with a capacitor. The crystal is serial resonant with a load

capacitance of 18 to 20 pF. The connection to V

is preferred but it might also be to GND.

Crystal oscillator

xtal

crystal frequency

note 3

MHz

input impedance

xtal

= 4 MHz

600

1200

i(DC)

DC input level

2.9

Modulator synthesizer

ref(mod)

reference frequency

250

kHz

RDR1

programmable reference divider
ratio

ND1

fix main divider ratio

1120

(cp)

charge-pump current

fixed

0.30

Converter synthesizer

step

step size

100

500

kHz

RD2

fix reference divider ratio

RDR2

programmable reference divider
ratio

see Tables 4 and 5

160

ND2

fix main divider ratio

NDR2

programmable main divider
ratio

see Tables 4 and 5

290

1800

3-wire bus

input LOW level

0.8

input HIGH level

2.4

Lock detect pin

O(lock)

output voltage (LOCK)

O(unlock)

output voltage (UNLOCK)

0.02

Serial control clock

clk

clock frequency

330

kHz

input data to CLK set-up time

see Fig.8

h(CLK)

input data to CLK hold time

see Fig.8

d(strt)

delay to rising clock edge

see Fig.8

d(stp)

delay from last clock edge

see Fig.8

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999 Nov 05

Philips Semiconductors

Product specification

QPSK transmitter

TDA8050A

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 230

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

1999 Nov 05

Philips Semiconductors

Product specification

QPSK transmitter

TDA8050A

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS

not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO

not recommended

(5)

suitable

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999

Philips Semiconductors a worldwide company

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
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Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777

Printed in The Netherlands

545004/25/01/pp

Date of release:

1999 Nov 05

Document order number:

9397 750 06123

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8050A

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8050A