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Электронный компонент: TDA9962

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DATA SHEET
Objective specification
File under Integrated Circuits, IC02
2000 May 01
INTEGRATED CIRCUITS
TDA9962
12-bit, 3.0 V, 20 Msps
analog-to-digital interface for CCD
cameras
2000 May 01
2
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
FEATURES
Correlated Double Sampling (CDS), Programmable
Gain Amplifier (PGA), 12-bit Analog-to-Digital Converter
(ADC) and reference regulator included
Fully programmable via a 3-wire serial interface
Sampling frequency up to 20 MHz
PGA gain range of 24 dB (in steps of 0.1 dB)
Low power consumption of only 140 mW at 2.7 V
Power consumption in standby mode of 4.5 mW (typ.)
3.0 V operation and 2.2 to 3.6 V operation for the digital
outputs
All digital inputs accept 5 V signals
Active control pulses polarity selectable via serial
interface
8-bit DAC included for analog settings
TTL compatible inputs, CMOS compatible outputs.
APPLICATIONS
Low-power, low-voltage CCD camera systems.
GENERAL DESCRIPTION
The TDA9962 is a 12-bit analog-to-digital interface for
CCD cameras. The device includes a correlated double
sampling circuit, PGA, clamp loops and a low-power 12-bit
ADC together with its reference voltage regulator.
The PGA gain and the ADC input clamp level are
controlled via the serial interface.
An additional DAC is provided for additional system
controls; its output voltage range is 1.0 V (p-p) which is
available at pin OFDOUT.
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TDA9962HL
LQFP48
plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
SOT313-2
2000 May 01
3
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CCA
analog supply voltage
2.7
3.0
3.6
V
V
CCD
digital supply voltage
2.7
3.0
3.6
V
V
CCO
digital outputs supply voltage
2.2
2.5
3.6
V
I
CCA
analog supply current
all clamps active
-
49
-
mA
I
CCD
digital supply current
-
2
-
mA
I
CCO
digital outputs supply current
f
pix
= 20 MHz; C
L
= 20 pF; input
ramp response time is 800
s
-
1
-
mA
ADC
res
ADC resolution
-
12
-
bits
V
i(CDS)(p-p)
maximum CDS input voltage
(peak-to-peak value)
V
CC
= 2.85 V
650
-
-
mV
V
CC
3.0 V
800
-
-
mV
f
pix(max)
maximum pixel rate
20
-
-
MHz
f
pix(min)
minimum pixel rate
tbf
-
-
MHz
DR
PGA
PGA dynamic range
-
24
-
dB
N
tot(rms)
total noise from CDS input to
ADC output
PGA gain = 0 dB; see Fig.8
-
1.2
-
LSB
E
in(rms)
equivalent input noise
(RMS value)
gain = 24 dB
-
95
-
V
P
tot
total power consumption
V
CCA
= V
CCD
= V
CCO
= 3 V
-
155
-
mW
V
CCA
= V
CCD
= V
CCO
= 2.7 V
-
140
-
mW
2000
May
01
4
Philips Semiconductors
Objectiv
e specification
12-bit, 3.0 V
,
20 Msps analog-to-digital
interf
ace f
or CCD camer
as
TD
A9962
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BLOCK DIA
GRAM
handbook, full pagewidth
FCE504
12-bit ADC
REGULATOR
CDS CLOCK GENERATOR
BLANKING
OUTPUT
BUFFER
37
38
27
26
25
28
29
30
31
32
33
34
35
36
39
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
OGND2
D1
D0
23
24
VCCO1
10
DCLPC
21
VCCD1
VCCO2
22
DGND1
3
AGND2
7
VCCA2
9
CPCDS2
8
CPCDS1
4
IN
5
AGND3
11
OFDOUT
14
VCCA3
OE
43
BLK
47
CLK
40
AGND6
2
AGND1
1
VCCA1
41
VCCA4
48
CLPDM
44
CLPOB
45
SHP
SHIFT
CORRELATED
DOUBLE
SAMPLING
7-BIT
REGISTER
8-BIT
REGISTER
8-BIT
REGISTER
16
15
OPGA
OPGAC
12
6
13
TEST
AGND4
AGND5
46
SHD
SERIAL
INTERFACE
17
18
19
SEN
SCLK SDATA
20
VSYNC
42
STDBY
PGA
CLAMP
Vref
OFD DAC
DATA
FLIP-
FLOP
CLAMP
TDA9962
OGND1
BLACK
LEVEL
SHIFT
Fig.1 Block diagram.
2000 May 01
5
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
PINNING
SYMBOL
PIN
DESCRIPTION
V
CCA1
1
analog supply voltage 1
AGND1
2
analog ground 1
AGND2
3
analog ground 2
IN
4
input signal from CCD
AGND3
5
analog ground 3
AGND4
6
analog ground 4
V
CCA2
7
analog supply voltage 2
CPCDS1
8
clamp storage capacitor pin 1
CPCDS2
9
clamp storage capacitor pin 2
DCLPC
10
regulator decoupling pin
OFDOUT
11
analog output of the additional 8-bit control DAC
TEST
12
test mode input pin (should be connected to AGND5)
AGND5
13
analog ground 5
V
CCA3
14
analog supply voltage 3
OPGA
15
PGA output (test pin)
OPGAC
16
PGA complementary output (test pin)
SDATA
17
serial data input for serial interface control
SCLK
18
serial clock input for serial interface
SEN
19
strobe pin for serial interface
VSYNC
20
vertical sync pulse input
V
CCD1
21
digital supply voltage 1
DGND1
22
digital ground 1
V
CCO1
23
digital outputs supply voltage 1
OGND1
24
digital output ground 1
D0
25
ADC digital output 0 (LSB)
D1
26
ADC digital output 1
D2
27
ADC digital output 2
D3
28
ADC digital output 3
D4
29
ADC digital output 4
D5
30
ADC digital output 5
D6
31
ADC digital output 6
D7
32
ADC digital output 7
D8
33
ADC digital output 8
D9
34
ADC digital output 9
D10
35
ADC digital output 10
D11
36
ADC digital output 11 (MSB)
OGND2
37
digital output ground 2
V
CCO2
38
digital outputs supply voltage 2
OE
39
output enable control input (LOW = outputs active; HIGH = outputs in high-impedance)
AGND6
40
analog ground 6
2000 May 01
6
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
V
CCA4
41
analog supply voltage 4
STDBY
42
standby mode control input (LOW = TDA9962 active; HIGH = TDA9962 standby)
BLK
43
blanking control input
CLPOB
44
clamp pulse input at optical black
SHP
45
preset sample-and-hold pulse input
SHD
46
data sample-and-hold pulse input
CLK
47
data clock input
CLPDM
48
clamp pulse input at dummy pixel
SYMBOL
PIN
DESCRIPTION
handbook, full pagewidth
1
2
3
4
5
6
7
8
9
10
11
36
35
34
33
32
31
30
29
28
27
26
13
14
15
16
17
18
19
20
21
22
23
48
47
46
45
44
43
42
41
40
39
38
12
24
37
25
TDA9962HL
FCE505
D9
D10
D11
D8
D7
D6
D4
D3
D2
D1
D0
VCCA1
VCCA2
AGND1
AGND2
IN
AGND3
AGND4
CPCDS1
CPCDS2
OFD
TEST
D5
CLK
SHD
SHP
CLPOB
BLK
STDBY
A
GND6
OGND2
OE
CLPDM
V
CCA4
V
CCO2
DCPLC
OPGA
C
OPGA
A
GND5
V
CCA3
V
CCD1
V
CCO1
DGND1
SCLK
SEN
OGND1
VSYNC
S
D
ATA
Fig.2 Pin configuration.
2000 May 01
7
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Note
1. The supply voltages V
CCA
, V
CCD
and V
CCO
may have any value between
-
0.3 and +7.0 V provided that the supply
voltage difference
V
CC
remains as indicated.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CCA
analog supply voltage
note 1
-
0.3
+7.0
V
V
CCD
digital supply voltage
note 1
-
0.3
+7.0
V
V
CCO
digital outputs supply voltage
note 1
-
0.3
+7.0
V
V
CC
supply voltage difference
between V
CCA
and V
CCD
-
0.5
+0.5
V
between V
CCA
and V
CCO
-
0.5
+1.2
V
between V
CCD
and V
CCO
-
0.5
+1.2
V
V
i
input voltage
referenced to AGND
-
0.3
+7.0
V
I
o
data output current
-
10
mA
T
stg
storage temperature
-
55
+150
C
T
amb
ambient temperature
-
20
+75
C
T
j
junction temperature
-
+150
C
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
R
th(j-a)
thermal resistance from junction to ambient
in free air
76
K/W
2000 May 01
8
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
CHARACTERISTICS
V
CCA
= V
CCD
= 3.0 V; V
CCO
= 2.5 V; f
pix
= 20 MHz; T
amb
= 25
C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
CCA
analog supply voltage
2.7
3.0
3.6
V
V
CCD
digital supply voltage
2.7
3.0
3.6
V
V
CCO
digital outputs supply
voltage
2.2
2.5
3.6
V
I
CCA
analog supply current
all clamps active
-
49
-
mA
I
CCD
digital supply current
-
2
-
mA
I
CCO
digital outputs supply
current
C
L
= 20 pF on all data
outputs; input ramp
response time is 800
s
-
1
-
mA
Digital inputs
P
INS
SHP, SHD
AND
CLK (
REFERENCED TO
DGND)
V
IL
LOW-level input voltage
0
-
0.6
V
V
IH
HIGH-level input voltage
2.2
-
5.5
V
I
i
input current
0
V
i
5.5 V
-
3
-
+3
A
Z
i
input impedance
f
CLK
= 20 MHz
-
50
-
k
C
i
input capacitance
f
CLK
= 20 MHz
-
-
2
pF
P
INS
CLPDM, CLPOB, SEN, SCLK, SDATA, STBY, OE, BLK
AND
VSYNC
V
IL
LOW-level input voltage
0
-
0.6
V
V
IH
HIGH-level input voltage
2.2
-
5.5
V
I
i
input current
0
V
i
5.5 V
-
2
-
+2
A
Clamps
G
LOBAL CHARACTERISTICS OF THE CLAMP LOOPS
t
W(clamp)
clamp active pulse width
in number of pixels
PGA code = 255 for
maximum 4 LSB error
12
-
-
pixels
I
NPUT CLAMP
(
DRIVEN BY
CLPDM)
g
m(CDS)
CDS input clamp
transconductance
-
20
-
mS
Correlated Double Sampling (CDS)
V
i(CDS)(p-p)
maximum peak-to-peak
CDS input amplitude
(video signal)
V
CC
= 2.85 V
650
-
-
mV
V
CC
3.0 V
800
-
-
mV
V
reset(max)
maximum CDS input reset
pulse amplitude
500
-
-
mV
I
i(IN)
input current into pin IN
at floating gate level
tbf
-
tbf
A
C
i
input capacitance
-
2
-
pF
t
CDS(min)
CDS control pulses
minimum active time
V
i(CDS)(p-p)
= 800 mV
black-to-white transition in
1 pixel with 99% V
i
recovery
11
15
-
ns
2000 May 01
9
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
t
h(IN;SHP)
CDS input hold time
(pin IN) compared to
control pulse SHP
V
CCA
= V
CCD
= 3.0 V;
T
amb
= 25
C;
see Figs 3 and 4
-
1
2
ns
t
h(IN;SHD)
CDS input hold time
(pin IN) compared to
control pulse SHD
V
CCA
= V
CCD
= 3.0 V;
T
amb
= 25
C;
see Figs 3 and 4
-
1
2
ns
Amplifier
DR
PGA
PGA dynamic range
-
24
-
dB
G
PGA
PGA gain step
0.08
0.10
0.12
dB
Analog-to-Digital Converter (ADC)
DNL
differential non linearity
f
pix
= 20 MHz; ramp input
-
0.5
0.9
LSB
Total chain characteristics (CDS + PGA + ADC)
f
pix(max)
maximum pixel frequency
20
-
-
MHz
f
pix(min)
minimum pixel frequency
tbf
-
-
MHz
t
CLKH
CLK pulse width HIGH
15
-
-
ns
t
CLKL
CLK pulse width LOW
15
-
-
ns
t
d(SHD;CLK)
time delay between
SHD and CLK
see Figs 3 and 4
10
-
-
ns
t
su(BLK;SHD)
set-up time of BLK
compared to SHD
see Figs 3 and 4
5
-
-
ns
V
i(IN)(FS)
video input dynamic signal
for ADC full-scale output
PGA code = 00
800
-
-
mV
PGA code = 255
50
-
-
mV
N
tot(rms)
total noise from CDS input
to ADC output
(RMS value)
see Fig.8
PGA gain = 0 dB
-
1.2
-
LSB
PGA gain = 9 dB
-
2.0
-
LSB
E
in(rms)
equivalent input noise
voltage (RMS value)
PGA gain = 24 dB
-
95
-
V
PGA gain = 9 dB
-
135
-
V
O
CCD(max)
maximum offset between
CCD floating level and
CCD dark pixel level
-
100
-
+100
mV
Digital-to-analog converter (OFDOUT DAC)
V
OFDOUT(p-p)
additional 8-bit control
DAC (OFD) output voltage
(peak-to-peak value)
R
i
= 1 M
-
1.0
-
V
V
OFDOUT(0)
DC output voltage for
code 0
-
AGND
-
V
V
OFDOUT(255)
DC output voltage for
code 255
-
AGND + 1.0
-
V
TC
DAC
DAC output range
temperature coefficient
-
250
-
ppm/
C
Z
OFDOUT
DAC output impedance
-
2000
-
I
OFDOUT
OFD output current drive
static
-
-
100
A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
2000 May 01
10
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
Digital outputs (f
pix
= 20 MHz; C
L
= 10 pF); see Figs 3 and 4
V
OH
HIGH-level output voltage
I
OH
=
-
1 mA
V
CCO
-
0.5
-
V
CCO
V
V
OL
LOW-level output voltage
I
OL
= 1 mA
0
-
0.5
V
I
OZ
output current in 3-state
mode
0.5 V < V
o
< V
CCO
-
20
-
+20
A
t
h(o)
output hold time
5
-
-
ns
t
d(o)
output delay time
C
L
= 10 pF; V
CCO
= 3.0 V
-
16
tbf
ns
C
L
= 10 pF; V
CCO
= 2.7 V
-
18
tbf
ns
C
L
= 10 pF; V
CCO
= 2.2 V
-
tbf
tbf
ns
C
L
output load capacitance
-
-
20
pF
Serial interface
f
SCLK(max)
maximum frequency of
serial clock interface
10
-
-
MHz
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
2000
May
01
11
Philips Semiconductors
Objectiv
e specification
12-bit, 3.0 V
,
20 Msps analog-to-digital
interf
ace f
or CCD camer
as
TD
A9962
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handbook, full pagewidth
N
0.6 V
2.2 V
N
+
2
N
+
1
N
+
3
N
+
4
N
-
2
N
-
1
N
-
3
N
-
4
N
+
5
tCDS(min)
tCLKH
th(IN;SHP)
0.6 V
0.6 V
0.6 V
0.6 V
th(IN;SHD)
2.2 V
tCDS(min)
td(SHD;CLK)
tsu(BLK;SHD)
2.2 V
2.2 V
2.2 V
FCE506
IN
SHP
SHD
CLK
DATA
BLK
th(o)
td(o)
50%
2.2 V
N
ADC CLAMP
CODE
Fig.3 Pixel frequency timing diagram; all polarities active HIGH.
2000
May
01
12
Philips Semiconductors
Objectiv
e specification
12-bit, 3.0 V
,
20 Msps analog-to-digital
interf
ace f
or CCD camer
as
TD
A9962
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handbook, full pagewidth
N
2.2 V
2.2 V
tCDS(min)
tCLKL
th(IN;SHP)
0.6 V
0.6 V
0.6 V
0.6 V
th(IN;SHD)
0.6 V
0.6 V
tCDS(min)
td(SHD;CLK)
tsu(BLK;SHD)
2.2 V
2.2 V
2.2 V
FCE507
IN
SHP
SHD
CLK
DATA
BLK
th(o)
td(o)
N
50%
ADC CLAMP
CODE
N
+
2
N
+
1
N
+
3
N
+
4
N
-
2
N
-
1
N
-
3
N
-
4
N
+
5
Fig.4 Pixel frequency timing diagram; all polarities active LOW.
2000 May 01
13
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
handbook, full pagewidth
FCE508
0
OFDOUT DAC
voltage
output
(V)
1.0
0
255
OFDOUT control DAC input code
Fig.5 DAC voltage output as a function of DAC input code.
handbook, full pagewidth
FCE509
BLK
(active HIGH)
CLPOB
(active HIGH)
CLPDM
(active HIGH)
AGCOUT
VIDEO
OPTICAL BLACK
CLPOB
WINDOW
HORIZONTAL FLYBACK
DUMMY
VIDEO
BLK window
CLPDM
WINDOW
Fig.6 Line frequency timing diagram.
2000 May 01
14
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
handbook, halfpage
0
64
192
PGA input code
128
TOTAL
gain
(dB)
255
25.9
6
0
1.9
12
24
30
18
FCE510
Fig.7 Total gain from CDS input to ADC input as a function of PGA input code.
handbook, halfpage
64
0
192
128
PGA code
256
FCE511
Ntot(rms)
(LSB)
5
4
7
8
6
3
2
0
1
Fig.8 Typical total noise performance as a function of PGA gain.
Noise measurement at ADC outputs: Coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. Front-end works
at 20 Mpixels with line of 1024 pixels whose first 40 are used to run CLPOB and the last 40 for CLPDM. Data at the ADC outputs are measured during
the other pixels. As a result of this, the standard deviation of the codes statistic is computed, resulting in the noise. No quantization noise is taken into
account.
2000 May 01
15
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
handbook, full pagewidth
OFDOUT DAC
LATCHES
PGA GAIN
LATCHES
ADC CLAMP
LATCHES
CONTROL PULSE
POLARITY
LATCHES
LATCH
SELECTION
SD0
LSB
MSB
SDATA
SCLK
SEN
8-bit DAC
FCE512
PGA control
ADC clamp
control
control pulses
polarity settings
SD2
SD1
SD3
SD4
SD5
12
SD6
SHIFT REGISTER
SD7
SD8
SD9 SD10 SD11
8
10
5
9
A0
A1
A2
A3
VSYNC
FLIP-FLOP
FLIP-FLOP
FLIP-FLOP
SCLK
Fig.9 Serial interface block diagram.
handbook, full pagewidth
FCE513
SDATA
SCLK
SEN
SD11
A1
A2
A3
A0
SD9
SD10
SD7
SD6
SD5
SD4
SD3
MSB
LSB
SD2
SD1
SD0
thd3
tsu3
tsu1
thd4
tsu2
SD8
Fig.10 Loading sequence of control input data via the serial interface.
t
su1
= t
su2
= t
su3
= 10 ns (min.); t
hd3
= t
hd4
= 10 ns (min.).
2000 May 01
16
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
Table 1
Serial interface programming
Table 2
Polarity settings
Table 3
Standby control using pin STDBY
ADDRESS BITS
DATA BITS SD11 TO SD0
A3
A2
A1
A0
0
0
0
0
PGA gain control (SD7 to SD0)
0
0
0
1
DAC OFDOUT output control (SD7 to SD0)
0
0
1
0
ADC clamp reference control (SD6 to SD0); from code 0 to 127
0
0
1
1
control pulses (pins SHP, SHD, CLPDM, CLPOB, BLK and CLK) polarity settings; SD2,
SD6, SD7 and SD9 should be set to logic 1; for SD6 and SD7 see Tables 3, 4, 5 and 6
0
1
0
0
SD7 = 0 by default; SD7 = 1 PGA gain up to 36 dB but noise and clamp behaviour are
not guaranteed
1
1
1
1
initialization (SD8 = 1; SD11 to SD9 = 0 and SD7 to SD0 = 0)
other addresses
test modes
SYMBOL
PIN
SERIAL CONTROL BIT
ACTIVE EDGE OR LEVEL
SHP and SHD
45 and 46
SD4
1 = HIGH; 0 = LOW
CLK
47
SD5
1 = rising; 0 = falling
CLPDM
48
SD0
1 = HIGH; 0 = LOW
CLPOB
44
SD1
1 = HIGH; 0 = LOW
BLK
43
SD3
1 = HIGH; 0 = LOW
VSYNC
20
SD8
0 = rising; 1 = falling
BIT SD7 OF REGISTER
0011
STDBY
ADC DIGITAL OUTPUTS SD11 TO SD0
I
CCA
+ I
CCO
+ I
CCD
(typ.)
1
1
last logic state
1.5 mA
0
active
51 mA
0
1
active
51 mA
0
test logic state
1.5 mA
2000 May 01
17
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
Table 4
Output enable selection using output enable pin (OE)
Table 5
Standby control by serial interface (register address A3 = 0, A2 = 0, A1 = 1, A0 = 1);
pin STDBY connected to ground
Table 6
Output enable control by serial interface (register address A3 = 0, A2 = 0, A1 = 1, A0 = 1);
output enable pin (OE) connected to ground
BIT SD6 OF REGISTER 0011
OE
ADC DIGITAL OUTPUTS SD9 TO SD0
1
0
active, binary
1
high-impedance
0
0
high-impedance
1
active binary
SD7
ADC DIGITAL OUTPUTS SD9 TO SD0
I
CCA
+ I
CCO
+ I
CCD
(typ.)
0
last logic state
1.5 mA
1
active
72 mA
SD6
ADC DIGITAL OUTPUTS SD9 TO SD0
0
high-impedance
1
active binary
2000 May 01
18
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
APPLICATION INFORMATION
ndbook, full pagewidth
FCE514
1
2
3
4
5
6
7
8
9
10
11
36
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17 18
19
20
21 22 23
24
35
34
33
32
31
30
29
28
27
26
12
25
TDA9962
D11
D10
D9
D8
D6
D5
D4
D3
D2
VCCO
VCCA1
VCCA2
AGND1
AGND2
IN
AGND3
CPCDS1
OFD
TEST
D7
SHP
SHD
CLPOB
BLK
V
CCA4
AGND6
STDBY
CLPDM
OGND2
OE
V
CCO2
CLK
CPCDS2
DCPLC
AGND5
V
CCA3
V
CCD1
V
CCO1
SCLK
SEN
VSYNC
OPGA
OPGAC
SDATA
AGND4
DGND1
OGND1
serial
interface
VCCA
VCCA
CCD
(2)
VCCA
VCCO
100 nF
100 nF
100 nF
VCCD
100 nF
VCCA
100 nF
VCCD
100 nF
1
F
1
F
1
F
1
F
(1)
(2)
(2)
D0
D1
VCCD
Fig.11 Application diagram.
(1) Pins SEN and VSYNC should be interconnected when vertical sync signal is not available.
(2) Input signals IN, SHD and SHP must be adjusted to comply with timing signals t
h(IN;SHP)
and t
h(IN;SHD)
(see Chapter "Characteristics").
2000 May 01
19
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
Power and grounding recommendations
When designing a printed-circuit board for applications
such as PC cameras, surveillance cameras, camcorders
and digital still cameras, care should be taken to minimize
the noise.
For the front-end integrated circuit, the basic rules of
printed-circuit board design and implementation of analog
components (such as classical operational amplifiers)
must be respected, particularly with respect to power and
ground connections.
The following additional recommendation is given for the
CDS input pin(s) which is/are internally connected to the
programmable gain amplifier.
The connections between the CCD interface and the CDS
input should be as short as possible and a ground ring
protection around these connections can be beneficial.
Separate analog and digital supplies provide the best
solution. If it is not possible to do this on the board then the
analog supply pins must be decoupled effectively from the
digital supply pins. If the same power supply and ground
are used for all the pins then the decoupling capacitors
must be placed as close as possible to the IC package.
In a two-ground system, in order to minimize the noise
through package and die parasitics, the following
recommendation must be implemented.
All the analog and digital supply pins must be decoupled to
the analog ground plane. Only the ground pin associated
with the digital outputs must be connected to the digital
ground plane. All the other ground pins should be
connected to the analog ground plane. The analog and
digital ground planes must be connected together at one
point as close as possible to the ground pin associated
with the digital outputs.
The digital output pins and their associated lines should be
shielded by the digital ground plane which can then be
used as a return path for digital signals.
2000 May 01
20
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
PACKAGE OUTLINE
UNIT
A
max.
A
1
A
2
A
3
b
p
c
E
(1)
e
H
E
L
L
p
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
0.5
9.15
8.85
0.95
0.55
7
0
o
o
0.12
0.1
0.2
1.0
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT313-2
MS-026
136E05
99-12-27
00-01-19
D
(1)
(1)
(1)
7.1
6.9
H
D
9.15
8.85
E
Z
0.95
0.55
D
b
p
e
E
B
12
D
H
b
p
E
H
v
M
B
D
ZD
A
Z E
e
v
M
A
1
48
37
36
25
24
13
A
1
A
L
p
detail X
L
(A )
3
A
2
X
y
c
w
M
w
M
0
2.5
5 mm
scale
pin 1 index
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
2000 May 01
21
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
"Data Handbook IC26; Integrated Circuit Packages"
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250
C. The top-surface temperature of the
packages should preferable be kept below 230
C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
For packages with leads on two sides and a pitch (e):
larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
For packages with leads on four sides, the footprint must
be placed at a 45
angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250
C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300
C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320
C.
2000 May 01
22
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45
angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE
SOLDERING METHOD
WAVE
REFLOW
(1)
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not suitable
(2)
suitable
PLCC
(3)
, SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended
(3)(4)
suitable
SSOP, TSSOP, VSO
not recommended
(5)
suitable
2000 May 01
23
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras
TDA9962
DATA SHEET STATUS
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DATA SHEET STATUS
PRODUCT
STATUS
DEFINITIONS
(1)
Objective specification
Development
This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
DEFINITIONS
Short-form specification
The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition
Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications
These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Philips Electronics N.V.
SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
2000
69
Philips Semiconductors a worldwide company
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Printed in The Netherlands
753504/01/pp
24
Date of release:
2000 May 01
Document order number:
9397 750 06915