2004 Mar 22
2
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
CONTENTS
1
FEATURES
1.1
General
1.2
System features
1.3
Fail-safe features
1.4
CAN physical layer
1.5
LIN physical layer
2
GENERAL DESCRIPTION
3
ORDERING INFORMATION
4
BLOCK DIAGRAM
5
PINNING
6
FUNCTIONAL DESCRIPTION
6.1
Introduction
6.2
Fail-safe system controller
6.2.1
Fail-safe mode
6.2.2
Start-up mode
6.2.3
Restart mode
6.2.4
Normal mode
6.2.5
Standby mode
6.2.6
Sleep mode
6.2.7
Flash mode
6.3
On-chip oscillator
6.4
Watchdog
6.4.1
Watchdog start-up behaviour
6.4.2
Watchdog window behaviour
6.4.3
Watchdog time-out behaviour
6.4.4
Watchdog OFF behaviour
6.5
System reset
6.5.1
System reset pin RSTN
6.5.2
Enable output pin EN
6.6
Power supplies
6.6.1
Supported battery systems
6.6.2
Static and dynamic battery monitoring
6.6.3
Voltage regulators V1 and V2
6.6.4
Switched battery output (V3)
6.7
CAN transceiver
6.7.1
Mode control
6.7.2
Termination control
6.7.3
Bus, RXD and TXD failure detection
6.8
LIN transceiver
6.8.1
Mode control
6.8.2
Bus and TXDL failure detection
6.9
Inhibit output (pin INH)
6.10
Wake-up input (pin WAKE)
6.11
Interrupt output
6.12
Temperature protection
6.13
SPI interface
6.14
SPI register mapping
6.14.1
Register overview
6.14.2
Mode register
6.14.3
System status register
6.14.4
System diagnosis register
6.14.5
Interrupt enable register
6.14.6
Interrupt Enable Feedback register
6.14.7
Interrupt register
6.14.8
System configuration register
6.14.9
System Configuration Feedback register
6.14.10
Physical Layer Control register
6.14.11
Physical layer control feedback register
6.14.12
Special Mode register
6.14.13
General Purpose registers
6.14.14
General Purpose Feedback registers
6.15
Register configurations at reset
6.16
Test modes
6.16.1
Software development mode
6.16.2
Forced Normal mode
7
LIMITING VALUES
8
DC CHARACTERISTICS
9
AC CHARACTERISTICS
10
PACKAGE OUTLINE
11
SOLDERING
11.1
Introduction to soldering surface mount
packages
11.2
Reflow soldering
11.3
Wave soldering
11.4
Manual soldering
11.5
Suitability of surface mount IC packages for
wave and reflow soldering methods
12
DATA SHEET STATUS
13
DEFINITIONS
14
DISCLAIMERS
2004 Mar 22
3
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
1
FEATURES
1.1
General
Excellent EMC performance
8 kV ESD protection (human body model) for the
outside module pins
CAN/LIN-bus pins are short-circuit proof to the battery
(up to 60 V) and to ground
Battery and CAN/LIN-bus pins are protected against
transients that occur in an automotive environment
(ISO7637)
Software Development mode partly disabling of fail-safe
and watchdog functionality to ease software
development
Unique SPI readable device type identification
Small footprint HTSSOP32 package (body 6
11 mm)
with low thermal resistance.
1.2
System features
12 V, 24 V and 42 V system support with low sleep
current (typical 50
A)
Support of 2.5, 3.0, 3.3 and 5.0 V microcontrollers with
automatic adaption of interface levels to
microcontrollers
Flexible, independent external regulator extension via
14 V battery related pin INH (enables fail-safe scalable
supply system)
Smart operating and power management modes
In-field Flash Programming mode
Cyclic wake-up capability in Standby and Sleep mode
Remote wake-up capability via CAN and LIN buses
Local WAKE port with cyclic supply feature
42 V battery related local wake-up input
42 V battery related high-side switch output to drive
external loads such as relays and wake-up switches
Interrupt output with 12 maskable interrupt sources:
Interrupt service monitor
One interrupt per watchdog period to prevent
microcontroller overloading; ensures predictable
software behaviour
Extensive set of SPI-readable system diagnostics:
Detection and detailed error reporting on CAN and
LIN bus failures (e.g. shorts to GND/BAT, open bus
wires, etc.)
TxD dominant and RxD recessive clamping as well
as RxD to TxD short detection to prevent bus
deadlocks
Local ECU ground-shift detection with two selectable
thresholds
Over-temperature warning
Battery monitoring to detect battery interrupt or a
chattering battery contact to store data before
microcontroller power down (e.g. to store seat
position)
Signalling of potential RAM-retention errors due to
low microcontroller V
CC
.
1.3
Fail-safe features
Programmable fail-safe coded window and time-out
watchdog with on-chip oscillator, guaranteeing
autonomous fail-safe system supervision
Fail-safe coded 16-bit SPI interface to microcontroller,
including chip-select pin for multiple SPI devices on the
same bus
Integrated fail-safe and system features:
Rigorous error handling based on diagnostics
12 dedicated reset sources supporting different,
history dependent, software start-up and diagnosis
Global enable pin for control of safety critical
hardware
Limp home output signal for activating application
hardware in case system enters Fail-safe mode
(e.g. switch on parking lights)
Single SPI message; no assembly of multiple SPI
frames
Programmable active-low system reset with
detection of both clamped and open reset line to
prevent system deadlocks
Fail-safe coded activation of Software Development
mode and Flash mode
24-bit access-protected RAM can be used, for
instance, for logging of cyclic problems.
2004 Mar 22
4
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
1.4
CAN physical layer
ISO11898-3 compliant fault-tolerant CAN transceiver
Downwards compatible with TJA1054/TJA1054A
Enhanced error signalling and reporting
Separated low-drop-out voltage regulator for CAN bus:
Microcontroller supply independent, autonomous
physical layer bus failure management
Significantly improves EMC performance
Partial networking capability:
Completely passive behaviour to the bus when
unpowered
Selective Sleep option with global wake-up allowing
selected CAN bus communication without waking-up
sleeping nodes.
1.5
LIN physical layer
LIN2.0 compatible LIN transceiver
Enhanced error signalling and reporting.
2
GENERAL DESCRIPTION
The UJA1061 is a System Basis Chip (SBC), replacing
basic discrete components that are commonly used in
Electronic Control Units (ECUs) for automotive body
multiplexing. The UJA1061 supports any body application
which controls various power peripherals by using the
fault-tolerant CAN as the main physical layer and the LIN
physical layer as local sub-bus. The UJA1061 contains the
following integrated devices:
Low speed, fault-tolerant CAN transceiver,
inter-operable and downwards compatible with CAN
transceivers TJA1054 and TJA1054A, and compatible
with ISO11898-3 standard
LIN transceiver compatible with LIN specification,
revision 2.0
Watchdog
Separate voltage regulators for both host controller and
CAN transceiver
Serial peripheral interface (full duplex)
Local wake-up input port
Inhibit output port.
In addition to the cost advantages compared with
conventional multi-chip solutions, the UJA1061 offers an
intelligent combination of system-specific functions such
as:
Advanced low power concept
Safe and controlled system start-up behaviour
Advanced fail-safe system behaviour that prevents any
deadlock
Detailed status reporting on system and sub-system (for
example, CAN) levels.
The UJA1061 is intended to be used in combination with a
microcontroller and a CAN controller. The microcontroller
is the first to come and the last to go in an ECU designed
with the UJA1061. In failure situations, the UJA1061
maintains the microcontroller function as long as possible
in order to provide full monitoring and software driven
fall-back operation.
The UJA1061 can be operated in:
Single 42 V power supply architecture when combined
with an external step-down converter
Single 14 V power supply architecture
Dual 14 V and 42 V power supply architecture.
3
ORDERING INFORMATION
Note
1. Add suffix to indicate version:
* = 5V0 for 5 V version
* = 3V3 for 3.3 V version
* = 3V0 for 3 V version
* = 2V5 for 2.5 V version.
TYPE
NUMBER
(1)
PACKAGE
NAME
DESCRIPTION
VERSION
UJA1061TW/*
HTSSOP32
plastic thermal enhanced thin shrink small outline package;
32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
SOT549-1
PDF 
ZIP
