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Product Description
Ordering Information
Typical Applications
Features
Functional Block Diagram
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Optimum Technology Matching Applied
Si BJT
GaAs MESFET
GaAs HBT
Si Bi-CMOS
SiGe HBT
Si CMOS
InGaP/HBT
GaN HEMT
SiGe Bi-CMOS
NKD-100-D
MILLIMETER-WAVE FREQUENCY DOUBLER
MMIC 5GHz TO 24GHz
Narrow and Broadband Commercial and
Military Radio Designs
Linear and Saturated Radio Applications
Upconversion Stage used in MW
Radio/Optical Designs
The NKD-100-D is a millimeter-wave frequency doubler
MMIC for general purpose microwave upconversion
needs. This 50
building block is based upon a reliable
InGaP/GaAs HBT proprietary MMIC design, providing
unsurpassed performance for microwave frequency
translation up to 24GHz. The circuit operates over a
broad range of input power drive. The NKD-100-D design
offers excellent rejection of third and fourth harmonics
enabling a significant reduction in filter requirements. The
doubler MMIC is offered in chip form for ease of integra-
tion into higher-order modules. The circuit incorporates
external DC decoupling capacitors and bias resistor for
maximum design flexibility.
Low Conversion Loss, 10dB@24GHz
Low Current Consumption, I
CC
=25mA
Broadband Performance 5GHz to 12GHz
Input Frequency
Single Power Supply Operation
50
I/O for Low VSWR
NKD-100-D
Millimeter-Wave Frequency Doubler MMIC 5GHz to
24GHz - Die Only (100 pieces minimum order)
0
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INPUT
OUTPUT
GND
VIA
0.017 0.001
(0.44 0.03)
0.017 0.001
(0.44 0.03)
0.004 0.001
(0.10 0.03)
UNITS:
Inches
(mm)
Back of chip is ground.
Package Style: Die
NOT FOR NEW DESIGNS
!
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Absolute Maximum Ratings
Parameter
Rating
Unit
RF Input Power
+20
dBm
Power Dissipation
300
mW
Device Current
70
mA
Channel Temperature
200
C
Operating Temperature
-45 to +85
C
Storage Temperature
-65 to +150
C
Exceeding any one or a combination of these limits may cause permanent damage.
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
Overall
V
D
=+3.35V, I
CC
=25mA, Z
0
=50
,
T
A
=+25C
Input Frequency, f
IN
5
12
GHz
Conversion Loss, L
(conv)
12.7
15
dB
f
OUT
=10GHz to 12.0GHz, P
IN
=+10dBm
12.2
14.5
dB
f
OUT
=12GHz to 14.0GHz, P
IN
=+10dBm
11.5
14.0
dB
f
OUT
=14GHz to 16.0GHz, P
IN
=+10dBm
10.5
13.0
dB
f
OUT
=16GHz to 20.0GHz, P
IN
=+10dBm
10.0
12.5
dB
f
OUT
=20GHz to 24.0GHz, P
IN
=+10dBm
Input and Output VSWR
1.4
f=5.0GHz to 10.0GHz
1.58
f=10.0GHz to 15.0GHz
1.92
f=15.0GHz to 20.0GHz
3rd Harmonic
-10
dB
Relative to 2nd harmonic
Device Voltage, V
D
3.15
3.35
3.55
V
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
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Pin
Function
Description
Interface Schematic
1
RF IN
RF input pin. This pin is NOT internally DC blocked. A DC blocking
capacitor, suitable for the frequency of operation, should be used in
most applications. DC coupling of the input is not allowed, because this
will override the internal feedback loop and cause temperature instabil-
ity.
2
GND
Ground connection. For best performance, keep traces physically short
and connect immediately to ground plane.
3
RF OUT
RF output and bias pin. Biasing is accomplished with an external series
resistor and choke inductor to V
CC
. The resistor is selected to set the
DC current into this pin to a desired level. The resistor value is deter-
mined by the following equation:
Care should also be taken in the resistor selection to ensure that the
current into the part never exceeds maximum datasheet current over
the planned operating temperature. This means that a resistor between
the supply and this pin is always required, even if a supply near 5.0V is
available, to provide DC feedback to prevent thermal runaway. Because
DC is present on this pin, a DC blocking capacitor, suitable for the fre-
quency of operation, should be used in most applications. The supply
side of the bias network should also be well bypassed.
4
GND
Same as pin 2.
R
V
CC
V
DEVICE
(
)
I
CC
-------------------------------------------
=
RF OUT
RF IN
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Typical Bias Configuration
Application notes related to biasing circuit, device footprint, and thermal considerations are available on request.
Sales Criteria - Unpackaged Die
Die Sales Information
All segmented die are sold 100% DC-tested. Testing parameters for wafer-level sales of die material shall be nego-
tiated on a case-by-case basis.
Segmented die are selected for customer shipment in accordance with RFMD Document #6000152 - Die Product
Final Visual Inspection Criteria
1
.
Segmented die has a minimum sales volume of 100 pieces per order. A maximum of 400 die per carrier is allow-
able.
Die Packaging
All die are packaged in GelPak ESD protective containers with the following specification:
O.D.=2"X2", Capacity=400 Die (20X20 segments), Retention Level=High(X8).
GelPak ESD protective containers are placed in a static shield bag. RFMD recommends that once the bag is
opened the GelPak/s should be stored in a controlled nitrogen environment. Do not press on the cover of a closed
GelPak, handle by the edges only. Do not vacuum seal bags containing GelPak containers.
Precaution must be taken to minimize vibration of packaging during handling, as die can shift during transit
2
.
Package Storage
Unit packages should be kept in a dry nitrogen environment for optimal assembly, performance, and reliability.
Precaution must be taken to minimize vibration of packaging during handling, as die can shift during transit
2
.
Die Handling
Proper ESD precautions must be taken when handling die material.
Die should be handled using vacuum pick-up equipment, or handled along the long side with a sharp pair of twee-
zers. Do not touch die with any part of the body.
When using automated pick-up and placement equipment, ensure that force impact is set correctly. Excessive force
may damage GaAs devices.
Recommended Bias Resistor Values
Voltage Supply, V
CC
(V) 5
8
10
12
15
Resistor Value (
)
66
186
266
346
466
X2
C block
1
3
4
2
C
BLOCK
In
F
0
Out
2F
0
L choke
(optional)
R bias
V
CC
V
DEVICE
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Die Attach
The die attach process mechanically attaches the die to the circuit substrate. In addition, the utilization of proper die
attach processes electrically connect the ground to the trace on which the chip is mounted. It also establishes the
thermal path by which heat can leave the chip.
Die should be mounted to a clean, flat surface. Epoxy or eutectic die attach are both acceptable attachment meth-
ods. Top and bottom metallization are gold. Conductive silver-filled epoxies are recommended. This procedure
involves the use of epoxy to form a joint between the backside gold of the chip and the metallized area of the sub-
strate.
All connections should be made on the topside of the die. It is essential to performance that the backside be well
grounded and that the length of topside interconnects be minimized.
Some die utilize vias for effective grounding. Care must be exercised when mounting die to preclude excess run-out
on the topside.
Die Wire Bonding
Electrical connections to the chip are made through wire bonds. Either wedge or ball bonding methods are accept-
able practices for wire bonding.
All bond wires should be made as short as possible.
Notes
1
RFMD Document #6000152 - Die Product Final Visual Inspection Criteria. This document provides guidance for die
inspection personnel to determine final visual acceptance of die product prior to shipping to customers.
2
RFMD takes precautions to ensure that die product is shipped in accordance with quality standards established to min-
imize material shift. However, due to the physical size of die-level product, RFMD does not guarantee that material will
not shift during transit, especially under extreme handling circumstances. Product replacement due to material shift will
be at the discretion of RFMD.
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