6LOLFRQ ,PDJH ,QF
Subject to Change without Notice
Si
I
151A PanelLink
Receiver
Datasheet
May 2000
General Description
Features
The Si
I
151A receiver uses PanelLink Digital technology to support high
resolution displays up to SXGA. The Si
I
151A receiver supports up to true
color panels (24 bit/pixel, 16.7M colors) in 1 or 2 pixels/clock mode. In
addition, the receiver data output is time staggered to reduce ground bounce
that affects EMI. Since all PanelLink products are designed on scaleable
CMOS architecture to support future performance requirements while
maintaining the same logical interface, system designers can be assured that
the interface will be fixed through a number of technology and performance
generations.
PanelLink Digital technology simplifies PC and display interface design
by resolving many of the system level issues associated with high-speed
mixed signal design, providing the system designer with a digital interface
solution that is quicker to market and lower in cost.
Low Power: 3.3V core operation
Time staggered data output for reduced ground
bounce
Sync Detect: for Plug & Display "Hot Plugging"
Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
Compliant with DVI 1.0 (DVI is backwards
compatible with VESA
P&D
TM
and DFP)
Si
I
151
A Pin Diagram
R S V D
1
SiI 151A
1 0 0 - P i n T Q F P
(Top View)
P D
2
S T
3
P I X S
4
G N D
5
V C C
6
S T A G _ O U T
7
S C D T
8
P D O
9
Q E 0
1 0
Q E 1
1 1
Q E 2
1 2
Q E 3
1 3
Q E 4
1 4
Q E 5
1 5
Q E 6
1 6
Q E 7
1 7
O V C C
1 8
O G N D
1 9
Q E 8
2 0
Q E 9
2 1
Q E 1 0
2 2
Q E 1 1
2 3
Q E 1 2
2 4
Q E 1 3
2 5
QE14
26
QE15
27
OGND
28
OVCC
29
QE16
30
QE17
31
QE18
32
QE19
33
QE20
34
QE21
35
QE22
36
QE23
37
VCC
38
GND
39
CTL1
40
CTL2
41
CTL3
42
OVCC
43
ODCK
44
OGND
45
DE
46
VSYNC
47
HSYNC
48
QO0
49
QO1
50
7 5
Q O 2 1
7 4
Q O 2 0
7 3
Q O 1 9
7 2
Q O 1 8
7 1
Q O 1 7
7 0
Q O 1 6
6 9
G N D
6 8
V C C
6 7
Q O 1 5
6 6
Q O 1 4
6 5
Q O 1 3
6 4
Q O 1 2
6 3
Q O 1 1
6 2
Q O 1 0
6 1
Q O 9
6 0
Q O 8
5 9
O G N D
5 8
O V C C
5 7
Q O 7
5 6
Q O 6
5 5
Q O 5
5 4
Q O 4
5 3
Q O 3
5 2
Q O 2
5 1
Q O 2 2
OCK_INV
100
RESERVED
99
PGND
98
PVCC
9
7
EXT_RES
96
AVCC
9
5
RXC-
94
RXC+
93
AGND
92
RX0-
91
RX0+
9
0
AGND
89
AVCC
8
8
AGND
87
RX1-
86
RX1+
85
AVCC
84
AGND
83
AVCC
82
RX2-
8
1
RX2+
80
AGND
7
9
OVCC
78
QO23
77
OGND
76
D I F F E R E N T I A L
S I G N A L
ODD 8-bits RED
E V E N 8 - b i t s R E D
ODD 8-bits GREEN
EVEN 8-bits GREEN
ODD 8-bits BLUE
EVEN 8-bits BLUE
CONFIG. PINS
P L L
PWR
MANAGEMENT
G P O
OUTPUT CLOCK
C O N T R O L S
6LOLFRQ ,PDJH ,QF
SiI 151
A
SiI
/DS-0029-A
6LOLFRQ ,PDJH ,QF
2
Subject to Change without Notice
Functional Block Diagram
Absolute Maximum Conditions
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Supply Voltage 3.3V
-0.3
4.0
V
V
I
Input Voltage
-0.3
V
CC
+
0.3
V
V
O
Output Voltage
-0.3
V
CC
+
0.3
V
T
A
Ambient Temperature (with power
applied)
-25
105
C
T
STG
Storage Temperature
-40
125
C
P
PD
Package Power Dissipation
1
W
Notes:
1
Permanent device damage may occur if absolute maximum conditions are exceeded.
2
Functional operation should be restricted to the conditions described under Normal Operating Conditions.
Normal Operating Conditions
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Supply Voltage
3.00
3.3
3.6
V
V
CCN
Supply Voltage Noise
100
mV
P-P
T
A
Ambient Temperature (with power
applied)
0
25
70
C
C T L 3
R X 2 +
R X 2 -
R X 1 +
R X 1 -
R X 0 +
R X 0 -
R X C +
R X C -
S Y N C 2
E X T _ R E S
P D O
S T
O D C K
P I X S
D F 0
O C K _ I N V
S T A G _ O U T
D a t a R e c o v e r y
C H 2
V C R
Termination
Control
D a t a R e c o v e r y
C H 1
V C R
D a t a R e c o v e r y
C H 0
V C R
P L L
V C R
S Y N C 1
S Y N C 0
C h a n n e l
S Y N C
S Y N C 2
S Y N C 1
S Y N C 0
D e c o d e r
C T L 2
C T L 1
V S Y N C
H S Y N C
Panel
Inter-
f a c e
Logic
Q E [ 2 3 : 0 ]
2 4
Q O [ 2 3 : 0 ]
2 4
D E
H S Y N C
V S Y N C
C T L 3
C T L 2
C T L 1
S C D T
D A T A
D A T A
D A T A
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SiI 151
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SiI
/DS-0029-A
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Subject to Change without Notice
DC Digital I/O Specifications
Under normal operating conditions unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IH
High-level Input
Voltage
2
V
V
IL
Low-level Input
Voltage
0.8
V
V
OH
High-level Output
Voltage
2.4
V
V
OL
Low-level Output
Voltage
0.4
V
V
CINL
Input Clamp Voltage
1
I
CL
= -18mA
GND -0.8
V
V
CIPL
Input Clamp Voltage
1
I
CL
= 18mA
IVCC + 0.8
V
V
CONL
Output Clamp
Voltage
1
I
CL
= -18mA
GND -0.8
V
V
COPL
Output Clamp
Voltage
1
I
CL
= 18mA
OVCC + 0.8
V
I
OL
Output Leakage
Current
High
Impedance
-10
10
A
Note:
1
Guaranteed by design.
DC Specifications
Under normal operating conditions unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
I
OHD
Output High Drive Data and
Controls
V
OUT
= V
OH
; ST = 1
ST = 0
4.2
2.1
8
4
18
9
mA
I
OLD
Output Low Drive Data and
Controls
V
OUT
= V
OL
; ST = 1
ST = 0
-5.2
-2.6
-5.5
-2.75
-11
-5.5
mA
I
OHC
ODCK High Drive
V
OUT
= V
OH
; ST = 1
ST = 0
8.5
4.2
17
9
37
18
mA
I
OLC
ODCK Low Drive
V
OUT
= V
OL
; ST = 1
ST = 0
-10.4
-5.2
-16
-8
-23
-11
mA
V
ID
Differential Input Voltage
Single Ended Amplitude
75
1000
mV
I
PD
Power-down Current
2
10
mA
I
CCR
Receiver Supply Current:
C
LOAD
= 10pF
R
EXT_SWING
= 560
With either ODCK=56MHz,
2-pixel/clock mode, or
ODCK=112MHz,
1-pixel/clock mode
Typical Pattern
3
185
240
mA
Worse Case Pattern
4
230
310
mA
Notes:
1
Guaranteed by design.
2
The transmitter must be in power-down mode, powered off, or disconnected for the current to be under this maximum.
3
The Typical Pattern contains a gray scale area, checkerboard area, and text.
4
Black and white checkerboard pattern, each checker is two pixel wide.
6LOLFRQ ,PDJH ,QF
SiI 151
A
SiI
/DS-0029-A
6LOLFRQ ,PDJH ,QF
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Subject to Change without Notice
AC Specifications
Under normal operating conditions unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
T
DPS
Intra-Pair (+ to -) Differential Input Skew
1
112MHz
1 pixel/clock
360
ps
T
CCS
Channel to Channel Differential Input Skew
1
112MHz
1 pixel/clock
6
ns
T
IJIT
Worst Case Differential Input Clock Jitter
tolerance
2,3
65 MHz
1 pixel/clock
465
ps
112 MHz
1 pixel/clock
270
ps
D
LHT
Low-to-High Transition Time : Data and Controls
(56 MHz, 2-pixel/clock, PIXS=1)
C
L
= 10pF;
ST = 1
3.0
ns
C
L
= 5pF;
ST = 0
4.7
ns
Low-to-High Transition Time : Data and Controls
(112 MHz, 1-pixel/clock, PIXS=0)
C
L
= 10pF;
ST = 1
3.1
ns
C
L
= 5pF;
ST = 0
5.0
ns
ODCK
(56 MHz, 2-pixel/clock, PIXS=1)
C
L
= 10pF;
ST = 1
2.0
ns
C
L
= 5pF;
ST = 0
2.9
ns
ODCK
(112 MHz, 1-pixel/clock, PIXS=0)
C
L
= 10pF;
ST = 1
2.0
ns
C
L
= 5pF;
ST = 0
2.8
ns
D
HLT
High-to-Low Transition Time: Data and Controls
(56 MHz, 2-pixel/clock, PIXS=1)
C
L
= 10pF;
ST = 1
2.8
ns
C
L
= 5pF;
ST = 0
3.9
ns
High-to-Low Transition Time: Data and Controls
(112MHz, 1-pixel/clock, PIXS=0)
C
L
= 10pF;
ST = 1
2.7
ns
C
L
= 5pF;
ST = 0
3.7
ns
ODCK
(56 MHz, 2-pixel/clock, PIXS=1)
C
L
= 10pF;
ST = 1
1.5
ns
C
L
= 5pF;
ST = 0
2.5
ns
ODCK
(112 MHz, 1-pixel/clock, PIXS=0)
C
L
= 10pF;
ST = 1
1.5
ns
C
L
= 5pF;
ST = 0
2.3
ns
T
SETUP
Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup
Time to ODCK falling edge (OCK_INV = 0) or to
ODCK rising edge (OCK_INV = 1) at 112 MHz
C
L
= 10pF;
ST = 1
1.7
*1.3
ns
*OCK_INV = 1
C
L
= 5pF;
ST = 0
1.1
*0.9
ns
T
HOLD
Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time
to ODCK falling edge, (OCK_INV = 0) or to ODCK
rising edge (OCK_INV = 1) at 112 MHz, PIXS=0
C
L
= 10pF;
ST = 1
5.6
*4.7
ns
*OCK_INV = 0
C
L
= 5pF;
ST = 0
6.0
*6.0
ns
Notes:
1
Guaranteed by design.
2
Jitter defined as per DVI 1.0 Specification, Section 4.6 Jitter Specification.
3
Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electrical Measurement Procedures.
4
Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.
5
Measured when transmitter was powered down (see Si
I
/AN-0005 "PanelLink Basic Design/Application Guide," Section 2.4).
6LOLFRQ ,PDJH ,QF
SiI 151
A
SiI
/DS-0029-A
6LOLFRQ ,PDJH ,QF
5
Subject to Change without Notice
AC Specifications (continued)
Under normal operating conditions unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
R
CIP
ODCK Cycle Time
1
(1-pixel/clock)
8.9
40
ns
F
CIP
ODCK Frequency
1
(1-pixel/clock)
25
112
MHz
R
CIP
ODCK Cycle Time
1
(2-pixels/clock)
17.8
80
ns
F
CIP
ODCK Frequency
1
(2-pixels/clock)
12.5
56
MHz
R
CIH
ODCK High Time
4
(112MHz, 1-pixel/clock, PIXS = 0)
C
L
= 10pF;
ST = 1
3.0
ns
C
L
= 5pF;
ST = 0
1.1
ns
R
CIL
ODCK Low Time
4
(112MHz, 1-pixel/clock, PIXS = 0)
C
L
= 10pF;
ST = 1
3.5
ns
C
L
= 5pF;
ST = 0
2.1
ns
T
PDL
Delay from PD or PDO Low to high impedance
outputs
1
10
ns
T
HSC
Link disabled (DE inactive) to SCDT low
1
100
ms
Link disabled (Tx power down) to SCDT low
5
250
ms
T
FSC
Link enabled (DE active) to SCDT high
1
25
DE
edges
T
ST
ODCK high to even data output
1
0.25
R
CIP
Notes:
1
Guaranteed by design.
2
Jitter defined as per DVI 1.0 Specification, Section 4.6 Jitter Specification.
3
Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electrical Measurement Procedures.
4
Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.
5
Measured when transmitter was powered down (see Si
I
/AN-0005 "PanelLink Basic Design/Application Guide," Section 2.4).
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