STPC

CONSUMER-II

X86 Core PC Compatible Information Appliance System-on-Chip

Release 1.5 - January 29, 2002

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Figure 0-1. Logic Diagram

POWERFUL x86 PROCESSOR

64-BIT SDRAM UMA CONTROLLER

VGA & SVGA CRT CONTROLLER

135 MHz RAMDAC

2D GRAPHICS ENGINE

VIDEO INPUT PORT

VIDEO PIPELINE
- UP-SCALER
- VIDEO COLOUR SPACE CONVERTER
- CHROMA & COLOUR KEY SUPPORT

TV OUTPUT
- THREE-LINE FLICKER FILTER
- ITU-R 601/656 SCAN CONVERTER
- NTSC / PAL COMPOSITE, RGB, S-VIDEO

PCI MASTER / SLAVE / ARBITER

ISA MASTER / SLAVE

OPTIONAL 16-BIT LOCAL BUS INTERFACE

EIDE CONTROLLER

I²C INTERFACE

IPC
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS

POWER MANAGEMENT UNIT

JTAG IEEE1149.1

DESCRIPTION

The STPC Consumer-II integrates a standard 5th
generation x86 core, a Synchronous DRAM
controller, a graphics subsystem, a video pipeline,
and support logic including PCI, ISA, and IDE
controllers to provide a single consumer
orientated PC compatible subsystem on a single
device.
The device is based on a tightly coupled Unified
Memory Architecture (UMA), sharing memory
between the CPU, the graphics and the video.

The STPC Consumer-II is packaged in a 388
Plastic Ball Grid Array (PBGA).

PBGA388

ons

er II

x86

Core

Host

I/F

SDRAM

CTRL

SVGA

VIP

PCI
m/s

CTR

PCI Bus

ISA
m/s

IPC

PCI
m/s

ISA Bus

CRTC

Cursor

Monitor

IDE

I/F

PMU

Video

Pipeline

C Key
K Key

LUT

Local Bus

Encoder

TVO

JTAG

STPC

CONSUMER-II

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Release 1.5 - January 29, 2002

X86 Processor core

Fully static 32-bit five-stage pipeline, x86

processor fully PC compatible.

Can access up to 4 GB of external memory.

8 Kbyte unified instruction and data cache

with write back and write through capability.

Parallel processing integral floating point unit,

with automatic power down.

Runs up to 100 MHz (x1) or 133 MHz (x2).

Fully static design for dynamic clock control.

Low power and system management modes.

Optimized design for 2.5 V operation.

SDRAM Controller

64-bit data bus.

Up to 100 MHz SDRAM clock speed.

Integrated system memory, graphic frame

memory and video frame memory.

Supports 2 MB up to 128 MB system

memory.

Supports 16-, 64-, and 128-Mbit SDRAMs.

Supports 8, 16, 32, 64, and 128 MB DIMMs.

Supports buffered, non buffered, and

registered DIMMs

Four-line write buffers for CPU to SDRAM

and PCI to SDRAM cycles.

Four-line read prefetch buffers for PCI

masters.

Programmable latency

Programmable timing for SDRAM

parameters.

Supports -8, -10, -12, -13, -15 memory parts

Supports memory hole between 1 MB and

8 MB for PCI/ISA busses.

2D Graphics Controller

64-bit windows accelerator.

Backward compatibility to SVGA standards.

Hardware acceleration for text, bitblts,

transparent blts and fills.

Up to 64 x 64 bit graphics hardware cursor.

Up to 4MB long linear frame buffer.

8-, 16-, 24- and 32-bit pixels.

Drivers availables for various OSes.

CRT Controller

Integrated 135 MHz triple RAMDAC allowing

for 1280 x 1024 x 75 Hz display.

Requires external frequency synthesizer and

reference sources.

8-bit, 16-bit, 24-bit pixels.

Interlaced or non-interlaced output.

Requires no external frequency synthesizer.

Requires only external reference source.

Video Input port

Accepts video inputs in ITU-R 601 mode.

Optional 2:1 decimator

Stores captured video in off setting area of

the onboard frame buffer.

Video pass through to the TV output for full

screen video images.

HSYNC and B/T generation or lock onto

external video timing source.

Video Pipeline

Two-tap interpolative horizontal filter.

Two-tap interpolative vertical filter.

Colour space conversion (RGB to YUV and

YUV to RGB).

Programmable window size.

Chroma and colour keying for integrated

video overlay.

Video Output

NTSC-M; PAL-B, D, G, H, I, M, N encoding.

ITU-R 601 encoding with programmable

colour subcarrier frequencies.

ITU-R 656 video output signal interface.

Four analog outputs in two configurations:

- R,G,B + CVBS
- C,YS,CVBS1 + CVBS2

Flicker-free interlaced output.

Programmable two tap filter with gamma

correction or three tap flicker filter.

Interlaced or non-interlaced operation mode.

Progressive to interlaced scan converter.

Cross colour reduction by specific trap

filtering on luma within CVBS flow.

Power down mode available on each DAC.

STPC

CONSUMER-II

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PCI Controller

Fully compliant with PCI 2.1 specification.

Integrated PCI arbitration interface. Up to 3

masters can connect directly. External PAL
allows for greater than 3 masters.

Translation of PCI cycles to ISA bus.

Translation of ISA master initiated cycle to

PCI.

Support for burst read/write from PCI master.

PCI clock is 1/2, 1/3 or 1/4 cpu bus clock.

ISA master/slave

Generates the ISA clock from either

14.318 MHz oscillator clock or PCI clock

Supports programmable extra wait state for

ISA cycles

Supports I/O recovery time for back to back

I/O cycles.

Fast Gate A20 and Fast reset.

Supports the single ROM that C, D, or E.

blocks shares with F block BIOS ROM.

Supports flash ROM.

Supports ISA hidden refresh.

Buffered DMA & ISA master cycles to reduce

bandwidth utilization of the PCI and Host
bus.

Local Bus interface

Multiplexed with ISA/DMA interface.

Low latency asynchronous bus

22-bit address bus.

16-bit data bus with word steering capability.

Programmable timing (Host clock granularity)

Two Programmable Flash Chip Select.

Four Programmable I/O Chip Select.

Supports 32-bit Flash burst.

Two-level hardware key protection for Flash

boot block protection.

Supports two banks of 16 MB flash devices

with boot block shadowed to 0x000F0000.

IDE Interface

Supports PIO

Transfer Rates to 22 MBytes/sec

Supports up to 4 IDE devices

Concurrent channel operation (PIO modes) -

4 x 32-Bit Buffer FIFOs per channel

Support for PIO mode 3 & 4.

Individual drive timing for all four IDE devices

Supports both legacy & native IDE modes

Supports hard drives larger than 528MB

Support for CD-ROM and tape peripherals

Backward compatibility with IDE (ATA-1).

Drivers for Windows and other Operating

Systems

Integrated Peripheral Controller

2X8237/AT compatible 7-channel DMA

controller.

2X8259/AT compatible interrupt Controller.

16 interrupt inputs - ISA and PCI.

Three 8254 compatible Timer/Counters.

Co-processor error support logic.

Power Management

Four power saving modes: On, Doze,

Standby, Suspend.

Programmable system activity detector

Supports Intel & Cyrix SMM and APM.

Supports STOPCLK.

Supports IO trap & restart.

Independent peripheral time-out timer to

monitor hard disk, serial & parallel port.

128K SM_RAM address space from

0xA0000 to 0xB0000

JTAG

Boundary Scan compatible IEEE1149.1.

Scan Chain control.

Bypass register compatible IEEE1149.1.

ID register compatible IEEE1149.1.

RAM BIST control.

The STPC Consumer-II has undergone an errata fix upgrade. The different versions can be differenciated by the part
number. Both versions are pin to pin compatible and there are some software extensions that have been added to the
upgraded parts. The parts labeled STPCC5 are the upgraded parts and the differences are identified in both the Datash-
eet and Programming Manual. All parts labeled STPCC4 do not support the new features outlined in the documentation.
Where nor C4 nor C5 are specified, the information or feature applies to both versions.

GENERAL DESCRIPTION

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1. GENERAL DESCRIPTION

At the heart of the STPC Consumer-II is an
advanced 64-bit x86 processor block. It includes a
64-bit SDRAM controller, advanced 64-bit
accelerated graphics and video controller, a high
speed PCI local-bus controller and Industry
standard PC chip set functions (Interrupt
controller, DMA Controller, Interval timer and ISA
bus).

The STPC Consumer-II has in addition, an EIDE
Controller, I

C Interface, a Local Bus interface and

a JTAG interface.

1.1. ARCHITECTURE

The STPC Consumer-II makes use of a tightly
coupled Unified Memory Architecture (UMA),
where the same memory array is used for CPU
main memory and graphics frame-buffer. This
means a reduction in total system memory for
system performances that are equal to that of a
comparable frame buffer and system memory
based system, and generally much better, due to
the higher memory bandwidth allowed by
attaching the graphics engine directly to the 64-bit
processor host interface running at the speed of
the processor bus rather than the traditional PCI
bus. The 64-bit wide memory array provides the
system with 528MB/s peak bandwidth. This allows
for higher resolution screens and greater color
depth.

The `standard' PC chipset functions (DMA,
interrupt controller, timers, power management
logic) are integrated together with the x86
processor core; additional functions such as
communications ports are accessed by the STPC
Consumer-II via internal ISA bus.

The PCI bus is the main data communication link
to the STPC Consumer-II chip. The STPC
Consumer-II translates appropriate host bus I/O
and Memory cycles onto the PCI bus. It also
supports generation of Configuration cycles on the
PCI bus. The STPC Consumer-II, as a PCI bus
agent (host bridge class), fully complies with PCI
specification 2.1. The chip-set also implements
the PCI mandatory header registers in Type 0 PCI
configuration space for easy porting of PCI aware
system BIOS. The device contains a PCI
arbitration function for three external PCI devices.

The STPC Consumer-II has two functional blocks

sharing the same balls

: The ISA / IPC / IDE block

and the Local Bus / IDE block (see Table 3). Any
board with the STPC Consumer-II should be built
using only one of these two configurations. The
IDE pins are dynamically multiplexed in each of
the blocks in ISA mode only.

Configuration is done by `strap options'. It is a set
of pull-up or pull-down resistors on the memory
data bus, checked on reset, which auto-configure
the STPC Consumer-II.

1.2. GRAPHICS FEATURES

Graphics functions are controlled through the on-
chip SVGA controller and the monitor display is
produced through the 2D graphics display engine.

This Graphics Engine is tuned to work with the
host CPU to provide a balanced graphics system
with a low silicon area cost. It performs limited
graphics drawing operations which include
hardware acceleration of text, bitblts, transparent
blts and fills. The results of these operations
change the contents of the on-screen or off-
screen frame buffer areas of SDRAM memory.
The frame buffer can occupy a space up to 4
Mbytes anywhere in the physical main memory.

The graphics resolution supported is a maximum
of 1280x1024 in 16M colors and 16M colors at
75Hz refresh rate, VGA and SVGA compatible.
Horizontal timing fields are VGA compatible while
the vertical fields are extended by one bit to
accommodate above display resolution.

1.3. VIDEO FUNCTIONS

The STPC Consumer-II provides several
additional functions to handle MPEG or similar
video streams. The Video Input Port accepts an
encoded digital video stream in one of a number of
industry standard formats, decodes it, optionally
decimates it, and deposits it into an off screen
area of the frame buffer. An interrupt request can
be generated when an entire field or frame has
been captured. The video output pipeline
incorporates a video-scaler and color space
converter function and provisions in the CRT
controller to display a video window. While
repainting the screen the CRT controller fetches
both the video as well as the normal non-video
frame buffer in two separate internal FIFOs. The
video stream can be color-space converted
(optionally) and smooth scaled. Smooth
interpolative scaling in both horizontal and vertical
direction are implemented. Color and Chroma key
functions are also implemented to allow mixing
video stream with non-video frame buffer.

The video output passes directly to the RAMDAC
for monitor output or through another optional
color space converter (RGB to 4:2:2 YCrCb) to the
programmable anti-flicker filter. The flicker filter is
configured as either a two line filter with gamma
correction (primarily designed for DOS type text)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: STPCC4

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: STPCC4