1/20

0.5Msps to 20Msps sampling frequency

Adaptive power consumption: 120mW @
20Msps, 95mW@10Msps

Single supply voltage: 2.5V
Independent supply for CMOS output stage
with 2.5V/3.3V capability

ENOB=11.2 @ Nyquist

SFDR= -81.5 dBc @ Nyquist

1GHz analog bandwidth Track-and-Hold

Common clocking between channels

Dual simultaneous Sample and Hold inputs

Multiplexed outputs

Built-in reference voltage with external bias
capability.

DESCRIPTION

The TSA1204 is a new generation of high speed,
dual-channel Analog to Digital converter pro-
cessed in a mainstream 0.25祄 CMOS technolo-
gy yielding high performances and very low power
consumption.
The TSA1204 is specifically designed for applica-
tions requiring very low noise floor, high SFDR
and good isolation between channels. It is based
on a pipeline structure and digital error correction
to provide excellent static linearity and over 11.2
effective bits at Fs=20Msps, and Fin=10MHz.
For each channel, a voltage reference is integrat-
ed to simplify the design and minimize external
components. It is nevertheless possible to use the
circuit with external references.
Each ADC outputs are multiplexed in a common
bus with small number of pins. A tri-state capabili-
ty is available for the outputs, allowing chip selec-
tion. The inputs of the ADC must be differentially
driven.
The TSA1204 is available in extended (-40 to
+85癈) temperature range, in a small 48 pins
TQFP package.

APPLICATIONS

Medical imaging and ultrasound

3G base station

I/Q signal processing applications

High speed data acquisition system

Portable instrumentation

ORDER CODE

PIN CONNECTIONS (top view)

BLOCK DIAGRAM

PACKAGE

Part Number

Temperature

Range

Package

Conditioning

Marking

TSA1204IF

-40癈 to +85癈

TQFP48

Tray

SA1204I

TSA1204IFT

-40癈 to +85癈

TQFP48

Tape & Reel

SA1204I

EVAL1204/BA

Evaluation board

SE
LE
CT

CL
K

RE
F

AV
CC

DV
CC

IN
C

RE
F

NDB

D10

D11(MSB)

AVCCB

index
corner

14 15

18 19

44 43

38 37

TSA1204

VCCBE

GNDBE

AGND

INI

AGND

IPOL

AGND

INBQ

INIB

AGND

INQ

RE
FM

D0
(
L

SB
)

AV
CC

RE
FP
I

I
NCM

AV
CC

VC
CB
I

DB
E

VC
CB
I

VC
CB
E

Timing

Buffers

IPOL

CLK

+2.5V/3.3V

VINI

VINBI

OEB

VINCMI

GND

VINQ

VINBQ

VINCMQ

AD 12
I channel

AD 12
Q channel

M
U

REF I

REF Q

SELECT

VREFPI

VREFPQ

Polar.

VREFMI

VREFMQ

common mode

D0
TO
D11

VCCBE

GNDBE

�

7 mm TQFP48

TSA1204

DUAL-CHANNEL, 12-BIT, 20MSPS, 120mW A/D CONVERTER

February 2003

TSA1204

2/20

CONDITIONS
AVCC = DVCC = VCCB = 2.5V, Fs= 20Msps, Fin=10.5MHz, Vin@ -1dBFS, VREFP=1.0V, VREFM=0V
Tamb = 25癈 (unless otherwise specified)

DYNAMIC CHARACTERISTICS

TIMING CHARACTERISTICS

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

SFDR

Spurious Free Dynamic Range

-81.5

-71.0

dBc

SNR

Signal to Noise Ratio

66.9

68.5

THD

Total Harmonics Distortion

-80

-70

dBc

SINAD

Signal to Noise and Distortion Ratio

64.8

ENOB

Effective Number of Bits

10.6

11.2

bits

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

Sampling Frequency

0.5

MHz

Clock Duty Cycle

TC1

Clock pulse width (high)

22.5

TC2

Clock pulse width (low)

22.5

Tod

Data Output Delay (Clock edge to Data Valid)

10pF load capacitance

Tpd I

Data Pipeline delay for I channel

cycles

Tpd Q

Data Pipeline delay for Q channel

7.5

cycles

Ton

Falling edge of OEB to digital output valid data

Toff

Rising edge of OEB to digital output tri-state

TSA1204

3/20

TIMING DIAGRAM

PIN CONNECTIONS (top view)

N-1

N+1

N+6

N+7

N+2

N+5

N+3

N+4

N+8

CLK

Tpd I + Tod

N+9

N+10

N+11

N+12

N+13

DATA

OUTPUT

sample N+1
I channel

sample N
Q channel

sample N+1
Q channel

sample N+2
I channel

sample N+2
Q channel

sample N+3
I channel

OEB

Simultaneous sampling
on I/Q channels

SELECT

sample N-9
I channel

sample N-8
I channel

sample N-7
Q channel

sample N-6
Q channel

CLOCK AND SELECT CONNECTED TOGETHER

Tod

SE
L

CLK

RE
F

AV
C

DV
CC

IN
C

RE
F

D10

D11(MSB)

AVCCB

index
corner

14 15

TSA1204

VCCBE

GNDBE

AGND

INI

AGND

IPOL

AGND

INBQ

INIB

AGND

INQ

RE
F

SB)

AV
C

IN
C

AVC

CCB

TSA1204

4/20

PIN DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

OPERATING CONDITIONS

Pin No

Name

Description

Observation

Pin No

Name

Description

Observation

AGND

Analog ground

GNDBE

Digital buffer ground

INI

I channel analog input

VCCBE

Digital Buffer power supply

2.5V/3.3V

AGND

Analog ground

D11(MSB) Most Significant Bit output

CMOS output (2.5V/3.3V)

INBI

I channel inverted analog input

D10

Digital output

CMOS output (2.5V/3.3V)

AGND

Analog ground

Digital output

CMOS output (2.5V/3.3V)

IPOL

Analog bias current input

Digital output

CMOS output (2.5V/3.3V)

AVCC

Analog power supply

2.5V

Digital output

CMOS output (2.5V/3.3V)

AGND

Analog ground

Digital output

CMOS output (2.5V/3.3V)

INQ

Q channel analog input

Digital output

CMOS output (2.5V/3.3V)

AGND

Analog ground

Digital output

CMOS output (2.5V/3.3V)

INBQ

Q channel inverted analog input

Digital output

CMOS output (2.5V/3.3V)

AGND

Analog ground

Digital output

CMOS output (2.5V/3.3V)

REFPQ

Q channel top reference voltage

Digital output

CMOS output (2.5V/3.3V)

REFMQ

Q channel bottom reference
voltage

D0(LSB)

Least Significant Bit output

CMOS output (2.5V/3.3V)

INCMQ

Q channel input common mode

VCCBE

Digital Buffer power supply

2.5V/3.3V - See Application
Note

AGND

Analog ground

GNDBE

Digital buffer ground

AVCC

Analog power supply

2.5V

VCCBI

Digital Buffer power supply

2.5V

DVCC

Digital power supply

2.5V

DVCC

Digital Buffer power supply

2.5V

DGND

Digital ground

OEB

Output Enable input

2.5V/3.3V CMOS input

CLK

Clock input

2.5V CMOS input

AVCC

Analog power supply

2.5V

SELECT

Channel selection

2.5V CMOS input

AVCC

Analog power supply

2.5V

DGND

Digital ground

INCMI

I channel input common mode

DVCC

Digital power supply

2.5V

REFMI

I channel bottom reference voltage 0V

GNDBI

Digital buffer ground

REFPI

I channel top reference voltage

Symbol

Parameter

Values

Unit

AVCC

Analog Supply voltage

0 to 3.3

DVCC

Digital Supply voltage

0 to 3.3

VCCBE

Digital buffer Supply voltage

0 to 3.6

VCCBI

Digital buffer Supply voltage

0 to 3.3

IDout

Digital output current

-100 to 100

Tstg

Storage temperature

+150

癈

ESD

HBM: Human Body Model

CDM: Charged Device Model

1.5

Latch-up Class

1). All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not exceed -0.3V or VCC

2). ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5k

3). Discharge to Ground of a device that has been previously charged.

4). Corporate ST Microelectronics procedure number 0018695

Symbol

Parameter

Min

Typ

Max

Unit

AVCC

Analog Supply voltage

2.25

2.5

2.7

DVCC

Digital Supply voltage

2.25

2.5

2.7

VCCBE

External Digital buffer Supply voltage

1.8

2.5

3.5

VCCBI

Internal Digital buffer Supply voltage

2.25

2.5

2.7

TSA1204

5/20

Condition VRefP-VRefM>0.3V

ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCB = 2.5V, Fs= 20Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=1.0V, VREFM=0V
Tamb = 25癈 (unless otherwise specified)

ANALOG INPUTS

DIGITAL INPUTS AND OUTPUTS

VREFPI

VREFPQ

Forced top voltage reference

0.96

1.4

VREFMI

VREFMQ

Forced bottom reference voltage

0.4

INCMI

INCMQ

Forced input common mode voltage

0.2

Symbol

Parameter

Min

Typ

Max

Unit

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

VIN-VINB Full scale reference voltage

Differential inputs mandatory

1.1

2.0

2.8

Vpp

Cin

Input capacitance

7.0

Req

Equivalent input resistor

Analog Input Bandwidth

Vin@Full Scale, Fs=20Msps

1000

MHz

ERB

Effective Resolution Bandwidth

MHz

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

Clock and Select inputs

VIL

Logic "0" voltage

0.8

VIH

Logic "1" voltage

2.0

2.5

OEB input

VIL

Logic "0" voltage

0.25 x

VCCBE

VIH

Logic "1" voltage

0.75 x

VCCBE

Digital Outputs

VOL

Logic "0" voltage

Iol=10礎

0.1 x

VCCBE

VOH

Logic "1" voltage

Ioh=10礎

0.9 x

VCCBE

IOZ

High Impedance leakage current OEB set to VIH

-1.7

1.7

礎

Output Load Capacitance

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: TSA1204

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: TSA1204