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AM26LV32C, AM26LV32I
LOW VOLTAGE HIGH SPEED QUADRUPLE DIFFERENTIAL LINE RECEIVER
SLLS202E - MAY 1995 - REVISED JUNE 2005
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Switching Rates up to 32 MHz
D
Operates From Single 3.3-V Supply
D
Ultra-Low Power Dissipation . . . 27 mW Typ
D
Open-Circuit, Short-Circuit, and Terminated
Fail-Safe
D
-0.3-V to 5.5-V Common-Mode Range With
200-mV Sensitivity
D
Accepts 5-V Logic Inputs With 3.3-V V
CC
D
Input Hysteresis . . . 50 mV Typ
D
235 mW With Four Receivers at 32 MHz
D
Pin-to-Pin Compatible With AM26C32,
AM26LS32, and MB570
description/ordering information
The AM26LV32, BiCMOS, quadruple, differential line receiver with 3-state outputs is designed to be similar to
TIA/EIA-422-B and ITU Recommendation V.11 receivers with reduced common-mode voltage range due to
reduced supply voltage.
The device is optimized for balanced bus transmission at switching rates up to 32 MHz. The enable function
is common to all four receivers and offers a choice of active-high or active-low inputs. The 3-state outputs permit
connection directly to a bus-organized system. Each device features receiver high input impedance and input
hysteresis for increased noise immunity, and input sensitivity of
200 mV over a common-mode input voltage
range from -0.3 V to 5.5 V. When the inputs are open circuited, the outputs are in the high logic state. This device
is designed using the Texas Instruments (TI
) proprietary LinIMPACT-C60
technology, facilitating ultra-low
power consumption without sacrificing speed.
This device offers optimum performance when used with the AM26LV31 quadruple line drivers.
The AM26LV32C is characterized for operation from 0
C to 70
C. The AM26LV32I is characterized for operation
from -45
C to 85
C.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
AM26LV32CDG4
D
Tape and reel
AM26LV32CDR
AM26LV32C
0
C to 70
C
D
Tape and reel
AM26LV32CDRG4
AM26LV32C
0 C to 70 C
NS
Tube
AM26LV32CNS
26LV32
NS
Tape and reel
AM26LV32CNSR
26LV32
SOP D
Tube
AM26LV32ID
AM26LV32I
-40
C to 85
C
SOP D
Tube
AM26LV32IDR
AM26LV32I
-40
C to 85
C
SOP NS
Tube
AM26LV32INS
26LV32I
SOP NS
Tape and reel
AM26LV32INSR
26LV32I
Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
Copyright
2005, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinIMPACT-C60 and TI are trademarks of Texas Instruments.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1Y
G
2Y
2A
2B
GND
V
CC
4B
4A
4Y
G
3Y
3A
3B
D OR NS PACKAGE
(TOP VIEW)
AM26LV32C, AM26LV32I
LOW VOLTAGE HIGH SPEED QUADRUPLE DIFFERENTIAL LINE RECEIVER
SLLS202E - MAY 1995 - REVISED JUNE 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each receiver)
DIFFERENTIAL
ENABLES
OUTPUT
DIFFERENTIAL
INPUT
G
G
OUTPUT
VID
0.2 V
H
X
X
L
H
H
- 0.2 V < VID < 0.2 V
H
X
X
L
?
?
VID
- 0.2 V
H
X
X
L
L
L
Open, shorted, or
terminated
H
X
X
L
H
H
X
L
H
Z
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
See application information attached.
logic symbol
4Y
3Y
2Y
1Y
13
11
5
3
4B
4A
3B
3A
2B
2A
1B
1A
G
G
15
14
9
10
7
6
1
2
12
4
EN
1
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
logic diagram (positive logic)
4Y
3Y
2Y
1Y
13
11
5
3
4B
4A
3B
3A
2B
2A
1B
1A
G
G
15
14
9
10
7
6
1
2
12
4
AM26LV32C, AM26LV32I
LOW VOLTAGE HIGH SPEED QUADRUPLE DIFFERENTIAL LINE RECEIVER
SLLS202E - MAY 1995 - REVISED JUNE 2005
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
schematics of equivalent inputs and outputs
Enable
G, G
VCC
TYPICAL OF ALL OUTPUTS (Y)
Y
VCC
GND
GND
EQUIVALENT OF EACH
ENABLE INPUT (G, G)
A, B
VCC
GND
EQUIVALENT OF EACH INPUT (A, B)
7.2 k
15 k
1.5 k
7.2 k
1.5 k
100
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
(see Note 1)
-0.3 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(A or B inputs)
-4 V to 8 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, V
ID
(see Note 2)
12 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable input voltage range
-0.3 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
-0.3 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum output current, I
O
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): D package
73
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
64
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. All voltage values are with respect to the GND terminal.
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC
3
3.3
3.6
V
High-level input voltage, VIH(EN)
2
V
Low-level input voltage, VIL(EN)
0.8
V
Common-mode input voltage, VIC
-0.3
5.5
V
Differential input voltage, VID
5.8
High-level output current, IOH
-5
mA
Low-level output current, IOL
5
mA
Operating free-air temperature, TA
AM26LV32C
0
70
C
Operating free-air temperature, TA
AM26LV32I
-40
85
C
AM26LV32C, AM26LV32I
LOW VOLTAGE HIGH SPEED QUADRUPLE DIFFERENTIAL LINE RECEIVER
SLLS202E - MAY 1995 - REVISED JUNE 2005
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended supply-voltage and operating free-air temperature
ranges (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIT+
Differential input high-threshold voltage
0.2
V
VIT-
Differential input low-threshold voltage
-0.2
V
VIK
Enable input clamp voltage
II = - 18 mA
-0.8
-1.5
V
VOH
High-level output voltage
VID = 200 mV,
IOH = - 5 mA
2.4
3.2
V
VOL
Low-level output voltage
VID = - 200 mV,
IOL = 5 mA
0.17
0.5
V
IOZ
High-impedance-state output current
VO = 0 to VCC
50
A
IIH(E)
High-level enable input current
VCC = 0 or 3 V,
VI = 5.5 V
10
A
IIL(E)
Low-level enable input current
VCC = 3.6 V,
VI = 0 V
-10
A
rI
Input resistance
7
12
k
II
Input current
VI = 5.5 V or - 0.3 V,
All other inputs GND
700
A
ICC
Supply current
VI(E) = VCC or GND, No load, line inputs open
8
17
mA
Cpd
Power dissipation capacitance
One channel
150
pF
All typical values are at VCC = 3.3 V and TA = 25
C.
Cpd determines the no-load dynamic current: IS = Cpd
VCC
f + ICC.
switching characteristics, V
CC
= 3.3 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low- to high-level output
See Figure 1
8
16
20
ns
tPHL
Propagation delay time, high- to low-level output
See Figure 1
8
16
20
ns
tt
Transistion time (tr or tf)
See Figure 1
5
ns
tPZH
Output-enable time to high level
See Figure 2
17
40
ns
tPZL
Output-enable time to low level
See Figure 3
10
40
ns
tPHZ
Output-disable time from high level
See Figure 2
20
40
ns
tPLZ
Output-disable time from low level
See Figure 3
16
40
ns
tsk(p)
Pulse skew
4
6
ns
tsk(o)
Pulse skew
4
6
ns
tsk(pp)#
Pulse skew (device to device)
6
9
ns
tsk(p) is |tPLH - tPHL| of each channel of the same device.
tsk(o) is the maximum difference in propagation delay times between any two channels of the same device switching in the same direction.
# tsk(pp) is the maximum difference in propagation delay times between any two channels of any two devices switching in the same direction.
AM26LV32C, AM26LV32I
LOW VOLTAGE HIGH SPEED QUADRUPLE DIFFERENTIAL LINE RECEIVER
SLLS202E - MAY 1995 - REVISED JUNE 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50
50
Generator
(see Note B)
VCC
CL = 15 pF
(see Note A)
tPLH
tPHL
90%
90%
50%
50%
10%
10%
tr
tf
A
B
Input
Output
2 V
1 V
VOH
VOL
A
B
Y
VO
G
G
(see Note C)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: ZO = 50
, PRR = 10 MHz, tr and tf (10% to 90%)
2 ns, 50% duty cycle.
C. To test the active-low enable G, ground G and apply an inverted waveform G.
Figure 1. t
PLH
and t
PHL
Test Circuit and Voltage Waveforms
50%
Input
tPZH
tPHZ
VOH
50%
50%
Voff
0
0 V
VCC
Output
Generator
(see Note B)
50
RL = 2 k
CL = 15 pF
(see Note A)
VCC
(see Note C)
VID = 1 V
A
B
Y
VO
G
G
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: ZO = 50
, PRR = 10 MHz, tr and tf (10% to 90%)
2 ns, 50% duty cycle.
C. To test the active-low enable G, ground G and apply an inverted waveform G.
VOH - 0.3 V
Figure 2. t
PZH
and t
PHZ
Test Circuit and Voltage Waveforms
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