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TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

High-Performance Static CMOS Technology

 Standard CAN Controller (SCC)

TMS470R1x 16/32-Bit RISC Core

16-Mailbox Capacity

(ARM7TDMITM)

Fully Compliant With CAN Protocol,

 24-MHz System Clock (48-MHz Pipeline

Version 2.0B

Mode)

 Class II Serial Interface (C2SIb)

 Independent 16/32-Bit Instruction Set

Two Selectable Data Rates

 Open Architecture With Third-Party Support

Normal Mode 10.4 Kbps and 4X Mode 41.6

 Built-In Debug Module

Kbps

 Big-Endian Format Utilized

High-End Timer (HET)

Integrated Memory

 16 Programmable I/O Channels:

 256K-Byte Program Flash

14 High-Resolution Pins

One Bank With 14 Contiguous Sectors

2 Standard-Resolution Pins

Internal State Machine for Programming

 High-Resolution Share Feature (XOR)

and Erase

 High-End Timer RAM

 12K-Byte Static RAM (SRAM)

64-Instruction Capacity

Operating Features

10-Bit Multi-Buffered ADC (MibADC)

 Core Supply Voltage (VCC): 1.81 V2.05 V

16-Channel

 I/O Supply Voltage (VCCIO): 3.0 V3.6 V

 64-Word FIFO Buffer

 Low-Power Modes: STANDBY and HALT

 Single- or Continuous-Conversion Modes

 Industrial Temperature Ranges

 1.55

s Minimum Sample and Conversion

Time

470+ System Module

 Calibration Mode and Self-Test Features

 32-Bit Address Space Decoding

Eight External Interrupts

 Bus Supervision for Memory and

Peripherals

Flexible Interrupt Handling

 Analog Watchdog (AWD) Timer

11 Dedicated GIO Pins, 1 Input-Only GIO Pin,
and 38 Additional Peripheral I/Os (A256)

 Real-Time Interrupt (RTI)

External Clock Prescale (ECP) Module

 System Integrity and Failure Detection

 Programmable Low-Frequency External

Zero-Pin Phase-Locked Loop (ZPLL)-Based

Clock (CLK)

Clock Module With Prescaler

Compatible ROM Device

 Multiply-by-4 or -8 Internal ZPLL Option

On-Chip Scan-Base Emulation Logic, IEEE

 ZPLL Bypass Mode

Standard 1149.1 (JTAG) Test-Access Port

(1)

Six Communication Interfaces:

100-Pin Plastic Low-Profile Quad Flatpack (PZ

 Two Serial Peripheral Interfaces (SPIs)

Suffix)

255 Programmable Baud Rates

 Two Serial Communications Interfaces

(SCIs)

(1)

The test-access port is compatible with the IEEE Standard
1149.1-1990, IEEE Standard Test-Access Port and Boundary

Selectable Baud Rates

Scan Architecture. Boundary scan is not supported on this

Asynchronous/Isosynchronous Modes

device.

ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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100

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

ADIN[11]

ADIN[14]

ADIN[10]

ADIN[13]

ADIN[9]

ADIN[12]

REFHI

REFLO

CCAD

SSAD

TMS

TMS2

HET[0]

FLTP2

FLTP1

CCP

HET[2]

HET[4]

HET[6]

HET[7]

AWD

HET[18]

HET[20]

HET[21]

SPI2SCS

SPI2ENA

SPI2SOMI

SPI2SIMO

SPI2CLK

C2SIbRX

C2SIbTX

C2SIbLPN

HET[24]

HET[31]

SCI2TX

SCI2RX

GIOA[3]/INT3

GIOA[2]/INT2

GIOA[1]/INT1/ECLK

GIOA[0]/INT0

(A)

TEST

TRST

SPI1ENA

SPI1SCS

SPI1SIMO

SPI1SOMI

SPI1CLK

OSCOUT

OSCIN

RST

I
O

GIOB[3]

GIOB[2]

GIOB[1]

GIOB[0]

HET[13]

HET[12]

HET[1

HET[10]

PORRST

GIOA[7]/INT7

GIOA[6]/INT6

GIOA[5]/INT5

GIOA[4]/INT4

ADIN[0]

ADIN[1]

ADIN[2]

ADIN[3]

ADIN[4]

ADIN[15]

ADIN[5]

ADIN[6]

ADIN[7]

ADEVT

SCI1RX

SCI1TX

SCI1CLK

CANSTX

CANSRX

CLKOUT

I
O

HET[8]

TCK

TDO

TDI

PLLDIS

ADIN[8]

HET[19]

DESCRIPTION

TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

TMS470R1A256 100-PIN PZ PACKAGE (TOP VIEW)

GIOA[0]/INT0 (pin 28) is an input-only GIO pin.

The TMS470R1A256

(1)

devices are members of the Texas Instruments TMS470R1x family of general-purpose

16/32-bit reduced instruction set computer (RISC) microcontrollers. The A256 microcontroller offers high
performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a
high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views
memory as a linear collection of bytes numbered upwards from 0. The TMS470R1A256 utilizes the big-endian
format where the most significant byte of a word is stored at the lowest numbered byte and the least significant
byte at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low
costs. The A256 RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.

The A256 device contains the following:

ARM7TDMI 16/32-Bit RISC CPU

TMS470R1x system module (SYS) with 470+ enhancements

(1)

Throughout the remainder of this document, the TMS470R1A256 device name will be referred to as either the full device name,
TMS470R1A256, or as A256.

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TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

256K-byte Flash

12K-byte SRAM

Zero-pin phase-locked loop (ZPLL) clock module

Analog watchdog (AWD) timer

Real-time interrupt ( RTI) module

Two serial peripheral interface (SPI) modules

Two serial communications interface (SCI) modules

Standard CAN controller (SCC)

Class II serial interface (C2SIb)

10-bit multi-buffered analog-to-digital converter (MibADC), 16-input channels

High-end timer (HET) controlling 16 I/Os

External Clock Prescale (ECP)

Up to 49 I/O pins and 1 input-only pin

The functions performed by the 470+ system module (SYS) include:

Address decoding

Memory protection

Memory and peripherals bus supervision

Reset and abort exception management

Prioritization for all internal interrupt sources

Device clock control

Parallel signature analysis (PSA)

This data sheet includes device-specific information such as memory and peripheral select assignment,
interrupt priority, and a device memory map. For a more detailed functional description of the SYS module,
see the TMS470R1x System Module Reference Guide (literature number SPNU189).

The A256 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.

The Flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented
with a 32-bit-wide data bus interface.The Flash operates with a system clock frequency of up to 24 MHz. In
pipeline mode, the Flash operates with a system clock frequency of up to 48 MHz. For more detailed information
on the Flash, see the Flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature
number SPNU213).

The A256 device has six communication interfaces: two SPIs, two SCIs, an SCC, and a C2SIb. The SPI provides
a convenient method of serial interaction for high-speed communications between similar shift-register type
devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the
CPU and other peripherals using the standard Non-Return-to-Zero (NRZ) format. The SCC uses a serial,
multimaster communication protocol that efficiently supports distributed real-time control with robust communi-
cation rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy and
harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring. The
C2SIb allows the A256 to transmit and receive messages on a class II network following an SAE J1850

(2)

standard. For more detailed functional information on the SPI, SCI, and SCC peripherals, see the specific
reference guides (literature numbers SPNU195, SPNU196, and SPNU197, respectively). For more detailed
functional information on the C2SIb peripheral, see the TMS470R1x Class II Serial Interface B (C2SIb)
Reference Guide (literature number SPNU214).

The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an
attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited
for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.
For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).

(2)

SAE Standard J1850 Class B Data Communication Network Interface

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TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

The A256 device has a 10-bit-resolution sample-and-hold MibADC. The MibADC channels can be converted
individually or can be grouped by software for sequential conversion sequences. There are three separate
groupings, two of which are triggerable by an external event. Each sequence can be converted once when
triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC,
see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number
SPNU206).

The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a
clock-enable circuit, and a prescaler (with prescale values of 18). The function of the ZPLL is to multiply the
external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system
(SYS) module. The SYS module subsequently provides the system clock (SYSCLK), real-time interrupt clock
(RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other A256 device modules. For more
detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase Locked Loop (ZPLL) Clock
Module Reference Guide (literature number SPNU212).

NOTE:

ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the
continuous system clock from an external resonator/crystal reference.

The A256 device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the
peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).

www.ti.com

device characteristics

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

The TMS470R1A256 device is a derivative of the F05 system emulation device SE470R1VB8AD. Table 1
identifies all the characteristics of the TMS470R1A256 device except the SYSTEM and CPU, which are generic.

Table 1. Device Characteristics

DEVICE DESCRIP-

CHARACTERISTICS

COMMENTS

TION

MEMORY

For the number of memory selects on this device, see the "Memory Selection Assignment" table (Table 2).

Flash is pipeline-capable.

256K-Byte Flash

INTERNAL MEMORY

The A256 RAM is implemented in one 12K array selected by two memory-select

12K-Byte SRAM

signals (see the "Memory Selection Assignment" table, Table 2).

PERIPHERALS

For the device-specific interrupt priority configurations, see the "Interrupt Priority" table (Table 4). For the 1K peripheral address ranges and
their peripheral selects, see the "A256 Peripherals, System Module, and Flash Base Addresses" table (Table 3).

CLOCK

ZPLL

Zero-pin PLL has no external loop filter pins.

GENERAL-PURPOSE I/Os

11 I/O 1 Input only

Port A has 8 external pins and Port B has 4 external pins.

ECP

YES

C2SIb

SCI

1 (3-pin) 1 (2-pin)

SCI2 has no external clock pin, only transmit/receive pins (SCI2TX and SCI2RX)

CAN

1 SCC

Standard CAN controller

(HECC and/or SCC)

SPI (5-pin, 4-pin or 3-pin)

2 (5-pin)

The A256 devices have both the logic and registers for a full 32-I/O HET
implemented, even though not all 32 pins are available externally.

The high-resolution (HR) SHARE feature allows even HR pins to share the next
higher odd HR pin structures. This HR sharing is independent of whether or not the

HET with XOR Share

16 I/O

odd pin is available externally. If an odd pin is available externally and shared, then
the odd pin can only be used as a general-purpose I/O.

For more information on HR SHARE, see the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199).

HET RAM

64-Instruction Capacity

10-bit, 16-channel

Both the logic and registers for a full 16-channel MibADC are present. The

MibADC

64-word FIFO

MibADC is capable of being event-triggered from a user-selectable event source.

CORE VOLTAGE

1.812.05 V

I/O VOLTAGE

3.03.6 V

PINS

100

PACKAGE

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SPI1SCS

SPI2SCS

ZPLL

MibADC

with

64-Word

FIFO

PLLDIS

OSCOUT

ADIN[15:0]

ADEVT

REFLO

REFHI

HET with

XOR Share

(64-Word)

SPI2

SCI1

SCC

SSAD

HET [31:29, 24]
HET[22:0]

CANSRX

CANSTX

SCI1TX

SCI1CLK

CCAD

RAM

(12K Bytes)

TMS470R1x

CPU

CPU Address/Data Bus

TMS470R1x 470+ SYSTEM MODULE

OSCIN

External Pins

CCP

FLTP1

FLTP2

TCK

TMS

TDO

TDI

TRST

AWD

RST

TMS2

PORRST

CLKOUT

FLASH

(256K Bytes)

14 Sectors

C2SIb

C2SIbTX

C2SIbLPN

C2SIbRX

SCI1RX

Crystal

External Pins

SPI1

SPI2CLK

SPI2ENA

SPI2SIMO

SPI2SOMI

GIO

GIOA[0]/INT[0

]
(
A

)

GIOA[2:7]/

TEST

GIOA[1]/INT[1]/

ECP

ECLK

SCI2

SCI2TX

SCI2RX

SPI1CLK

SPI1ENA

SPI1SIMO

SPI1SOMI

INT[2:7]

Expansion Address/Data Bus

GIOB[3:0]

TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

functional block diagram

GIOA[0]/INT[0] is an input-only GIO pin.

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TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

Table 2. Terminal Functions

TERMINAL

INTERNAL

TYPE

(1) (2)

PULLUP/

DESCRIPTION

PIN

NAME

PULLDOWN

(3)

NUMBER

HIGH-END TIMER (HET)

HET[0]

HET[1]

HET[2]

HET[3]

HET[4]

HET[5]

The A256 devices have both the logic and registers for a full 32-I/O
HET implemented, even though not all 32 pins are available

HET[6]

externally

HET[7]

100

Timer input capture or output compare. The HET[31:0] applicable

HET[8]

pins can be programmed as general-purpose input/output (GIO)
pins.

HET[9]

HET[10]

HET[21:18, 13:10, 8:6, 4, 2, 0] are high-resolution pins and HET[31,
24] are standard-resolution pins for A256.

HET[11]

The high-resolution (HR) SHARE feature allows even HR pins to

HET[12]

share the next higher odd HR pin structures. This HR sharing is

HET[13]

independent of whether or not the odd pin is available externally. If

3.3-V I/O

IPD

an odd pin is available externally and shared, then the odd pin can

HET[14]

only be used as a general-purpose I/O. For more information on HR

HET[15]

SHARE, see the TMS470R1x High-End Timer (HET) Reference

HET[16]

Guide (literature number SPNU199).

HET[17]

The HET[19] or HET[18] pins can also be used as a user-selectable
event source to event trigger the MibADC event group or group1 if

HET[18]

the associated register source bits are properly configured and

HET[19]

defined. For the internal device connections, see the MibADC
section of this data sheet. For more detailed functional information

HET[20]

on the MibADC, see the TMS470R1x Multi-Buffered

HET[21]

Analog-to-Digital Converter (MibADC) Reference Guide (literature
number SPNU206).

HET[22]

HET[24]

HET[28]

HET[29]

HET[30]

HET[31]

STANDARD CAN CONTROLLER (SCC)

CANSRX

3.3-V I/O

SCC receive pin or GIO pin

CANSTX

3.3-V I/O

IPU

SCC transmit pin or GIO pin

CLASS II SERIAL INTERFACE (C2SIb)

C2SIbLPN

3.3-V I/O

IPD

C2SIb module loopback enable pin or GIO pin

C2SIbRX

3.3-V I/O

C2SIb module receive data input pin or GIO pin

C2SIbTX

3.3-V I/O

IPD

C2SIb module transmit data output pin or GIO pin

(1)

I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect

(2)

All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.

(3)

IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST
state.)

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TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

Table 2. Terminal Functions (continued)

TERMINAL

INTERNAL

TYPE

(1) (2)

PULLUP/

DESCRIPTION

PIN

NAME

PULLDOWN

(3)

NUMBER

GENERAL-PURPOSE I/O (GIO)

GIOA[0]/INT0

3.3-V I

GIOA[1]/INT1/

ECLK

GIOA[2]/INT2

GIOA[3]/INT3

General-purpose input/output pins.

GIOA[4]/INT4

GIOA[0]/INT[0] is an input-only pin. GIOA[7:0]/INT[7:0] are inter-

GIOA[5]/INT5

rupt-capable pins.

GIOA[6]/INT6

GIOA[1]/INT[1]/ECLK pin is multiplexed with the external clock-out

GIOA[7]/INT7

3.3-V I/O

IPD

function of the external clock prescale (ECP) module.

GIOB[0]

GIOB[1]

GIOB[2]

GIOB[3]

MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)

MibADC event input. ADEVT can be programmed as a GIO pin.The
ADEVT pin can also be used as a user-selectable event source to
event trigger the MibADC event group or group1 if the associated

ADEVT

3.3-V I/O

register source bits are properly configured and defined. For the
internal device connections, see the MibADC section of this data
sheet.

ADIN[0]

ADIN[1]

ADIN[2]

ADIN[3]

ADIN[4]

ADIN[5]

IPD

ADIN[6]

ADIN[7]

3.3-V I

MibADC analog input pins

ADIN[8]

ADIN[9]

ADIN[10]

ADIN[11]

ADIN[12]

ADIN[13]

ADIN[14]

ADIN[15]

REFHI

3.3-V REF I

MibADC module high-voltage reference input

REFLO

GND REF I

MibADC module low-voltage reference input

CCAD

3.3-V PWR

MibADC analog supply voltage

SSAD

GND

MibADC analog ground reference.

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TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

Table 2. Terminal Functions (continued)

TERMINAL

INTERNAL

TYPE

(1) (2)

PULLUP/

DESCRIPTION

PIN

NAME

PULLDOWN

(3)

NUMBER

SERIAL PERIPHERAL INTERFACE 1 (SPI1)

SPI1CLK

SPI1 clock. SPI1CLK can be programmed as a GIO pin.

SPI1ENA

SPI1 chip enable. SPI1ENA can be programmed as a GIO pin.

SPI1SCS

SPI1 slave chip select. SPI1SCS can be programmed as a GIO pin.

3.3-V I/O

IPD

SPI1 data stream. Slave in/master out. SPI1SIMO can be pro-

SPI1SIMO

grammed as a GIO pin.

SPI1 data stream. Slave out/master in. SPI1SOMI can be pro-

SPI1SOMI

grammed as a GIO pin.

SERIAL PERIPHERAL INTERFACE 2 (SPI2)

SPI2CLK

SPI2 clock. SPI2CLK can be programmed as a GIO pin.

SPI2ENA

SPI2 chip enable. SPI2ENA can be programmed as a GIO pin.

SPI2SCS

SPI2 slave chip select. SPI2SCS can be programmed as a GIO pin.

3.3-V I/O

IPD

SPI2 data stream. Slave in/master out. SPI2SIMO can be pro-

SPI2SIMO

grammed as a GIO pin.

SPI2 data stream. Slave out/master in. SPI2SOMI can be pro-

SPI2SOMI

grammed as a GIO pin.

ZERO-PIN PHASE-LOCKED LOOP (ZPLL)

OSCIN

1.8-V I

Crystal connection pin or external clock input

OSCOUT

1.8-V O

External crystal connection pin

Enable/disable the ZPLL. The ZPLL can be bypassed and the
oscillator becomes the system clock. If not in bypass mode, TI

PLLDIS

3.3-V I

IPD

recommends that PLLDIS be connected to ground or pulled down to
ground by an external resistor.

SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)

SCI1CLK

3.3-V I/O

IPD

SCI1 clock. SCI1CLK can be programmed as a GIO pin.

SCI1RX

3.3-V I/O

IPU

SCI1 data receive. SCI1RX can be programmed as a GIO pin.

SCI1TX

3.3-V I/O

IPU

SCI1 data transmit. SCI1TX can be programmed as a GIO pin.

SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)

SCI2RX

3.3-V I/O

IPU

SCI2 data receive. SCI2RX can be programmed as a GIO pin.

SCI2TX

3.3-V I/O

IPU

SCI2 data transmit. SCI2TX can be programmed as a GIO pin.

SYSTEM MODULE (SYS)

Bidirectional pin. CLKOUT can be programmed as a GIO pin or the

CLKOUT

3.3-V I/O

IPD

output of SYSCLK, ICLK, or MCLK.

Input master chip power-up reset. External V

monitor circuitry

PORRST

3.3-V I

IPD

must assert a power-on reset.

Bidirectional reset. The internal circuitry can assert a reset, and an
external system reset can assert a device reset. On RST, the output

RST

3.3-V I/O

IPU

buffer is implemented as an open drain (drives low only). To ensure
an external reset is not arbitrarily generated, TI recommends that an
external pullup resistor be connected to RST.

WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)

Analog watchdog reset. The AWD pin provides a system reset if the
WD KEY is not written in time by the system, providing an external
RC network circuit is connected. If the user is not using AWD, TI
recommends that AWD be connected to ground or pulled down to
ground by an external resistor.

AWD

3.3-V I/O

IPD

For more details on the external RC network circuit, see the
TMS470R1x System Module Reference Guide(literature number
SPNU189) and the application note Analog Watchdog Resistor,
Capacitor and Discharge Interval Selection Constraints (literature
number SPNA005).

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TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

Table 2. Terminal Functions (continued)

TERMINAL

INTERNAL

TYPE

(1) (2)

PULLUP/

DESCRIPTION

PIN

NAME

PULLDOWN

(3)

NUMBER

TEST/DEBUG (T/D)

TCK

3.3-V I

IPD

Test clock. TCK controls the test hardware (JTAG)

Test data in. TDI inputs serial data to the test instruction register,

TDI

3.3-V I

IPU

test data register, and programmable test address (JTAG).

Test data out. TDO outputs serial data from the test instruction

TDO

3.3-V O

IPD

Test enable. Reserved for internal use only. TI recommends that

TEST

3.3-V I

IPD

TEST be connected to ground or pulled down to ground by an
external resistor.

Serial input for controlling the state of the CPU test access port

TMS

3.3-V I

IPU

(TAP) controller (JTAG)

Serial input for controlling the second TAP. TI recommends that

TMS2

3.3-V I

IPU

TMS2 be connected to VCCIO or pulled up to VCCIO by an external
resistor.

Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1

TRST

3.3-V I

IPD

(JTAG) Boundary-Scan Logic. TI recommends that TRST be pulled
down to ground by an external resistor.

FLASH

Flash test pads 1 and 2. For proper operation, these pins must

FLTP1

not be connected (no connect [NC]).

FLTP2

CCP

3.3-V PWR

Flash external pump voltage (3.3 V)

SUPPLY VOLTAGE CORE (1.8 V)

1.8-V PWR

Core logic supply voltage

SUPPLY VOLTAGE DIGITAL I/O (3.3 V)

CCIO

3.3-V PWR

Digital I/O supply voltage

SUPPLY GROUND CORE

GND

Core supply ground reference

SUPPLY GROUND DIGITAL I/O

SSIO

GND

Digital I/O supply ground reference

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A256 DEVICE-SPECIFIC INFORMATION

memory

0xFFE8_C000

0xFFE8_8000

0xFFFF_FFFF

System Module Control Registers

(512K Bytes)

Exception, Interrupt, and

Reset Vectors

Memory (4G Bytes)

Program

and

Data Area

Peripheral Control Registers

(512K Bytes)

Reserved

MPU Control Registers

Reserved

0xFFF8_0000

0xFFF7_FFFF

0xFFF0_0000

0xFFE8_BFFF

0xFFE8_7FFF

0xFFE8_4024
0xFFE8_4023

0xFFE8_4000

0xFFE0_0000

0x0000_001F

0x0000_0000

FIQ

IRQ

Reserved

Data Abort

Prefetch Abort

Software Interrupt

Undefined Instruction

Reset

0x0000_ 001F

0x0000_ 001C

0x0000_ 0018

0x0000_ 0014

0x0000_ 0010

0x0000_ 000C

0x0000_ 0008

0x0000_ 0004

0x0000_ 0000

Reserved

0xFFFF_FD00

0xFFF8_0000

HET

0xFFF7_FC00

0xFFF7_F800

0xFFF7_F400

0xFFF7_F000

0xFFF7_EC00

0xFFF7_E400

SPI1

SCI1

MibADC

GIO/ECP

Reserved

RAM

(12K Bytes)

FLASH

(256K Bytes)

14 Sectors

Flash Control Registers

Reserved

0xFFEF_FFFF

SCC RAM

SCC

0xFFF7_E000

0xFFF7_DC00

0xFFF7_D800

0xFFF7_D400

C2SIb

Reserved

0xFFF0_0000

SYSTEM

0xFFE8_3FFF

SCI2

0xFFF7_F500

Reserved

RESERVED

SPI2

0xFFF7_C800

0xFFF7_CC00

0xFFFF_FFFF

0x0000_0020

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

Figure 1 shows the memory map of the A256 device.

Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.

The CPU registers are not part of the memory map.

Figure 1. Memory Map

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memory selects

TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

Memory selects allow the user to address memory arrays (i.e., Flash, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that together define the array's starting (base) address, block size, and protection.

The base address of each memory select is configurable to any memory address boundary that is a multiple of
the decoded block size. For more information on how to control and configure these memory select registers, see
the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature number
SPNU189).

For the memory selection assignments and the memory selected, see Table 3.

Table 3. Memory Selection Assignment

MEMORY

MEMORY SELECTED

MEMORY

STATIC MEM

MPU

MEMORY BASE ADDRESS REGISTER

SELECT

(ALL INTERNAL)

SIZE

CTL REGISTER

0 (fine)

FLASH

MFBAHR0 and MFBALR0

256K

1 (fine)

FLASH

MFBAHR1 and MFBALR1

2 (fine)

RAM

YES

MFBAHR2 and MFBALR2

12K

(1)

3 (fine)

RAM

YES

MFBAHR3 and MFBALR3

4 (fine)

HET RAM

MFBAHR4 and MFBALR4

SMCR1

(1)

The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block
size in the memory-base address register.

RAM

The A256 device contains 12K bytes of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This RAM is implemented in one 12K array selected by two
memory-select signals. This configuration imposes an additional constraint on the memory map for RAM; the
starting addresses for both RAM memory selects cannot be offset from each other by the multiples of the size of
the physical RAM (i.e., 12K for the A256 device). The RAM is addressed through memory selects 2 and 3.

The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user
finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an
operating system while allowing access to the current task. For more detailed information on the MPU portion of
the SYS module and memory protection, see the memory section of the TMS470R1x System Module Reference
Guide (literature number SPNU189).

F05 Flash

The F05 Flash memory is a nonvolatile electrically erasable, and programmable memory implemented with a
32-bit-wide data bus interface. The F05 Flash has an external state machine for programming and erase
functions. See the Flash read and Flash program and erase sections of this document.

Flash protection keys

The A256 device provides Flash protection keys. These four 32-bit protection keys prevent pro-
gram/erase/compaction operations from occurring until after the four protection keys have been matched by the
CPU loading the correct user keys into the FMPKEY control register. The protection keys on the A256 are
located in the last 4 words of the first 8K sector. For more detailed information on the Flash protection keys and
the FMPKEY control register, see the protection keys portions of the TMS470R1x F05 Flash Reference Guide
(literature number SPNU213).

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TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

Flash read

The A256 Flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to
0xFFE0_0000. The Flash is addressed through memory selects 0 and 1.

NOTE:

The Flash external pump voltage (V

CCP

) is required for all operations (program, erase,

and read).

Flash pipeline mode

When in pipeline mode, the Flash operates with a system clock frequency of up to 48 MHz (versus a system
clock in normal mode of up to 24 MHz). Flash in pipeline mode is capable of accessing 64-bit words and
provides two 32-bit pipelined words to the CPU. Also in pipeline mode, the Flash can be read with no wait states
when memory addresses are contiguous (after the initial 1-or 2-wait-state reads).

NOTE:

After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a 0). In
other words, the A256 device powers up and comes out of reset in non-pipeline
mode. Furthermore, setting the Flash configuration mode bit (GLBCTRL.4) will
override pipeline mode.

Flash program and erase

The A256 device Flash has one 256K-byte bank that consists of fourteen sectors. These fourteen sectors are
sized as follows:

SECTOR NO.

SEGMENT

LOW ADDRESS

HIGH ADDRESS

8K Bytes

0x00000000

0x00001FFF

8K Bytes

0x00002000

0x00003FFF

8K Bytes

0x00004000

0x00005FFF

8K Bytes

0x00006000

0x00007FFF

32K Bytes

0x00008000

0x0000FFFF

32K Bytes

0x00010000

0x00017FFF

32K Bytes

0x00018000

0x0001FFFF

32K Bytes

0x00020000

0x00027FFF

32K Bytes

0x00028000

0x0002FFFF

32K Bytes

0x00030000

0x00037FFF

8K Bytes

0x00038000

0x00039FFF

8K Bytes

0x0003A000

0x0003BFFF

8K Bytes

0x0003C000

0x0003DFFF

8K Bytes

0x0003E000

0x0003FFFF

The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit
word.

NOTE:

The Flash external pump voltage (V

CCP

) is required for all operations (program, erase,

and read).

For more detailed information on Flash program and erase operations, see the TMS470R1x F05 Flash
Reference Guide (literature number SPNU213).

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peripheral selects and base addresses

TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

HET RAM

The A256 device contains HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is
configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET
RAM is addressed through memory select 4.

XOR share

The A256 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution
channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more
detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).

The A256 device uses 10 of the 16 peripheral selects to decode the base addresses of the peripherals. These
peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used by the
SYS module.

Control registers for the peripherals, SYS module, and Flash begin at the base addresses shown in Table 4.

Table 4. A256 Peripherals, System Module, and Flash Base Addresses

ADDRESS RANGE

CONNECTING MODULE

PERIPHERAL SELECTS

BASE ADDRESS

ENDING ADDRESS

SYSTEM

0xFFFF_FD00

0xFFFF_FFFF

N/A

RESERVED

0xFFF8_0000

0xFFFF_FCFF

N/A

HET

0xFFF7_FC00

0xFFF7_FFFF

PS[0]

SPI1

0xFFF7_F800

0xFFF7_FBFF

PS[1]

SCI2

0XFFF7_F500

0XFFF7_F7FF

PS[2]

SCI1

0xFFF7_F400

0xFFF7_F4FF

ADC

0xFFF7_F000

0xFFF7_F3FF

PS[3]

GIO/ECP

0xFFF7_EC00

0xFFF7_EFFF

PS[4]

RESERVED

0xFFF7_E400

0xFFF7_EBFF

PS[5] - PS[6]

SCC

0xFFF7_E000

0xFFF7_E3FF

PS[7]

SCC RAM

0xFFF7_DC00

0xFFF7_DFFF

PS[8]

RESERVED

0XFFF7_D800

0XFFF7_DBFF

PS[9]

SPI2

0XFFF7_D400

0XFFF7_D7FF

PS[10]

RESERVED

0xFFF7_CC00

0xFFF7_D3FF

PS[11] - PS[12]

C2SIb

0xFFF7_C800

0xFFF7_CBFF

PS[13]

RESERVED

0xFFF7_C000

0xFFF7_C7FF

PS[14] - PS[15]

RESERVED

0xFFF0_0000

0xFFF7_BFFF

N/A

FLASH CONTROL REGISTERS

0xFFE8_8000

0xFFE8_BFFF

N/A

MPU CONTROL REGISTERS

0xFFE8_4000

0xFFE8_4023

N/A

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interrupt priority

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

The central interrupt manager (CIM) portion of the SYS module manages the interrupt requests from the device
modules (i.e., SPI1 or SPI2, SCI1 or SCI2, and RTI, etc.).

Although the CIM can accept up to 32 interrupt request signals, the A256 device only uses 21 of those interrupt
request signals. The request channels are maskable so that individual channels can be selectively disabled. All
interrupt requests can be programmed in the CIM to be of either type:

Fast interrupt request (FIQ)

Normal interrupt request (IRQ)

The precedences of request channels decrease with ascending channel order in the CIM (0 [highest] and 31
[lowest] priority). For these channel priorities and the associated modules, see Table 5.

Table 5. Interrupt Priority

MODULES

INTERRUPT SOURCES

INTERRUPT LEVEL/CHANNEL

SPI1

SPI1 end-transfer/overrun

RTI

COMP2 interrupt

RTI

COMP1 interrupt

RTI

TAP interrupt

SPI2

SPI2 end-transfer/overrun

GIO

Interrupt A

RESERVED

HET

Interrupt 1

RESERVED

SCI1/SCI2

SCI1/SCI2 error interrupt

SCI1

SCI1 receive interrupt

C2SIb

C2SIb interrupt

RESERVED

SCC

Interrupt A

RESERVED

MibADC

End event conversion

SCI2

SCI2 receive interrupt

RESERVED

SCI1

SCI1 transmit interrupt

System

SW interrupt (SSI)

RESERVED

HET

Interrupt 2

RESERVED

SCC

Interrupt B

SCI2

SCI2 transmit interrupt

MibADC

End Group 1 conversion

RESERVED

GIO

Interrupt B

MibADC

End Group 2 conversion

RESERVED

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MibADC

TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a
10-bit digital value.

The A256 MibADC module can function in two modes: compatibility mode, where its programmer's model is
compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or in
buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion
group (event, group1 [G1], and group2 [G2]). In buffered mode, the MibADC buffers can be serviced by
interrupts.

MibADC event trigger enhancements

The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC.

Both group1 and the event group can be configured for event-triggered operation, providing up to two
event-triggered groups.

The trigger source and polarity can be selected individually for both group 1 and the event group from the
three options identified in Table 6.

Table 6. MibADC Event Hookup Configuration

EVENT #

SOURCE SELECT BITS for G1 or EVENT

SIGNAL PIN NAME

(G1SRC[1:0] or EVSRC[1:0])

EVENT1

ADEVT

EVENT2

HET18

EVENT3

HET19

EVENT4

RESERVED

For group 1, these event-triggered selections are configured through the group 1 source select bits (G1SRC[1:0])
in the AD event source register (ADEVTSRC.[5:4]). For the event group, these event-triggered selections are
configured through the event group source select bits (EVSRC[1:0]) in the AD event source register
(ADEVTSRC.[1:0]).

For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital
Converter (MibADC) Reference Guide (literature number SPNU206).

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documentation support

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

Extensive documentation supports all of the TMS470 microcontroller family generation of devices. The types of
documentation available include: data sheets with design specifications; complete user's guides; and errata
sheets. Useful reference documentation includes:

Bulletin
TMS470 Microcontroller Family Product Bulletin (literature number SPNB086)

Data Sheets
TMS470R1A128 16/32Bit RISC Microcontroller (literature number SPNS098)
TMS470R1A64 16/32Bit RISC Microcontroller (literature number SPNS099)
TMS470R1A256 16/32Bit RISC Microcontroller (literature number SPNS100)

User's Guides
TMS470R1x System Module Reference Guide (literature number SPNU189)
TMS470R1x General Purpose Input/Output (GIO) Reference Guide (literature number SPNU192)
TMS470R1x Serial Peripheral Interface (SPI) Reference Guide SPNU195
TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196)
TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197)
TMS470R1x High End Timer (HET) Reference Guide (literature number SPNU199)
TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202)
TMS470R1x MultiBuffered Analog to Digital (MibADC) Reference Guide (literature number SPNU206)
TMS470R1x ZeroPin Phase Locked Loop (ZPLL) Clock Module Reference Guide (literature number

SPNU212)

TMS470R1x F05 Flash Reference Guide (literature number SPNU213)
TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214)
TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (literature number SPNU218)
TMS470 Peripherals Overview Reference Guide (literature number SPNU248)

Errata Sheet:
TMS470R1A256 TMS470 Microcontrollers Silicon Errata (literature number SPNZ133)

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device numbering conventions

PREFIX

470

FAMILY

DEVICE TYPE A

= 100-pin Low-Profile Quad Flatpack (LQFP)

TMS

470 = TMS470 RISC - Embedded

Microcontroller Family

PACKAGE TYPE

ARCHITECTURE

R1 = ARM7TDM1 CPU

TMS = Fully Qualified Device

256 = 256K-Bytes Flash Memory

256

REVISION CHANGE

Blank = Original

Blank = No options

OPTIONS

FLASH MEMORY

With 256K-Bytes Flash memory:

1.8V Core, 3.3V I/O

Flash Program Memory

Temperature Range: -40

to +85

Celsius

ZPLL Clock

12K-Byte Static RAM

1K-Byte HET RAM (64 Instructions)

Analog Watchdog (AWD)

Real-Time Interrupt (RTI)

10-bit, 16-input MibADC

Two SPI Modules

Two SCI Modules

C2SIb

CAN [SCC]

HET, 16 Channels

ECP

TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

Figure 2 illustrates the numbering and symbol nomenclature for the TMS470R1x family.

Figure 2. TMS470R1x Family Nomenclature

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device identification code register

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

The device identification code register identifies the silicon version, the technology family (TF), a ROM or Flash
device, and an assigned device-specific part number (see Figure 3). The A256 device identification code register
value is 0x0857.

Reserved

VERSION

R/F

PART NUMBER

R-K

R-1

LEGEND: R = Read only; -K = value constant after RESET; -n = value after RESET

Figure 3. TMS470 Device ID Bit Allocation Register

TMS470 Device ID Bit Allocation Register Description

BIT

NAME

Value

DESCRIPTION

31-16

Reserved

Reads are undefined and writes have no effect.

15-12

VERSION

Silicon version (revision) bits
These bits identify what version of silicon the device is. Initial device version numbers start at 0000.

Technology Family (TF)
This bit distinguishes the technology family core power supply.

3.3 V for F10/C10 devices

1.8 V for F05/C05 devices

R/F

ROM/Flash
This bit distinguishes between ROM and Flash devices:

Flash device

ROM device

9-3

PART NUM-

Device-specific part number

BER

These bits identify the assigned device-specific part number.
The assigned device-specific part number for the A256 device is 0001010.

2-0

Mandatory High
Bits 2, 1, and 0 are tied high by default.

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Device electrical specifications and timing parameters

absolute maximum ratings over operating free-air temperature range

(1)

device recommended operating conditions

(1)

TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

Supply voltage ranges:

, V

CCF

(2)

-0.3 V to 2.5

Supply voltage ranges:

CCIO

, V

CCAD

, V

CCP

(Flash pump)

(2)

-0.3 V to 4.1V

Input voltage range:

All input pins

-0.3 V to 4.1

Input clamp current:

< 0 or V

> V

CCIO

)

20 mA

All pins except ADIN[0:15], PORRST,
TRST, TEST and TCK

< 0 or V

> V

CCAD

)

10 mA

ADIN[0:11]

Operating free-air temperature ranges, T

-40

C to 85

Operating junction temperature range, T

-40

C to 150

Storage temperature range, T

stg

-65

C to 150

(1)

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to their associated grounds.

MIN

NOM

MAX

UNIT

Digital logic and Flash supply voltage (Core)

1.81

2.05

CCIO

Digital logic supply voltage (I/O)

3.3

3.6

CCAD

ADC supply voltage

3.3

3.6

CCP

Flash pump supply voltage

3.3

3.6

Digital logic supply ground

SSAD

ADC supply ground

-0.1

0.1

Operating free-air temperature

-40

Operating junction temperature

-40

150

(1)

All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD.

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electrical characteristics over recommended operating free-air temperature range

(1)

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

hys

Input hysteresis

0.15

All inputs

(2)

except OSCIN

-0.3

0.8

Low-level input

voltage

OSCIN only

-0.3

0.35 V

All inputs except OSCIN

CCIO

+ 0. 3

High-level input

voltage

OSCIN only

0.65 V

+ 0. 3

Input threshold

AWD only

1.35

1.8

voltage

Drain to source

RDS

AWD only

(3)

VOL = 0.35V @ I

= 8mA

resistance

= I

MAX

0.2 V

CCIO

Low-level output voltage

(4)

= 50

0.2

= I

MIN

0.8 V

CCIO

High-level output voltage

(4)

= 50

CCIO

-0.2

< V

SSIO

-0. 3 or

Input clamp current (I/O pins)

(5)

-2

> V

CCIO

+ 0. 3

Pulldown

= V

-1

Pulldown

= V

CCIO

Input current

Pullup

= V

-40

-5

(I/O pins)

Pullup

= V

CCIO

-1

All other pins

No pullup or pulldown

-1

CLKOUT, AWD, TDO

= V

MAX

RST, SPI1CLK, SPI1SIMO,

Low-level output

SPI1SOMI, SPI2CLK,

= V

MAX

current

SPI2SIMO, SPI2SOMI

All other output pins

(6)

= V

MAX

CLKOUT, TDO

= V

MIN

-8

High-level out-

SPI1CLK, SPI1SIMO,

put

SPI1SOMI, SPI2CLK,

= V

MIN

-4

current

SPI2SIMO, SPI2SOMI

All other output pins

(6)

= V

MIN

-2

SYSCLK = 48 MHz, ICLK =
24 MHz,

= 2.05 V

digital supply current (operating mode)

SYSCLK = 24 MHz, ICLK =
12 MHz,

= 2.05 V

OSCIN = 6 MHz, V

digital supply current (standby mode)

(7)

3.0

2.05 V

All frequencies, V

= 2.05

digital supply current (halt mode)

(7)

1.0

(1)

Source currents (out of the device) are negative while sink currents (into the device) are positive.

(2)

This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section.

(3)

These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).

(4)

and V

are linear with respect to the amount of load current (I

) applied.

(5)

Parameter does not apply to input-only or output-only pins.

(6)

The 2 mA buffers on this device are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a
low level and the other is outputting a high level, the resulting value will always be low.

(7)

For Flash pumps/banks in sleep mode.

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PARAMETER MEASUREMENT INFORMATION

Tester Pin

Electronics

LOAD

Output
Under
Test

Where: I

= I

MAX for the respective pin

(A)

= I

MIN for the respective pin

(A)

LOAD

= 1.5 V

= 150-pF typical load-circuit capacitance

(B)

TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

electrical characteristics over recommended operating free-air temperature range (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

No DC load, V

CCIO

= 3.6

CCIO

digital supply current (operating mode)

(8)

No DC load, V

CCIO

= 3.6

CCIO

digital supply current (standby mode)

300

(8)

No DC load, V

CCIO

= 3.6

CCIO

digital supply current (halt mode)

300

(8)

All frequencies, V

CCAD

supply current (operating mode)

3.6 V

All frequencies, V

CCAD

supply current (standby mode)

3.6 V

All frequencies, V

CCAD

supply current (halt mode)

3.6 V

CCP

= 3.6 V read oper-

ation

CCP

= 3.6 V program and

erase

CCP

pump supply current

CCP

= 3.6 V standby mode

operation

(7)

CCP

= 3.6 V halt mode

operation

(7)

Input capacitance

Output capacitance

(8)

I/O pins configured as inputs or outputs with no load. All pulldown inputs

0.2 V. All pullup inputs

CCIO

- 0.2 V.

For these values, see the "electrical characteristics over recommended operating free-air temperature range" table.

All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.

Figure 4. Test Load Circuit

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timing parameter symbology

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

Timing parameter symbols have been created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:

Compaction, CMPCT

Read

CLKOUT

RST

Reset, RST

Erase

SCInRX

ICLK

Interface clock

Slave mode

Master mode

SCC

SCInCLK

OSC, OSCI

OSCIN

SIMO

SPInSIMO

OSCO

OSCOUT

SOMI

SPInSOMI

Program, PROG

SPC

SPInCLK

Ready

SYS

System clock

Read margin 0, RDMRGN0

SCInTX

Read margin 1, RDMRGN1

Lowercase subscripts and their meanings are:

access time

rise time

cycle time (period)

setup time

delay time

transition time

fall time

valid time

hold time

pulse duration (width)

The following additional letters are used with these meanings:

High

Unknown, changing, or don't care level

Low

High impedance

Valid

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external reference resonator/crystal oscillator clock option

External

Clock Signal

(toggling 0 1.8 V)

OSCOUT

OSCIN

(A)

Crystal

OSCOUT

OSCIN

(a)

(b)

TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

The oscillator is enabled by connecting the appropriate fundamental 420 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 5a. The oscillator is a single-stage
inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and
HALT mode. TI strongly encourages each customer to submit samples of the device to the res-
onator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best
tune their resonator/crystal to the microcontroller device for optimum start-up and operation over tempera-
ture/voltage extremes.

An external oscillator source can be used by connecting a 1.8V clock signal to the OSCIN pin and leaving the
OSCOUT pin unconnected (open) as shown in Figure 5b.

The values of C1 and C2 should be provided by the resonator/crystal vendor.

Figure 5. Crystal/Clock Connection

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ZPLL and clock specifications

timing requirements for ZPLL circuits enabled or disabled

switching characteristics over recommended operating conditions for clocks

(1) (2)

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

MIN

MAX

UNIT

(OSC)

Input clock frequency

MHz

c(OSC)

Cycle time, OSCIN

w(OSCIL)

Pulse duration, OSCIN low

w(OSCIH)

Pulse duration, OSCIN high

(OSCRST)

OSC FAIL frequency

(1)

kHz

(1)

Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1)
bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).

PARAMETER

TEST CONDITION

(3)

MIN

MAX

UNIT

Pipeline mode enabled

(SYS)

System clock frequency

(4)

MHz

Pipeline mode disabled

(CONFIG)

System clock frequency - Flash config mode

MHz

Pipeline mode enabled

(ICLK)

Interface clock frequency

MHz

Pipeline mode disabled

Pipeline mode enabled

(ECLK)

External clock output frequency for ECP Module

MHz

Pipeline mode disabled

Pipeline mode enabled

20.8

c(SYS)

Cycle time, system clock

Pipeline mode disabled

41.6

c(CONFIG)

Cycle time, system clock - Flash config mode

41.6

Pipeline mode enabled

c(ICLK)

Cycle time, interface clock

Pipeline mode disabled

41.6

Pipeline mode enabled

c(ECLK)

Cycle time, ECP module external clock output

Pipeline mode disabled

41.6

(1)

(SYS)

= M

(OSC)

/ R, where M = {4 or 8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the

CLKDIVPRE [2:0] bits in the global control register (GLBCTRL.[2:0]) and M is the PLL multiplier determined by the MULT4 bit, also in
the GLBCTRL register (GLBCTRL.3).
f

(SYS)

= f

(OSC)

/ R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.

(ICLK)

= f

(SYS)

/ X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1]

bits in the SYS module.

(2)

(ECLK)

= f

(ICLK)

/ N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module

(3)

Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).

(4)

Flash Vread must be set to 5V to achieve maximum system clock frequency.

www.ti.com

switching characteristics over recommended operating conditions for external clocks

(1) (2) (3)

CLKOUT

ECLK

TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

(see Figure 6 and Figure 7)

NO.

PARAMETER

TEST CONDITION

MIN

MAX

UNIT

SYSCLK or MCLK

(4)

0.5t

c(SYS)

w(COL)

Pulse duration, CLKOUT low

ICLK, X is even or 1

(5)

0.5t

c(ICLK)

ICLK, X is odd and not 1

(5)

0.5t

c(ICLK)

+ 0.5t

c(SYS)

SYSCLK or MCLK

(4)

0.5t

c(SYS)

w(COH)

Pulse duration, CLKOUT high

ICLK, X is even or 1

(5)

0.5t

c(ICLK)

ICLK, X is odd and not 1

(5)

0.5t

c(ICLK)

0.5t

c(SYS)

N is even and X is even or odd

0.5t

c(ECLK)

w(EOL)

Pulse duration, ECLK low

N is odd and X is even

0.5t

c(ECLK)

N is odd and X is odd and not 1

0.5t

c(ECLK)

+ 0.5t

c(SYS)

N is even and X is even or odd

0.5t

c(ECLK)

w(EOH)

Pulse duration, ECLK high

N is odd and X is even

0.5t

c(ECLK)

N is odd and X is odd and not 1

0.5t

c(ECLK)

0.5t

c(SYS)

(1)

X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits in the SYS module.

(2)

N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.

(3)

CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.

(4)

Clock source bits selected as either SYSCLK (CLKCNTL.[6:5] = 11 binary) or MCLK (CLKCNTL.[6:5] = 10 binary).

(5)

Clock source bits selected as ICLK (CLKCNTL.[6:5] = 01 binary).

Figure 6. CLKOUT Timing Diagram

Figure 7. ECLK Timing Diagram

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RST and PORRST timings

timing requirements for PORRST

CCP

CCIO

CCP

CCIO

CCPORH

CCIOPORL

IL(PORRST)

CCIOPORH

CCIOPORL

CCPORL

PORRST

CCIO

CCPORH

CCPORL

IL(PORRST)

switching characteristics over recommended operating conditions for RST

(1)

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

(see Figure 8)

NO.

MIN

MAX

UNIT

CCPORL

low supply level when PORRST must be active during power up

0.6

high supply level when PORRST must remain active during power up

CCPORH

1.5

and become active during power down

CCIOPORL

CCIO

low supply level when PORRST must be active during power up

1.1

CCIO

high supply level when PORRST must remain active during power

CCIOPORH

2.75

up and become active during power down

Low-level input voltage after V

CCIO

> V

CCIOPORH

0.2 V

CCIO

IL(PORRST)

Low-level input voltage of PORRST before V

CCIO

> V

CCIOPORL

0.5

su(PORRST)r

Setup time, PORRST active before V

CCIO

> V

CCIOPORL

during power up

su(VCCIO)r

Setup time, V

CCIO

> V

CCIOPORL

before V

> V

CCPORL

h(PORRST)r

Hold time, PORRST active after V

> V

CCPORH

su(PORRST)f

Setup time, PORRST active before V

CCPORH

during power down

h(PORRST)rio

Hold time, PORRST active after V

> V

CCIOPORH

h(PORRST)d

Hold time, PORRST active after V

< V

CCPORL

su(PORRST)fio

Setup time, PORRST active before V

CCIOPORH

during power down

su(VCCIO)f

Setup time, V

< V

CCPORE

before V

CCIO

< V

CCIOPORL

Figure 8. PORRST Timing Diagram

PARAMETER

MIN

MAX

UNIT

Valid time, RST active after PORRST inactive

4112t

c(OSC)

v(RST)

Valid time, RST active (all others)

c(SYS)

(1)

Specified values do NOT include rise/fall times. For rise and fall timings, see the "switching characteristics for output timings versus load
capacitance" table.

www.ti.com

output timings

switching characteristics for output timings versus load capacitance (C

)

80%

20%

Output

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

(see Figure 10)

PARAMETER

MIN

MAX

UNIT

= 15 pF

0.5

2.50

= 50 pF

1.5

Rise time, CLKOUT, AWD, TDO

= 100 pF

= 150 pF

4.5

12.5

= 15 pF

0.5

2.5

= 50 pF

1.5

Fall time, CLKOUT, AWD, TDO

= 100 pF

= 150 pF

4.5

12.5

= 15 pF

2.5

= 50 pF

Rise time, SPInCLK, SPInSOMI, SPInSIMO

(1)

= 100 pF

= 150 pF

= 15 pF

2.5

= 50 pF

Fall time, RST, SPInCLK, SPInSOMI, SPInSIMO

(1)

= 100 pF

= 150 pF

= 15 pF

2.5

= 50 pF

6.0

Rise time, all other output pins

= 100 pF

= 150 pF

= 15 pF

= 50 pF

8.5

Fall time, all other output pins

= 100 pF

= 150 pF

(1)

n = 1 and 2

Figure 10. CMOS-Level Outputs

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input timings

timing requirements for input timings

(1)

Input

80%

20%

Flash timings

timing requirements for program Flash

(1)

TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

(see Figure 11)

MIN

MAX

UNIT

Input minimum pulse width

c(ICLK)

+ 10

(1)

c(ICLK)

= interface clock cycle time = 1 / f

(ICLK)

Figure 11. CMOS-Level Inputs

MIN

TYP

MAX

UNIT

prog(16-bit)

Half word (16-bit) programming time

200

µs

prog(Total)

256K-byte programming time

(2)

erase(sector)

Sector erase time

wec

Write/erase cycles at T

= 125

100 cycles

(1)

For more detailed information on the Flash core sectors, see the Flash program and erase section of this data sheet.

(2)

The 256K-byte programming times include overhead of state machine.

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SPIn master mode timing parameters

SPIn MASTER MODE EXTERNAL TIMING PARAMETERS

SPInSOMI

SPInSIMO

SPInCLK

(clock polarity = 1)

SPInCLK

(clock polarity = 0)

Master In Data

Must Be Valid

Master Out Data Is Valid

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

(CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)

(1) (2) (3)

(see Figure 12)

NO.

MIN

MAX

UNIT

c(SPC)M

Cycle time, SPInCLK

(4)

100

256t

c(ICLK)

w(SPCH)M

Pulse duration, SPInCLK high (clock polarity = 0)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

(5)

w(SPCL)M

Pulse duration, SPInCLK low (clock polarity = 1)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

w(SPCL)M

Pulse duration, SPInCLK low (clock polarity = 0)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

(5)

w(SPCH)M

Pulse duration, SPInCLK high (clock polarity = 1)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

d(SPCH-SIMO)M

Delay time, SPInCLK high to SPInSIMO valid (clock polarity = 0)

(5)

d(SPCL-SIMO)M

Delay time, SPInCLK low to SPInSIMO valid (clock polarity = 1)

Valid time, SPInSIMO data valid after SPInCLK low

v(SPCL-SIMO)M

c(SPC)M

- 5 - t

(clock polarity = 0)

(5)

Valid time, SPInSIMO data valid after SPInCLK high

v(SPCH-SIMO)M

c(SPC)M

- 5 - t

(clock polarity = 1)

su(SOMI-SPCL)M

Setup time, SPInSOMI before SPInCLK low (clock polarity = 0)

(5)

su(SOMI-SPCH)M

Setup time, SPInSOMI before SPInCLK high (clock polarity = 1)

Valid time, SPInSOMI data valid after SPInCLK low

v(SPCL-SOMI)M

(clock polarity = 0)

(5)

Valid time, SPInSOMI data valid after SPInCLK high

v(SPCH-SOMI)M

(clock polarity = 1)

(1)

The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.

(2)

c(ICLK)

= interface clock cycle time = 1 / f

(ICLK)

(3)

For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

(4)

When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t

c(SPC)M

(PS +1)t

c(ICLK)

100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.

For PS values of 0: t

c(SPC)M

= 2t

c(ICLK)

100 ns.

(5)

The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 0)

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SPIn MASTER MODE EXTERNAL TIMING PARAMETERS

Data Valid

SPInSOMI

SPInSIMO

SPInCLK

(clock polarity = 1)

SPInCLK

(clock polarity = 0)

Master In Data

Must Be Valid

Master Out Data Is Valid

TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

(CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)

(1) (2) (3)

(see Figure 13)

NO.

MIN

MAX

UNIT

c(SPC)M

Cycle time, SPInCLK

(4)

100

256t

c(ICLK)

w(SPCH)M

Pulse duration, SPInCLK high (clock polarity = 0)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

(5)

w(SPCL)M

Pulse duration, SPInCLK low (clock polarity = 1)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

w(SPCL)M

Pulse duration, SPInCLK low (clock polarity = 0)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

(5)

w(SPCH)M

Pulse duration, SPInCLK high (clock polarity = 1)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

Valid time, SPInCLK high after SPInSIMO data valid

v(SIMO-SPCH)M

0.5t

c(SPC)M

- 10

(clock polarity = 0)

(5)

Valid time, SPInCLK low after SPInSIMO data valid

v(SIMO-SPCL)M

0.5t

c(SPC)M

- 10

(clock polarity = 1)

Valid time, SPInSIMO data valid after SPInCLK high

v(SPCH-SIMO)M

c(SPC)M

- 5 - t

(clock polarity = 0)

(5)

Valid time, SPInSIMO data valid after SPInCLK low

v(SPCL-SIMO)M

c(SPC)M

- 5 - t

(clock polarity = 1)

su(SOMI-SPCH)M

Setup time, SPInSOMI before SPInCLK high (clock polarity = 0)

(5)

su(SOMI-SPCL)M

Setup time, SPInSOMI before SPInCLK low (clock polarity = 1)

Valid time, SPInSOMI data valid after SPInCLK high

v(SPCH-SOMI)M

(clock polarity = 0)

(5)

Valid time, SPInSOMI data valid after SPInCLK low

v(SPCL-SOMI)M

(clock polarity = 1)

(1)

The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.

(2)

c(ICLK)

= interface clock cycle time = 1 / f

(ICLK)

(3)

For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

(4)

When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t

c(SPC)M

(PS +1)t

c(ICLK)

100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.

For PS values of 0: t

c(SPC)M

= 2t

c(ICLK)

100 ns.

(5)

The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

Figure 13. SPIn Master Mode External Timing (CLOCK PHASE = 1)

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SPIn SLAVE MODE TIMING PARAMETERS

SPIn SLAVE MODE EXTERNAL TIMING PARAMETERS

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

(CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)

(1) (2) (3) (4)

(see Figure 14)

NO.

MIN

MAX

UNIT

c(SPC)S

Cycle time, SPInCLK

(5)

100

256t

c(ICLK)

Pulse duration, SPInCLK high

w(SPCH)S

0.5t

c(SPC)S

- 0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

(clock polarity = 0)

(6)

Pulse duration, SPInCLK low

w(SPCL)S

0.5t

c(SPC)S

- 0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

(clock polarity = 1)

Pulse duration, SPInCLK low

w(SPCL)S

0.5t

c(SPC)S

- 0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

(clock polarity = 0)

(6)

Pulse duration, SPInCLK high

w(SPCH)S

0.5t

c(SPC)S

- 0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

(clock polarity = 1)

Delay time, SPInCLK high to

d(SPCH-SOMI)S

6 + t

SPInSOMI valid (clock polarity = 0)

(6)

Delay time, SPInCLK low to

d(SPCL-SOMI)S

6 + t

SPInSOMI valid (clock polarity = 1)

Valid time, SPInSOMI data valid after

v(SPCH-SOMI)S

c(SPC)S

- 6 - t

SPInCLK high (clock polarity = 0)

(6)

Valid time, SPInSOMI data valid after

v(SPCL-SOMI)S

c(SPC)S

- 6 - t

SPInCLK low (clock polarity = 1)

Setup time, SPInSIMO before

su(SIMO-SPCL)S

SPInCLK low (clock polarity = 0)

(6)

Setup time, SPInSIMO before

su(SIMO-SPCH)S

SPInCLK high (clock polarity = 1)

Valid time, SPInSIMO data valid after

v(SPCL-SIMO)S

SPInCLK low (clock polarity = 0)

(6)

Valid time, SPInSIMO data valid after

v(SPCH-SIMO)S

SPInCLK high (clock polarity = 1)

(1)

The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.

(2)

If the SPI is in slave mode, the following must be true: t

c(SPC)S

(PS + 1) t

c(ICLK)

, where PS = prescale value set in SPInCTL1.[12:5].

(3)

For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

(4)

c(ICLK)

= interface clock cycle time = 1 /f

(ICLK)

(5)

When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t

c(SPC)S

(PS +1)t

c(ICLK)

100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.

For PS values of 0: t

c(SPC)S

= 2t

c(ICLK)

100 ns.

(6)

The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

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SPIn SLAVE MODE EXTERNAL TIMING PARAMETERS

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

(CLOCK PHASE = 1, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)

(1) (2) (3) (4)

(see Figure 15)

NO.

MIN

MAX

UNIT

c(SPC)S

Cycle time, SPInCLK

(5)

100

256t

c(ICLK)

Pulse duration, SPInCLK high

w(SPCH)S

0.5t

c(SPC)S

- 0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

(clock polarity = 0)

(6)

Pulse duration, SPInCLK low

w(SPCL)S

0.5t

c(SPC)S

- 0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

(clock polarity = 1)

Pulse duration, SPInCLK low

w(SPCL)S

0.5t

c(SPC)S

- 0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

(clock polarity = 0)

(6)

Pulse duration, SPInCLK high

w(SPCH)S

0.5t

c(SPC)S

- 0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

(clock polarity = 1)

Valid time, SPInCLK high after

v(SOMI-SPCH)S

0.5t

c(SPC)S

- 6 - t

SPInSOMI data valid (clock polarity = 0)

(6)

Valid time, SPInCLK low after

v(SOMI-SPCL)S

0.5t

c(SPC)S

- 6 - t

SPInSOMI data valid (clock polarity = 1)

Valid time, SPInSOMI data valid after

v(SPCH-SOMI)S

0.5t

c(SPC)S

- 6 - t

SPInCLK high (clock polarity = 0)

(6)

Valid time, SPInSOMI data valid after

v(SPCL-SOMI)S

0.5t

c(SPC)S

- 6 - t

SPInCLK low (clock polarity = 1)

Setup time, SPInSIMO before SPInCLK

su(SIMO-SPCH)S

high (clock polarity = 0)

(6)

Setup time, SPInSIMO before SPInCLK

su(SIMO-SPCL)S

low (clock polarity = 1)

Valid time, SPInSIMO data valid after

v(SPCH-SIMO)S

SPInCLK high (clock polarity = 0)

(6)

Valid time, SPInSIMO data valid after

v(SPCL-SIMO)S

SPInCLK low (clock polarity = 1)

(1)

The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.

(2)

If the SPI is in slave mode, the following must be true: t

c(SPC)S

(PS + 1) t

c(ICLK)

, where PS = prescale value set in SPInCTL1.[12:5].

(3)

For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

(4)

c(ICLK)

= interface clock cycle time = 1 /f

(ICLK)

(5)

When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t

c(SPC)S

(PS +1)t

c(ICLK)

100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.

For PS values of 0: t

c(SPC)S

= 2t

c(ICLK)

100 ns.

(6)

The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

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SCIn ISOSYNCHRONOUS MODE TIMINGS INTERNAL CLOCK

timing requirements for internal clock SCIn isosynchronous mode

(1) (2) (3)

Data Valid

SCICLK

SCITX

SCIRX

Data Valid

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

(see Figure 16)

(BAUD + 1)

IS EVEN OR BAUD = 0

IS ODD AND BAUD

NO.

UNIT

MIN

MAX

MIN

MAX

c(SCC)

Cycle time, SCInCLK

c(ICLK)

-1) t

c(ICLK)

Pulse duration,

w(SCCL)

0.5t

c(SCC)

- t

0.5t

c(SCC)

+ 5

0.5t

c(SCC)

+ 0.5t

c(ICLK)

- t

0.5t

c(SCC)

+ 0.5t

c(ICLK)

SCInCLK low

Pulse duration,

w(SCCH)

0.5t

c(SCC)

- t

0.5t

c(SCC)

+ 5

0.5t

c(SCC)

- 0.5t

c(ICLK)

- t

0.5t

c(SCC)

- 0.5t

c(ICLK)

SCInCLK high

Delay time, SCInCLK

d(SCCH-TXV)

high to SCInTX valid

Valid time, SCInTX

v(TX)

data after SCInCLK

c(SCC)

- 10

c(SCC)

- 10

low

Setup time, SCInRX

su(RX-SCCL)

c(ICLK)

+ t

+ 20

c(ICLK)

+ t

+ 20

before SCInCLK low

Valid time, SCInRX

v(SCCL-RX)

data after SCInCLK

- t

c(ICLK)

+ t

+ 20

- t

c(ICLK)

+ t

+ 20

low

(1)

BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.

(2)

c(ICLK)

= interface clock cycle time = 1 / f

(ICLK)

(3)

For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

Data transmission/reception characteristics for isosynchronous mode with external clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling
edge.

Figure 16. SCIn Isosynchronous Mode Timing Diagram for Internal Clock

www.ti.com

SCIn isosynchronous mode timings -- external clock

timing requirements for external clock SCIn isosynchronous mode

(1) (2)

Data Valid

SCICLK

SCITX

SCIRX

TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

(see Figure 17)

NO.

MIN

MAX

UNIT

c(SCC)

Cycle time, SCInCLK

(3)

c(ICLK)

w(SCCH)

Pulse duration, SCInCLK high

0.5t

c(SCC)

- 0.25t

c(ICLK)

0.5t

c(SCC)

+ 0.25t

c(ICLK)

w(SCCL)

Pulse duration, SCInCLK low

0.5t

c(SCC)

- 0.25t

c(ICLK)

0.5t

c(SCC)

+ 0.25t

c(ICLK)

d(SCCH-TXV)

Delay time, SCInCLK high to SCInTX valid

c(ICLK)

+ 12 + t

v(TX)

Valid time, SCInTX data after SCInCLK low

c(SCC)

- 10

su(RX-SCCL)

Setup time, SCInRX before SCInCLK low

v(SCCL-RX)

Valid time, SCInRX data after SCInCLK low

c(ICLK)

+ 10

(1)

c(ICLK)

= interface clock cycle time = 1 / f

(ICLK)

(2)

For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

(3)

When driving an external SCInCLK, the following must be true: t

c(SCC)

c(ICLK)

Figure 17. SCIn Isosynchronous Mode Timing Diagram for External Clock

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HIGH-END TIMER (HET) TIMINGS

Minimum PWM output pulse width:

Minimum input pulses we can capture:

standard CAN controller (SCC) mode timings

dynamic characteristics for the CANSTX and CANSRX pins

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution prescale
factor (hr), which is user defined, giving prescale factors of 1 to 64 with a linear increment of codes.

Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK

For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns

The input pulse width must be greater or equal to the low resolution clock period (LRP), i.e., the HET loop (the
HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale factor (lr), which
is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.

Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK

For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns

NOTE:

Once the input pulse width is greater than LRP, the resolution of the measurement is
still HRP. (That is, the captured value gives the number of HRP clocks inside the
pulse.)

Abbreviations:

hr = HET high resolution divide rate = 1, 2, 3,...63, 64

lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32

High resolution clock period = HRP = hr/SYSCLK

Loop resolution clock period = LRP = hr*lr/SYSCLK

PARAMETER

MIN

MAX

UNIT

(CANSTX)

Delay time, transmit shift register to CANSTX pin

(1)

(CANSRX)

Delay time, CANSRX pin to receive shift register

(1)

These values do not include the rise/fall times of the output buffer.

www.ti.com

MULTI-BUFFERED A-TO-D CONVERTER (MibADC)

TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry. This power bus
enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could be
present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with
respect to ADREFLO unless otherwise noted.

Resolution

10 bits (1024 values)

Monotonic

Assured

Output conversion code

00h to 3FFh [00 for VAI

REFLO

; 3FF for VAI

REFHI

]

Table 14. MibADC RECOMMENDED OPERATING CONDITIONS

(1)

MIN

MAX

UNIT

REFHI

A-to-D high-voltage reference source

SSAD

CCAD

REFLO

A-to-D low-voltage reference source

SSAD

CCAD

Analog input voltage

SSAD

- 0.3

CCAD

+ 0.3

Analog input clamp current

(2)

AIC

-2

< V

SSAD

- 0.3 or V

> V

CCAD

+ 0.3)

(1)

For V

CCAD

and V

SSAD

recommended operating conditions, see the "device recommended operating conditions" table.

(2)

Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.

Table 15. OPERATING CHARACTERISTICS OVER FULL RANGES OF RECOMMENDED OPERATING

CONDITIONS

(1) (2)

PARAMETER

DESCRIPTION/CONDITIONS

MIN

TYP

MAX UNIT

Analog input resistance

See Figure 18.

250

500

Conversion

Analog input capacitance

See Figure 18.

Sampling

AIL

Analog input leakage current

See Figure 18.

-1

µA

ADREFHI

REFHI

input current

REFHI

= 3.6 V, AD

REFLO

= V

SSAD

Conversion range over which specified

REFHI

- AD

REFLO

3.6

accuracy is maintained

Difference between the actual step width and the ideal

DNL

Differential nonlinearity error

LSB

value after offset correction. See Figure 19.

Maximum deviation from the best straight line through
the MibADC. MibADC transfer characteristics, exclud-

INL

Integral nonlinearity error

LSB

ing the quantization error after offset correction. See
Figure 20.

Maximum value of the difference between an analog

TOT

Total error/Absolute accuracy

LSB

value and the ideal midstep value. See Figure 21.

(1)

CCIO

= V

CCAD

= AD

REFHI

(2)

1 LSB = (AD

REFHI

- AD

REFLO

)/ 2

for the MibADC

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Parasitic
Capacitance

src

MibADC

Input Pin

Sample
Capacitor

leak

Sample Switch

External

Analog Input Value (LSB)

Digital Output Code

Differential
Linearity Error (1/2 LSB)

1 LSB

Differential Linearity
Error ( 1/2 LSB)

1 LSB

0 ... 101

0 ... 100

0 ... 011

0 ... 010

0 ... 001

0 ... 000

0 ... 110

TMS470R1A256

16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

Figure 18. MibADC Input Equivalent Circuit

Table 16. MULTI-BUFFER ADC TIMING REQUIREMENTS

MIN

MAX

UNIT

c(ADCLK)

Cycle time, MibADC clock

0.05

µs

d(SH)

Delay time, sample and hold time

µs

d(C)

Delay time, conversion time

0.55

µs

d(SHC)

(1)

Delay time, total sample/hold and conversion time

1.55

µs

(1)

This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors for more
detail; see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).

The differential nonlinearity error shown in Figure 19 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.

1 LSB = (AD

REFHI

- AD

REFLO

)/2

Figure 19. Differential Nonlinearity (DNL)

www.ti.com

At Transition
011/100
( 1/2 LSB)

End-Point Lin. Error

At Transition
001/010 ( 1/4 LSB)

Ideal

Transition

Actual

Transition

0 ... 101

0 ... 100

0 ... 011

0 ... 010

0 ... 111

0 ... 110

Digital Output Code

0 ... 001

0 ... 000

Analog Input Value (LSB)

0 ... 101

0 ... 100

0 ... 011

0 ... 010

0 ... 001

0 ... 000

0 ... 111

0 ... 110

Analog Input Value (LSB)

Digital Output Code

Total Error
At Step
0 ... 001 ( 1/2 LSB)

Total Error
At Step 0 ... 101
( 1 1/4 LSB)

TMS470R1A256
16/32-Bit RISC Flash Microcontroller

SPNS100 NOVEMBER 2004

The integral nonlinearity error shown in Figure 20 (sometimes referred to as linearity error) is the deviation of the
values on the actual transfer function from a straight line.

1 LSB = (AD

REFHI

- AD

REFLO

)/2

Figure 20. Integral Nonlinearity (INL) Error

The absolute accuracy or total error of an MibADC as shown in Figure 21 is the maximum value of the difference
between an analog value and the ideal midstep value.

1 LSB = (AD

REFHI

- AD

REFLO

)/2

Figure 21. Absolute Accuracy (Total) Error

PACKAGING INFORMATION

Orderable Device

Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

TMS470R1A256PZ

ACTIVE

LQFP

100

TBD

Call TI

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco

Plan

The

planned

eco-friendly

classification:

Pb-Free

(RoHS)

Green

(RoHS

Sb/Br)

please

check

http://www.ti.com/productcontent

for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com

30-Mar-2005

Addendum-Page 1

IMPORTANT NOTICE

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