Document Outline
- WM8740
- 24-bit, High Performance 192kHz Stereo DAC
- Advanced Information, July 2000, Rev 1.7
- DESCRIPTION
- FEATURES
- APPLICATIONS
- BLOCK DIAGRAM
- PIN CONFIGURATION
- ORDERING INFORMATION
- PIN DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- DEVICE DESCRIPTION
- SYSTEM CLOCK
- AUDIO DATA INTERFACE
- NORMAL SAMPLE RATE
- 8 X FS INPUT SAMPLE RATE
- MODES OF OPERATION
- HARDWARE CONTROL MODES
- SOFTWARE CONTROL INTERFACE
- REGISTER MAP
- MUTE MODES
- FILTER RESPONSES
- RECOMMENDED EXTERNAL COMPONENTS
- RECOMMENDED EXTERNAL COMPONENTS VALUES
- SUGGESTED DIFFERENTIAL OUTPUT FILTER CIRCUIT
- PACKAGE DIMENSIONS
WM8740
24-bit, High Performance 192kHz Stereo DAC
Advanced Information, July 2000, Rev 1.7
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk
Advanced Information data sheets contain
preliminary data on new products in the
preproduction phase of development.
Supplementary data will be published at a
later date.
2000 Wolfson Microelectronics Ltd
.
DESCRIPTION
The WM8740 is a very high performance stereo DAC
designed for audio applications such as CD, DVD, home
theatre systems, set top boxes and digital TV. The WM8740
supports data input word lengths from 16 to 24-bits and
sampling rates up to 192kHz. The WM8740 consists of a
serial interface port, digital interpolation filter, multi-bit sigma
delta modulator and stereo DAC in a small 28-pin SSOP
package. The WM8740 also includes a digitally controllable
mute and attenuator function on each channel.
The internal digital filter has two selectable roll-off
characteristics. A sharp or slow roll-off can be selected
dependent on application requirements. Additionally, the
internal digital filter can be by-passed and the WM8740
used with an external digital filter.
The WM8740 supports two connection schemes for audio
DAC control. The SPI-compatible serial control port
provides access to a wide range of features including on-
chip mute, attenuation and phase reversal. A hardware
controllable interface is also available.
FEATURES
120dB SNR (`A' weighted mono @48kHz), THD+N: -104dB
@ FS
117dB SNR (`A' weighted stereo @48kHz), THD+N: -104dB
@ FS
Sampling frequency: 8kHz to 192kHz
Selectable digital filter roll-off
Optional interface to industry standard external filters
Differential mono mode needing no glue logic
Input data word: 16 to 24-bit
Hardware or SPI compatible serial port control modes:
Hardware mode: mute, de-emphasis, audio format
control
Serial mode: mute, de-emphasis, attenuation (256
steps), phase reversal
Fully differential voltage outputs
APPLICATIONS
CD, DVD audio
Home theatre systems
Professional audio systems
BLOCK DIAGRAM
SERIAL
INTERFACE
MUTE/
ATTEN
CONTROL INTERFACE
BCKIN (3)
(12) VOUTRP
SIGMA
DELTA
MODULATOR
LRCIN (1)
DIN (2)
AGNDR
(10)
AVDDR
(9)
MUTE/
ATTEN
SIGMA
DELTA
MODULATOR
DIGITAL
FILTERS
MODE8X
(4)
MUX
(8)
DVDD
(15)
AVDD
(14)
AGND
(7)
DGND
MUTEB
(25)
DIFFHW
(6)
MD/DM0
(26)
MC/DM1
(27)
ML/I2S
(28)
MODE
(24)
CSBIWO
(23)
RSTB
(22)
ZERO
(21)
LOW
PASS
FILTER
LOW
PASS
FILTER
(11) VMIDR
MUX
(18) VMIDL
RIGHT
DAC
LEFT
DAC
(19)
AGNDL
(20)
AVDDL
.
WM8740
SCLK (5)
(16) VOUTLN
(13) VOUTRN
(17) VOUTLP
WM8740
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
2
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
XWM8740EDS
-25
to +85
C
28-pin SSOP
16
15
14
20
19
18
17
5
6
7
1
2
3
4
13
12
11
8
9
10
BCKIN
VOUTRN
VOUTLN
LRCIN
DIN
ZERO
MUTEB
MODE
RSTB
CSBIWO
MD/DM0
MC/DM1
ML/I2S
VMIDR
VMIDL
SCLK
DIFFHW
MODE8X
AGNDR
AGNDL
AVDDR
DVDD
AVDDL
DGND
21
22
23
24
25
26
27
28
VOUTRP
AGND
VOUTLP
AVDD
PIN DESCRIPTION
PIN
NAME
TYPE
DESCRIPTION
1
LRCIN
Digital input
Sample rate clock input.
2
DIN
Digital input
Audio data serial input (except in 8XMODE when it is DINL).
3
BCKIN
Digital input
Audio data bit clock input .
4
MODE8X
Digital input
Internal pull-down, active high, 8 x fs mode.
5
SCLK
Digital input
System clock input.
6
DIFFHW
Digital input
Internal pull-down, active high, differential mono mode.
7
DGND
Supply
Digital ground supply.
8
DVDD
Supply
Digital positive supply.
9
AVDDR
Supply
Analogue positive supply.
10
AGNDR
Supply
Analogue ground supply.
11
VMIDR
Analogue output
Mid rail right channel.
12
VOUTRP
Analogue output
Right channel DAC output positive.
13
VOUTRN
Analogue output
Right channel DAC output negative.
14
AGND
Supply
Analogue ground supply.
15
AVDD
Supply
Analogue positive supply.
16
VOUTLN
Analogue output
Left channel DAC output negative.
17
VOUTLP
Analogue output
Left channel DAC output positive.
18
VMIDL
Analogue output
Mid rail left channel.
19
AGNDL
Supply
Analogue ground supply.
20
AVDDL
Supply
Analogue positive supply.
21
ZERO
Digital output
Infinite zero detect active low. Open drain type output with active pull-down.
22
RSTB
Digital input
Reset input active low. Internal pull-up.
Advanced Information
WM8740
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
3
PIN
NAME
TYPE
DESCRIPTION
Hardware Mode
Normal Mode
Differential Mode
8X Mode
Software
Mode
23
CSBIWO
Digital input
Internal pull-down
Wordlength:
Low for 16-bit data.
High for 20-bit
(normal) or 24-bit
I
2
S data.
Wordlength:
Low for 16-bit data.
High for 20-bit
(normal) or 24-bit
I
2
S data.
Wordlength:
Low for 20-bit data.
High for 24-bit data.
Low for
serial
interface
operation.
24
MODE
Digital input
Internal pull-up
Low for hardware
mode.
Low for left
mono mode.
High for right
mono mode
DINR
High for
software
mode.
25
MUTEB
Digital input
Internal pull-up
Low to soft mute.
High for normal
operation.
Low to soft mute.
High for normal
operation.
Low to soft mute.
High for normal
operation.
Low to
soft mute.
High for
normal
operation.
26
MD/DM0
Digital input
Internal pull-up
De-emphasis mode
select bit 0.
Low for no
de-emphasis.
High for 44.1kHz
de-emphasis.
LRP LRCLK
polarity select.
Control serial
interface
data signal.
27
MC/DM1
Digital input
Internal pull-up
De-emphasis mode
select bit 1.
Low for normal filter
operation.
High for filter slow
roll-off.
Unused.
Leave unconnected.
Control serial
interface
clock signal.
28
ML/I2S
Digital input
Internal pull-up
Audio serial format:
Low right justified.
High I
2
S.
Audio serial format:
Low right justified.
High I
2
S.
Input data format:
Low right justified.
High left justified.
Control serial
interface
load signal.
Note:
Digital input pins have Schmitt trigger input buffers.
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
CONDITION
MIN
MAX
Supply voltage
-0.3V
+7.0V
Reference input
VDD + 0.3V
Operating temperature range, T
A
-25
C
+85
C
Storage temperature
-65
C
+150
C
Package body temperature (soldering, 10 seconds)
+240
C
Package body temperature (soldering, 2 minutes)
+183
C
WM8740
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
4
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital supply range
DVDD
-10%
3.3 to 5
+10%
V
Analogue supply range
AVDD
-10%
3.3 to 5
+10%
V
Ground
AGND, DGND
0
V
Difference DGND to AGND
-0.3
0
+0.3
V
Analogue supply current
AVDD = 5V
15
mA
Digital supply current
DVDD = 5V
15
mA
Analogue supply current
AVDD = 3.3V
15
mA
Digital supply current
DVDD = 3.3V
9
mA
ELECTRICAL CHARACTERISTICS
TEST CONDITIONS
AVDD, DVDD = 5V, AGND, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC Circuit Specifications
Mono fs @ 48kHz
120
dB
Stereo fs @ 48kHz
110
117
dB
SNR
(See Note 1)
Stereo fs @ 96kHz
116
dB
Mono 0dB
-104
dB
THD (full-scale)
(See Note 2)
Stereo 0dB
-95
-104
dB
THD+N (Dynamic range)
(See Note 2)
-60dB
117
dB
Filter Characteristics (Sharp Roll-off)
Passband
0.0012 dB
0.4535fs
dB
Stopband
-3dB
0.491fs
Passband ripple
0.0012
dB
Stopband attenuation
f > 0.5465fs
-82
dB
Delay time
30/fs
s
Filter Characteristics (Slow Roll-off)
Passband
0.001dB
0.274fs
Stopband
-3dB
0.459fs
Passband ripple
0.001
dB
Stopband attenuation
f > 0.732fs
-82
dB
Delay time
9/fs
s
Internal Analogue Filter
Bandwidth
-3dB
195
kHz
Passband edge response
20kHz
-0.043
dB
Digital Logic Levels
Input LOW level
V
IL
0.8
Input HIGH level
V
IH
2.0
V
Output LOW level
V
OL
I
OL
= 2mA
AVSS + 0.3V
V
Output HIGH level
V
OH
I
OH
= 2mA
AVDD - 0.3V
Advanced Information
WM8740
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
5
TEST CONDITIONS
AVDD, DVDD = 5V, AGND, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Output Levels
Into 10kohm, full scale 0dB,
(5V supply)
2
V
RMS
Output level differential
Into 10kohm, full scale 0dB,
(3.3V supply)
1.32
V
RMS
To midrail or AC coupled
(5V supply)
1
kohms
Minimum resistance load
To midrail or AC coupled
(3.3V supply)
600
ohms
Maximum capacitance load
5V or 3.3V
100
pF
Output DC level
AVDD/2
V
Reference Levels
Potential divider resistance
AVDD to VMIDL/VMIDR and
VMIDL/VMIDR to AGND
10
kohms
Voltage at VMIDL/VMIDR
AVDD/2
POR
POR threshold
2.2
V
Notes: 1.
Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A'
weighted over a 20Hz to 20kHz bandwidth.
2.
All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher
THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low
pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.
BCKIN
DIN
LRCIN
t
BCH
t
BCL
t
BL
t
LB
t
BCY
t
DS
t
DH
Figure 1 Audio Data Input Timing
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN pulse cycle time
t
BCY
100
ns
BCKIN pulse width high
t
BCH
40
ns
BCKIN pulse width low
t
BCL
40
ns
BCKIN rising edge to
LRCIN edge
t
BL
20
ns
LRCIN rising edge to
BCKIN rising edge
t
LB
20
ns
WM8740
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
6
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIN setup time
t
DS
20
ns
DIN hold time
t
DH
20
ns
SCKI
t
SCKIL
t
SCKIH
t
SCKY
Figure 2 System Clock Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
System clock pulse width high
t
SCKIH
10
ns
System clock pulse width low
t
SCKIL
10
ns
System clock cycle time
t
SCKY
27
ns
ML/I2S
MC/DM1
MD/DM0
t
MHH
t
MLD
t
MCY
t
MCH
t
MCL
t
MDS
t
MDH
LSB
t
MLS
t
MLL
Figure 3 Program Register Input Timing SPI Compatible Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
MC/DM1 pulse cycle time
t
MCY
80
ns
MC/DM1 pulse width low
t
MCL
32
ns
MD/DM0 pulse width high
t
MCH
32
ns
MD/DM0 set-up time
t
MDS
10
ns
MC/DM1 hold time
t
MDH
10
ns
ML/I2S pulse width low
t
MLL
10
ns
ML/I2S pulse width high
t
MHH
10
ns
ML/I2S set-up time
t
MLS
10
ns
ML/I2S delay from MC
t
MLD
10
ns
Advanced Information
WM8740
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
7
DEVICE DESCRIPTION
The WM8740 is a high performance 128fs oversampling rate stereo DAC employing a novel 64 level
sigma delta DAC design which provides optimised signal-to-noise performance and clock jitter
tolerance. It is ideally suited to high quality audio applications such as CD, DVD-audio, home theatre
receivers and professional mixing consoles. The WM8740 supports sample rates from 8ks/s to
192ks/s.
The control functions of the WM8740 are either pin selected (hardware mode) or programmed via the
serial interface (software mode). Control functions that are available include: data input word length
and format selection (16-24 bits: I
2
S, left justified or right justified): de-emphasis sample rate
selection (48kHz, 44.1kHz and 32kHz); differential output modes; a software or hardware mute and
independently digitally controllable attenuation on both channels.
The digital filtering may be bypassed entirely by selecting MODE8X. Data is then input directly to the
DAC, bypassing the digital filters. Left and right channels are input separately, using the MODE pin
as the right channel input. This mode allows the use of alternative digital filters, such as the Pacific
Microsonics PMD100 HDCD filter.
In addition to the normal stereo operating mode the WM8740 may also be used in dual differential
mode with either the left or right channel (selectable) being output dual differentially. Two WM8740s
can then be used in parallel to implement a stereo channel, each supporting a single channel
differentially. Note that this mode uses 2 pairs of differential outputs for each channel the benefit is
SNR improved by 3dB. This mode is available in both software and hardware modes and may also
be used in conjunction with MODE8X.
SYSTEM CLOCK
Sample rates from 8ks/s up to 96ks/s are available, and automatically selected, with a system clock
of 256fs or 384fs. In addition a system clock of 128fs or 192fs may be used, with sample rates up to
192ks/s. With a 128fs or 192fs system clock 64x oversampling mode operation is automatically
selected and the first stage of the digital filter is bypassed.
WM8740 has an asynchronous monitor circuit, which in the event of removal of the master system
clock, resets the digital filters and analogue circuits, muting the output. Re-application of the system
clock re-starts the filters from an intitialised state. Control registers are not reset under this condition.
The WM8740 is tolerant of asynchronous bit clock jitter. The internal signal processing
resynchronises to the external LRCIN once the phase difference between bit clock and the system
clock exceeds half an LRCIN period. During this re-synch period the interpolating filters will either
miss or repeat an audio sample, minimising the audible effects of the operation. Table 1 shows the
typical system clock frequency inputs for the WM8740.
SYSTEM CLOCK FREQUENCY (MHZ)
SAMPLING
RATE
(LRCIN)
128fs
192fs
256fs
384fs
32kHz
4.096
6.144
8.192
12.288
44.1kHz
5.6448
8.467
11.2896
16.9340
48kHz
6.114
9.216
12.288
18.432
96kHz
12.288
18.432
24.576
36.864
192kHz
24.576
36.864
Unavailable
Unavailable
Table 1 System Clock Frequencies Versus Sampling Rate
AUDIO DATA INTERFACE
Data may be input at a rate corresponding to the system clock having a rate of 256fs or 384fs, in
which case an oversampling ratio of 128x is selected. Alternatively a rate of 128fs or 192fs may be
used, in which case the first filter stage is bypassed and an oversampling ratio of 64x results. Finally,
in MODE8X, data may be input at 8x the normal rate, in which case separate input pins are used to
input the two stereo channels of data (unless DIFFHW mode and MODE8X are both selected, in
which case only a mono channel is converted differentially). In MODE8X all filter stages are by-
passed, prior to the sigma delta modulator. Data is input MSB first in all modes.
WM8740
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
8
NORMAL SAMPLE RATE
In normal mode, the data is input serially on one pin for both left and right channels.
Data can be "right justified" meaning that the last 16, 20 or 24 bits (depending on chosen PCM word
length) that were clocked in prior to the transition on LRCIN are valid.
Alternatively data can be "left justified" (20 and 24-bit PCM data only), where the bits are clocked in
as the first 20 or 24 bits after a transition on LRCIN.
For the three I
2
S modes supported (16-bit, 20-bit and 24-bit PCM data), data is clocked "left justified"
except with one additional preceding clock cycle.
LRCIN (PIN 1)
16-BIT RIGHT
JUSTIFIED
DIN (PIN 2)
20-BIT RIGHT
JUSTIFIED
DIN (PIN 2)
24-BIT RIGHT
JUSTIFIED
DIN (PIN 2)
24-BIT LEFT
JUSTIFIED
DIN (PIN 2)
20-BIT LEFT
JUSTIFIED
DIN (PIN 2)
BCKIN (PIN 3)
B2
B1
B0
B2
B1
B0
B2 B1
B0
B0
B0
B23 B22 B21
B19 B18 B17
B23 B22 B21 B20 B19
B4
B3
B2
B1
B0
B0
B19 B18 B17
B15
B2
B1
B0
B2
B1
B0
B2
B1
B0
B23 B22 B21
B19 B18 B17
B0
B4
B3
B2
B1
B0
B23 B22 B21 B20 B19
B19 B18 B17
B15
B2
B1
B0
B2
B1
B0
B2
B1
B0
RIGHT
LEFT
1/fs
LRCIN (PIN 1)
16-BIT I
2
S
DIN (PIN 2)
24-BIT I
2
S
DIN (PIN 2)
20-BIT I
2
S
DIN (PIN 2)
BCKIN (PIN 3)
B2
B1
B0
B0
B2
B1
B0
B3
B2
B1
RIGHT
LEFT
B15
B23
B19
B6
B5
B4
B2
B1
B0
B3
B2
B1
B15
B23
B19
B6
B5
B4
B0
B2
B1
B0
B23
B19
B15
Figure 4 Audio Data Input Format
Advanced Information
WM8740
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
9
8 X FS INPUT SAMPLE RATE
Due to the higher speed of the interface in 8 x fs mode, audio data is input on two pins. The MODE
pin (pin 24) is used as the second input for the right channel data and left data is input on DIN (pin2).
In this mode, software control of the device is not available. The data can be input in two formats, left
or right justified, selectable by ML/I2S and two word lengths (20 or 24 bit), selectable by CSBIWO. In
both modes the data is always clocked in MSB first.
For left justified data the word start is marked by the falling edge of LRCIN. The data is clocked in on
the next 20/24 BCKIN rising edges. This format is compatible with devices such as the PMD100.
For right justified the data is justified to the rising edge of LRCIN and the data is clocked in on the
preceding 20/24 BCKIN rising edges before the LRCIN rising edge. This format is compatible with
devices such as the DF1704 or SM5842.
In both modes the polarity of LRCIN can be switched using MD/DM0.
Differential hardware mode can be used in conjunction with 8fs mode by setting the DIFFHW
pin high. In differential 8fs mode the data is input on DIN and output differentially. MODE is
unused and must be tied low.
LRCIN (PIN 1)
LEFT AUDIO
DATA DIN
(PIN 2)
RIGHT AUDIO
DATA MODE
(PIN 24)
BCKIN (PIN 3)
1/8fs
B19
B22
B23
B20
B21
B2
B1
B0
B23
B22
B21
B20
B19
B22
B23
B20
B21
B2
B1
B0
B23
B22
B21
B20
LRCIN (PIN 1)
LEFT AUDIO
DATA DIN
(PIN 2)
RIGHT AUDIO
DATA MODE
(PIN 24)
BCKIN (PIN 3)
1/8fs
B19
B22
B23
B20
B21
B2
B1
B0
B19
B22
B23
B20
B21
B2
B1
B0
Figure 5 Audio Data Input Format (8 x fs Operation)
MODES OF OPERATION
Control of the various modes of operation is either by software control over the serial interface, or
by hard-wired pin control. Selection of software or hardware mode is via MODE pin. The following
functions may be controlled either via the serial control interface or by hard wiring of the
appropriate pins.
HARDWARE CONTROL MODES
When the MODE pin is held `low' the following hardware modes of operation are available. In
Hardware differential mode or 8X mode some of these modes/control words are altered or
unavailable.
WM8740
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
10
DE-EMPHASIS CONTROL
MDDM1
PIN 27
MCDMO
PIN 26
DE-EMPHASIS
L
L
Off
L
H
48kHz
H
L
44.1kHz
H
H
32kHz
Table 2 De-Emphasis Control
AUDIO INPUT FORMAT
ML/I2S
PIN 28
CSBIWO
PIN 23
DATA FORMAT
L
L
16 bit normal right
justified
L
H
20 bit normal right
justified
H
L
16 bit I
2
S
H
H
24 bit I
2
S
Table 3 Audio Input Format
SOFT MUTE
MUTEB
PIN 25
FUNCTION
L
Mute On (no output)
H
Mute Off (normal operation)
Table 4 Soft Mute
A logic low on the MUTEB pin will cause the attenuation to ramp to infinite attenuation at a rate of
128/fs seconds per 0.5dB step. Setting MUTEB high will cause the attenuation to ramp back to its
previous value.
SOFTWARE CONTROL INTERFACE
The WM8740 can be controlled using a 3-wire serial interface. MD/DM0 (pin 26) is used for the
program data, MC/DM1 (pin 22) is used to clock in the program data and ML/I2S (pin 28) is use to
latch in the program data. The 3-wire interface protocol is shown in Figure 6. CSB/IWO (pin 23) must
be low when writing.
ML/I2S (PIN 28)
MC/DM1 (PIN 27)
MD/DM0 (PIN 26)
B15
B14
B13
B2
B1
B0
Figure 6 Three-Wire Serial Interface
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WM8740
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
11
REGISTER MAP
WM8740 controls the special functions using 4 program registers, which are 16-bits long. These
registers are all loaded through input pin MD/DM0. After the 16 data bits are clocked in, ML/I2S is
used to latch in the data to the appropriate register. Table 5 shows the complete mapping of the 4
registers. Note that in hardware differential mode and 8X modes, software control is not available.
The hardware differential mode (Diff[1:0]) clock loss detector disable (CDD) can only be accessed by
writing to M2[8:5] with the pattern 1111. Register M4 is then accessible by setting A[2:0] to 110.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
M0
-
-
-
-
A2 (0) A1(0)
A0(0)
LDL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
M1
-
-
-
-
A2(0)
A1(0)
A0(1)
LDR
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
M2
-
-
-
-
A2(0)
A1(1)
A0(0)
-
-
-
-
IW1
IW0
OPE
DEM
MUT
M3
-
-
-
-
A2(0)
A1(1)
A0(1)
IZD
SF1
SF0
CK0
REV
SR0
ATC
LRP
I
2
S
M4
-
-
-
-
A2(1)
A1(1)
A0(0)
-
-
CDD
DIFF1 DIFF0
-
-
-
-
Table 5 Mapping of Program Registers
REGISTER
BITS
NAME
DEFAULT
DESCRIPTION
[7:0]
AL[7:0]
FF
Attenuation data for left channel.
0
8
LDL
0
Attenuation data load control for left channel.
[7:0]
AR[7:0]
FF
Attenuation data for right channel.
1
8
LDR
0
Attenuation data load control for right channel.
0
MUT
0
Left and right DACs soft mute control.
1
DEM
0
De-emphasis control.
2
OPE
0
Left and right DACs operation control.
2
[4:3]
IW[1:0]
0
Input audio data bit select.
0
I2S
0
Audio data format select.
1
LRP
0
Polarity of LRCIN select.
2
ATC
0
Attenuator control.
3
SR0
0
Digital filter slow roll-off select.
4
REV
0
Output phase reverse.
5
CKO
0
CLKO frequency select.
[7:6]
SF[1:0]
0
Sampling rate select.
3
8
IZD
0
Infinite zero detection circuit control.
[5:4]
DIFF
0
Differential output mode.
4
6
CDD
0
Clock loss detector disable.
Table 6 Register Bit Descriptions
DAC OUTPUT ATTENUATION
The level of attenuation for eight bit code X, is given by:
0.5
(X - 255) dB, 1
X
255
-
dB (mute),
X = 0
Bit 8 in register 0 (LDL) is used to control the loading of attenuation data in B[7:0]. When LDL is set
to 0, attenuation data will be loaded into AL[7:0], but it will not affect the filter attenuation. LDR in
register 1 has the same function for right channel attenuation. Only when LDL or LDR is set to '1' will
the filter attenuation be updated. This permits left and right channel attenuation to be updated
simultaneously.
Attenuation level is controlled by AL[7:0] (left channel) or AR[7:0] (right channel). Attenuation levels
are given in Table 7.
WM8740
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WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
12
X[7:0]
ATTENUATION LEVEL
00(hex)
-
dB (mute)
01(hex)
-127.0dB
:
:
:
:
FD(hex)
-1.0dB
FE(hex)
-0.5dB
FF(hex)
0.0dB
Table 7 Attenuation Control Level
Bit 2 in Reg3 is used to control the attenuator (ATC). When ATC is "high", the attenuation data
loaded in program register 0 is used for both the left and the right channels. When ATC is low, the
attenuation data for each register is applied separately to left and right channels.
SOFT MUTE
MUT
(REG2, B0)
L
Soft Mute off (normal operation)
H
Soft Mute on (no output)
Table 8 Soft Mute
Setting MUT causes the attenuation to ramp from the current value down to 00. The values held in
the attenuation registers are unchanged. When MUT is reset the attenuation will ramp back up to the
previous value. The ramp rate is 128/fs s/0.5dB step.
DIGITAL DE-EMPHASIS
DEM
(REG2, B1)
L
De-emphasis off
H
De-emphasis on
Table 9 Digital De-Emphasis
DAC OPERATION ENABLE
OPE
(REG2,B2)
L
Normal operation
H
DAC output forced to bipolar zero,
irrespective of input data.
Table 10 DAC Operation Enable
AUDIO DATA INPUT FORMAT
I2S
(REG3, B0)
IW1
(REG2, B4)
IW0
(REG2, B3)
AUDIO INTERFACE
0
0
0
16-bit standard right justified
0
0
1
20-bit standard right justified
0
1
0
24-bit standard right justified
0
1
1
24-bit left justified (MSB first)
1
0
0
16-bit I
2
S
1
0
1
24-bit I
2
S
1
1
0
20-bit I
2
S
1
1
1
20-bit left justified (MSB first)
Table 11 Audio Data Input Format
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WM8740
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
13
POLARITY OF LR INPUT CLOCK
The left channel data for a particular sample instant is always input first, then the right channel data.
LRP
(REG3, B1)
L
LR High left channel
LR Low right channel
H
LR Low left channel
LR High right channel
Table 12 Polarity of LR Input Clock
INDIVIDUAL OR COMMON ATTENUTATION CONTROL
ATC
(REG3, B2)
L
Individual control
H
Common control from Reg0
Table 13 Individual or Common Attenuation Control
DIGITAL FILTER ROLL-OFF SELECTION
SRO
(REG3, B3)
L
Sharp
H
Slow
Table 14 Digital Filter Roll-Off Selection
ANALOGUE OUTPUT POLARITY REVERSAL
REV
(REG3, B4)
L
Normal
H
Inverted
Table 15 Analogue Output Polarity Reversal
CLKO OUTPUT FREQUENCY
CKO
(REG3, B5)
L
XTI
H
XTI/2
Table 16 CLKO Output Frequency
DE-EMPHASIS SAMPLE RATE
SF1
(REG3, B7)
SF0
(REG3, B6)
SAMPLE RATE
0
0
No de-emphasis
0
1
48kHz
1
0
44.1kHz
1
1
32kHz
Table 17 De-Emphasis Sample Rate
INFINITE ZERO DETECT
IZD
(REG3, B8)
L
Zero detect mute off
H
Zero detect mute on
Table 18 Infinite Zero Detect
WM8740
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
14
DIFFERENTIAL MONO MODE
Using bits 4 and 5, the differential output mode may be selected to be one of normal stereo, reversed
stereo, mono left or mono right, as shown in Table 19.
DIFF[1:0]
B[4:5])
DIFFERENTIAL OUTPUT MODE
00
Stereo
01
Stereo reverse.
10
Mono left differential outputs.
VOUTL is left channel.
VOUTR is the negative of left channel.
11
Mono right differential outputs.
VOUTL is the negative right channel.
VOUTR is right channel.
Table 19 Differential Output Modes
Using these controls a pair of WM8740 devices may be used to build a dual differential stereo
implementation with higher performance and differential output.
Note: DIFFHW mode pin may be used to achieve the same result by hardware means.
CLOCK LOSS DETECTOR DISABLE
CDD (REG4, B6)
L
Clock loss detector on
R
Clock loss detector off
Table 20 Clock Loss Detector Disable
When the system clock is inactive for approximately 100
s, the clock loss detector circuit detects the
loss of clock and the analogue circuitry is forced into a mute condition and the digital filters reset.
Setting the CDD bit disables this behaviour.
MUTE MODES
The device has various mute modes.
ANALOGUE
DIGITAL FILTER
ANRES
ANMUTE
Reg bit OPE = `1'
Unaffected
Asserted
MUTEB pin
Gain ramped to zero
On release volume ramps
to previous value
Asserted when
gain = 0
AUTOMUTE
(detect 1024 zero
input samples)
Automute has no effect on digital
filters
Asserted after
1024 zero input
samples if IZD = 1
Reg bit MUT
As MUTEB pin
As MUTEB pin
Gain = 00
(left & right)
Gain = -
dB
Asserted
RAM initialise
Gain initialised to 0dB
Asserted
Loss of system
clock
Not running (no clock). On clock
restart, filters initialised, RAM
initialised. Registers unchanged
Asserted
Asserted
No LRCLK or invalid
SCLK/LRCLK ratio
Filters initialised, RAM initialised.
Registers unchanged
Asserted
Asserted
RB
Reset gain initialised to 0dB
Asserted
Asserted
Power-on reset
Reset
Asserted
Asserted
Table 21 Mute Modes
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WM8740
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AI Rev 1.7 July 2000
15
ANRES is the reset to the switched capacitor filter.
ANMUTE is an analogue muting signal gating the analogue signal at the output (after
the SC filter)
AUTOMUTE is asserted when both the IZD register bit is asserted and the input audio
data has been zero on both left and right channels for 1024 input samples. The first
non-zero sample de-asserts.
Applying a logic low to MUTEB or setting MUT in Reg2 causes the gain registers to
ramp to zero. When a logic high is applied, the gain ramps slowly back up to the value
held in the appropriate attenuation register (AL or AR). The ramp rate = 128/fs s/0.5dB
step.
If SOFTMUTE is set or
MUTEB=0 then GAINL and
GAINR are overridden to 00
MUTEB
GAINL[0:7]
GAINR[0:7]
ANMUTE
SOFTMUTE
gain ramps between
previous and new gain
setting
Signal
Processing
IZD
ZERO
OPE
FREQ_INVALID
INIT
Automute:
Detect 1024
zero input
samples
Figure 7 Mute Modes
WM8740
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
16
FILTER RESPONSES
Figure 8 Digital Filter Response (Sharp Roll-off Mode)
Figure 9 Digital Filter Response (Sharp Roll-off Mode)
Figure 10 Digital Filter Response (Slow Roll-off Mode)
Figure 11 Digital Filter Response (Slow Roll-off Mode)
-120
-100
-80
-60
-40
-20
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Response (dB)
Frequency (Fs)
Figure 12 Digital Filter Response 128fs Mode (192kHz
Sample Rate) Normal Mode Solid, Slow Mode Dashed
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WM8740
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-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0
10
20
30
40
50
60
Impulse Response
Time (input samples)
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0
10
20
30
40
50
60
Impulse Response
Time (input samples)
Figure 13 Impulse Response (Normal Roll-off,
no De-emphasis)
Figure 14 Impulse Response (Slow Roll-off,
no De-emphasis)
WM8740
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
18
RECOMMENDED EXTERNAL COMPONENTS
28
DVDD
DGND
ML/I2S
AGND
AVDDL
AVDD
11
VMIDR
C
11
C
10
C
9
AGND
8
7
Software I/F or
Hardware Control
WM8740
Notes: 1.
AGND and DGND should be connected as close to the WM8740 as possible.
2.
C
2
to C
5
, C
9
and C
11
should be positioned as close to the WM8740 as possible.
3.
Capacitor type used can have a big effect on device performance. It is
recommended that capacitors with very low ESR are used and that ceramics are
either NPO or COG type material to achieve best performance from the WM8740.
AVDDR
AGNDR
AGNDL
C
3
C
4
C
5
C
6
AGND
C
2
DVDD
C
1
27
MC/DM1
26
MD/DM0
23
CSB/IWO
22
RSTB
12
MODE8X
6
DIFFHW
21
ZERO
AVDD
AVDD
R
1
18
VMIDL
C
12
1
LRCIN
2
DIN
3
BCKIN
5
SCLK
Audio Serial Data I/F
System Clock Input
DGND
+
+
+
+
15
9
20
14
10
19
24
MODE
25
MUTEB
VOUTRN
VOUTRP
-
-
+
+
13
12
LEFT OUTPUT DATA
RIGHT OUTPUT DATA
VOUTLP
17
VOUTLN
16
Figure 15 External Components Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1 and C6
10
F
De-coupling for DVDD and AVDD.
C2 to C5
0.1
F
De-coupling for DVDD and AVDD.
C7 and C8
10
F
Output AC coupling caps to remove VMID DC level from outputs.
C9 and C11
0.1
F
C10 and C12
10
F
Reference de-coupling capacitors for VMIDR and VMIDL.
R1
10k
Resistor to AVDD for open drain output operation.
Table 22 External Components Description
Advanced Information
WM8740
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
19
SUGGESTED DIFFERENTIAL OUTPUT FILTER CIRCUIT
Figure 16 Suggested Differential Output Filter Circuit
WM8740
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
20
PACKAGE DIMENSIONS
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
DM007.B
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)
Symbols
Dimensions
(mm)
MIN
NOM
MAX
A
-----
-----
2.13
A
1
0.05
-----
0.25
A
2
1.62
1.75
1.88
b
0.22
-----
0.38
c
0.09
-----
0.20
D
9.90
10.20
10.50
e
0.65 BSC
E
7.40
7.80
8.20
E
1
5.00
5.30
5.60
L
0.63
0.90
1.03
0
o
4
o
8
o
REF:
JEDEC.95, MO-150
A A2
A1
SEATING PLANE
-C-
0.10 C
14
1
D
15
28
E1
E
e
b
c
L
GAUGE
PLANE
0.25
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