AD5371 40-Channel, 14-Bit Serial Input, Voltage-Output DAC Preliminary data Sheet (Rev. PrC)
40-Channel, 14-Bit
Serial Input, Voltage-Output DAC
Preliminary Technical Data
AD5371
Rev. Pr C
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2005 Analog Devices, Inc. All rights reserved.
FEATURES
40-channel DAC in 80 Lead LQFP and 100 Ball CSPBGA
Guaranteed monotonic to 14 bits
Maximum output voltage span of 4 V
REF
(20 V)
Nominal output voltage range of -4 V to +8 V
Multiple, Independent output spans available
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Thermal Monitor Function
DSP/microcontroller-compatible serial interface
LVDS serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
Power-on reset
Digital reset (RESET)
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
CONTROL
REGISTER
STATE
MACHINE
14
POWER-ON
RESET
SPI/LVDS
SYNC
SDI
SCLK
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
AD5371
SERIAL
INTERFACE
14
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
SIGGND1
14
14
14
DAC 0
REGISTER
14
14
8
8
14
14
14
14
TO
MUX 2's
MUX
1
A/B SELECT
REGISTER
X1A REGISTER
X1B REGISTER
M REGISTER
C REGISTER
14
MUX
2
X2A REGISTER
X2B REGISTER
OFS1
REGISTER
14
14
DAC 0
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OFFSET
DAC 1
BUFFER
14
14
14
DAC 7
REGISTER
14
14
14
14
14
14
MUX
1
X1A REGISTER
X1B REGISTER
M REGISTER
C REGISTER
14
MUX
2
X2A REGISTER
X2B REGISTER
DAC 7
GROUP 1
VREF0
SIGGND0
VREF2
SIGGND2
SIGGND4
SIGGND3
VREF2 SUPPLIES
GROUPS 2 TO 4
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT16
TO
VOUT39
GROUPS 2 TO 4
SAME AS GROUP 1
LDAC
DV
CC
V
DD
V
SS
AGND DNGD
14
14
14
DAC 0
REGISTER
14
14
8
8
14
14
14
14
TO
MUX 2's
MUX
1
A/B SELECT
REGISTER
X1A REGISTER
X1B REGISTER
M REGISTER
C REGISTER
14
MUX
2
X2A REGISTER
X2B REGISTER
OFS0
REGISTER
14
14
DAC 0
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OFFSET
DAC 0
BUFFER
GROUP 0
14
14
14
DAC 7
REGISTER
14
14
14
14
14
14
MUX
1
X1A REGISTER
X1B REGISTER
M REGISTER
C REGISTER
14
MUX
2
X2A REGISTER
X2B REGISTER
DAC 7
BUFFER
VREF1
5371-0001
Figure 1.
AD5371--Protected by U.S. Patent No. 5,969,657; other patents pending
Preliminary Technical Data
AD5371
Rev. Pr C | Page 2 of 24
TABLE OF CONTENTS
Specifications......................................................................................4
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings.............................................................9
ESD Caution.................................................................................. 9
Terminology .....................................................................................12
Functional Description ...................................................................13
DAC Architecture--General..................................................... 13
Channel Groups.......................................................................... 13
A/ B Registers And Gain/Offset Adjustment.......................... 14
Load DAC.................................................................................... 14
Offset DACs ................................................................................ 14
Output Amplifier........................................................................ 14
Transfer Function ....................................................................... 15
Reference Selection .................................................................... 15
Calibration................................................................................... 16
Reset Function ............................................................................ 16
Clear Function ............................................................................ 16
Power-Down Mode.................................................................... 17
Thermal Monitor Function....................................................... 17
Toggle Mode................................................................................ 17
Serial Interface .................................................................................18
SPI Interface ................................................................................ 18
LVDS Interface............................................................................ 18
SPI Write Mode .......................................................................... 18
SPI Readback Mode ................................................................... 19
LVDS Operation ......................................................................... 19
Register Update Rates ................................................................ 19
Channel Addressing And Special Modes................................ 19
Special Function Mode.............................................................. 20
Power Supply Decoupling ......................................................... 22
Power Supply Sequencing ......................................................... 22
Interfacing Examples ................................................................. 23
Outline Dimensions ........................................................................24
Ordering Guide .......................................................................... 24
REVISION HISTORY
Pr B1
Changed DIN to SDI
Pr. B2
Added Reset Function text
Pr. B3
Added Power Down Mode text
Pr. B4
Added Terminology and Power Supply Sequencing sections
Preliminary Technical Data
AD5371
Rev. Pr C | Page 3 of 24
General Description
The AD5371 contains 40, 14-bit DACs in a single, 80-lead,
LQFP package. It provides buffered voltage outputs with a span
4 times the reference voltage. The gain and offset of each DAC
can be independently trimmed to remove errors. For even
greater flexibility, the device is divided into blocks of 8 DACs,
and the output range of each block can be independently
adjusted by an offset DAC.
The AD5371 offers guaranteed operation over a wide supply
range with V
SS
from -4.5 V to -16.5 V and V
DD
from +8 V to
+16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.
The AD5371 has a high-speed serial interface, which is
compatible with SPI, QSPITM, MICROWIRETM, and DSP
interface standards and can handle clock speeds of up to 50
MHz. It also has a 100 MHz Low Voltage Differential Signaling
(LVDS) serial interface compliant with EIA-644 specification.
The DAC outputs are updated on reception of new data into the
DAC registers. All the outputs can be updated simultaneously
by taking the LDAC input low. Each channel has a program-
mable gain and an offset adjust register.
Each DAC output is amplified and buffered on-chip with
respect to an external SIGGND input. The DAC outputs can
also be switched to SIGGND via the CLR pin.
Table 1. High Channel Count Bipolar DACs
Model
Resolution
Nominal Output Span
Output
Channels
Linearity Error
(LSB)
Package Description
Package Option
AD5360BCPZ
16 Bits
4
V
REF
(20 V)
16
4
56-Lead LFCSP
CP-56
AD5360BSTZ
16 Bits
4
V
REF
(20 V)
16
4
52-Lead LQFP
ST-52
AD5361BCPZ
14 Bits
4
V
REF
(20 V)
16
1
56-Lead LFCSP
CP-56
AD5361BSTZ
14 Bits
4
V
REF
(20 V)
16
1
52-Lead LQFP
ST-52
AD5362BCPZ 16
Bits
4
V
REF
(20 V)
8
4
56-Lead LFCSP
CP-56
AD5362BSTZ 16
Bits
4
V
REF
(20 V)
8
4
52-Lead LQFP
ST-52
AD5363BCPZ
14 Bits
4
V
REF
(20 V)
8
1
56-Lead LFCSP
CP-56
AD5363BSTZ
14 Bits
4
V
REF
(20 V)
8
1
52-Lead LQFP
ST-52
AD5370BCPZ
16 Bits
4
V
REF
(12 V)
40
4
64-Lead LFCSP
CP-64
AD5370BSTZ
16 Bits
4
V
REF
(12 V)
40
4
64-Lead LQFP
ST-64
AD5371BCPZ
14 Bits
4
V
REF
(12 V)
40
1
100-Ball CSPBGA
BC-100-2
AD5371BSTZ
14 Bits
4
V
REF
(12 V)
40
1
80-Lead LQFP
ST-80
AD5372BCPZ
16 Bits
4
V
REF
(12 V)
32
4
56-Lead LFCSP
CP-56
AD5372BSTZ
16 Bits
4
V
REF
(12 V)
32
4
64-Lead LQFP
ST-64
AD5373BCPZ
14 Bits
4
V
REF
(12 V)
32
1
56-Lead LFCSP
CP-56
AD5373BSTZ
14 Bits
4
V
REF
(12 V)
32
1
64-Lead LQFP
ST-64
Preliminary Technical Data
AD5371
Rev. Pr C | Page 4 of 24
SPECIFICATIONS
DV
CC
= 2.3 V to 5.5 V; V
DD
= 8 V to 16.5 V; V
SS
= -4.5 V to -16.5 V; V
REF
= 3 V; AGND = DGND = SIGGND = 0 V; R
L
= Open Circuit;
Gain (m), Offset (c) and DAC Offset registers at default values; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.Performance Specifications
Parameter B
Version
1
Unit
Test
Conditions/Comments
2
ACCURACY
Resolution 14
Bits
Relative Accuracy
1
LSB max
Differential Nonlinearity
1
LSB max
Guaranteed monotonic by design over temperature.
Offset Error
6
2
mV min/max
mV typ
Before Calibration
Gain Error
10
3
mV max
mV typ
Before Calibration
Offset Error
2
100
V max
After Calibration
Gain Error
2
100
V max
After Calibration
VOUT Temperature Coefficient
5
ppm FSR/C typ
Includes linearity, offset, and gain drift.
DC Crosstalk
2
1.5
mV max
Typically 100 V.
REFERENCE INPUTS (VREF0, VREF1,
VREF2)
2
V
REF
Input Current
60
nA max
Per input. Typically 30 nA.
V
REF
Range
2/5
V min/max
2% for specified operation.
SIGGND INPUT (SIGGND0 TO SIGGND4)
2
DC Input Impedance
55
k min
Typically 60 k.
Input Range
0.5
V min/max
OUTPUT CHARACTERISTICS
2
Output Voltage Range
V
SS
+ 1.4
V min
I
LOAD
= 1 mA.
V
DD
- 1.4
V max
I
LOAD
= 1 mA.
Nominal Output Voltage Range
-4 to +8
V
Short Circuit Current
10
mA max
Load Current
1
mA max
Capacitive Load Stability
2
nF max
DC Output Impedance
0.5
max
DIGITAL INPUTS
JEDEC compliant.
Input High Voltage
1.7
V min
DV
CC
= 2.3 V to 3.6 V.
2.0
V
min
DV
CC
= 3.6 V to 5.5 V.
Input Low Voltage
0.8
V max
DV
CC
= 2.5 V to 5.5 V.
0.7
V
DV
CC
= 2.3 V to 2.7 V.
Input Current
1
A max
Except CLR and RESET
Input Capacitance
2
10
pF
max
DIGITAL OUTPUTS (SDO, BUSY)
Output Low Voltage
0.5
V max
Sinking 200 A.
Output High Voltage (SDO)
DV
CC
- 0.5
V min
Sourcing 200 A.
High Impedance Leakage Current
5
A max
SDO only.
High Impedance Output Capacitance
10
pF typ
Preliminary Technical Data
AD5371
Rev. Pr C | Page 5 of 24
Parameter B
Version
1
Unit
Test
Conditions/Comments
2
LVDS INTERFACE Reduced Range Link
Digital Inputs
2
Input Voltage Range
875/1575
mV min/max
Input Differential Threshold
---0.1/0.1 V
min/max
External Termination Resistance
80/120
min/max
100
typ
132
max
Differential Input Voltage
100
mV min
POWER REQUIREMENTS
DV
CC
2.3/5.5
V
min/max
V
DD
8/16.5
V
min/max
V
SS
-4.5/-16.5
V
min/max
Power Supply Sensitivity
2
Full Scale/ V
DD
-75
dB
typ
Full Scale/ V
SS
-75
dB
typ
Full Scale/ V
CC
-90
dB
typ
DI
CC
2
mA
max
V
CC
= 5.5 V, V
IH
= V
CC
, V
IL
= GND.
I
DD
14
mA max
Outputs unloaded.
I
SS
14
mA max
Outputs unloaded.
Power Dissipation
Power Dissipation Unloaded (P)
250
mW
V
SS
= -5.5 V, V
DD
= +9.5 V, DV
CC
= 2.5 V
Junction Temperature
3
130 C
max
T
J
= T
A
+ P
TOTAL
J
.
1
Temperature range for B Version: -40C to +85C. Typical specifications are at 25C.
2
Guaranteed by design and characterization, not production tested.
3
Where
J
represents the package thermal impedance.
AC CHARACTERISTICS
DV
CC
= 2.5; V
DD
= 15 V; V
SS
= -15 V; V
REF
= 3 V; AGND = DGND = SIGGND = 0 V; C
L
= 200 pF to GND; R
L
= 10 k to GND;
Gain (m), Offset (c) and DAC Offset registers at default values; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3. AC Characteristics
Parameter b
Version
1
Unit
Test
Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
TBD
s typ
Full-scale change
30
s max
Slew Rate
1
V/s typ
Digital-to-Analog Glitch Energy
20
nV-s typ
Glitch Impulse Peak Amplitude
10
mV max
Channel-to-Channel Isolation
100
dB typ
V
REF
(+) = 2 V p-p, 1 kHz.
DAC-to-DAC Crosstalk
40
nV-s typ
Between DACs inside a group.
10
nV-s typ
Between DACs from different groups.
Digital Crosstalk
0.1
nV-s typ
Digital Feedthrough
1
nV-s typ
Effect of input bus activity on DAC output under test.
Output Noise Spectral Density @ 10 kHz
250
nV/(Hz)
1/2
typ
V
REF
= 0 V.
1
Guaranteed by design and characterization, not production tested.
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