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16-Bit, 100 kSPS PulSAR
Differential ADC in MSOP
AD7684
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
16-bit resolution with no missing codes
Throughput: 100 kSPS
INL: 1 LSB typ, 3 LSB max
True differential analog input range: V
REF
0 V to V
REF
with V
REF
up to VDD on both inputs
Single-supply operation: 2.7 V to 5.5 V
Serial interface SPI-
/QSPI-TM/MICROWIRE-TM/DSP-compatible
Power Dissipation : 4 mW @ 5 V, 1.5 mW @ 2.7 V,
150 W @ 2.7 V/10 kSPS
Standby current: 1 nA
8-lead MSOP package
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control
APPLICATION DIAGRAM
AD7684
REF
GND
VDD
+IN
IN
DCLOCK
D
OUT
CS
3-WIRE SPI
INTERFACE
0.5V TO VDD 2.7V TO 5.5V
04302-001
0
V
REF
0
V
REF
Figure 1.
Table 1. MSOP, QFN (LFCSP)/SOT-23, 16-Bit PulSAR ADCs
Type
100 kSPS
250 kSPS
500 kSPS
True Differential
AD7684
AD7687
AD7688
Pseudo
Differential/Unipolar
AD7683
AD7685
AD7694
AD7686
Unipolar
AD7680
GENERAL DESCRIPTION
The AD7684 is a 16-bit, charge redistribution, successive
approximation, PulSAR
TM
analog-to-digital converter (ADC)
that operates from a single power supply, VDD, between 2.7 V
to 5.5 V. It contains a low power, high speed, 16-bit sampling
ADC with no missing codes, an internal conversion clock, and a
serial, SPI-compatible interface port. The part also contains a
low noise, wide bandwidth, short aperture delay, track-and-hold
circuit. On the CS falling edge, it samples the voltage difference
between +IN and IN pins. The reference voltage, REF, is
applied externally and can be set up to the supply voltage. Its
power scales linearly with throughput.
The AD7684 is housed in an 8-lead MSOP package, with an
operating temperature specified from -40C to +85C.
AD7684
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Application Information................................................................ 12
Circuit Information.................................................................... 12
Converter Operation.................................................................. 12
Transfer Functions...................................................................... 12
Typical Connection Diagram ................................................... 13
Analog Input ............................................................................... 13
Driver Amplifier Choice............................................................ 13
Voltage Reference Input ............................................................ 14
Power Supply............................................................................... 14
Digital Interface .......................................................................... 14
Layout .......................................................................................... 14
Evaluating the AD7684's Performance .................................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
10/04--Initial Version: Revision 0
AD7684
Rev. 0 | Page 3 of 16
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; V
REF
= VDD; T
A
= 40C to +85C, unless otherwise noted.
Table 2.
Parameter Conditions Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUT
Voltage Range
+IN - (IN)
-V
REF
+V
REF
V
Absolute Input Voltage
+IN, IN
-0.1
VDD + 0.1
V
Analog Input CMRR
f
IN
= 100 kHz
65
dB
Leakage Current at 25C
Acquisition phase
1
nA
Input Impedance
See the Analog Input section.
THROUGHPUT SPEED
Complete Cycle
10
S
Throughput Rate
0
100
kSPS
DCLOCK Frequency
0
2.9
MHz
REFERENCE
Voltage Range
0.5
VDD + 0.3
V
Load Current
100 kSPS, V
+IN
= V
-IN
= V
REF
/2 = 2.5 V
50
A
DIGITAL INPUTS
Logic Levels
V
IL
-0.3
0.3 VDD
V
V
IH
0.7 VDD
VDD + 0.3
V
I
IL
-1
+1
A
I
IH
-1
+1
A
Input Capacitance
5
pF
DIGITAL OUTPUTS
Data Format
Serial 16 Bits Twos Complement.
V
OH
I
SOURCE
= -500 A
VDD - 0.3
V
V
OL
I
SINK
= +500 A
0.4
V
POWER SUPPLIES
VDD Specified
performance
2.7
5.5
V
VDD Range
1
2.0
5.5
V
Operating Current
100 kSPS throughput
VDD = 5 V
800
A
VDD = 2.7 V
560
A
Standby Current
2, 3
VDD = 5 V, 25
C
1
50
nA
Power Dissipation
VDD = 5 V
4
6
mW
VDD = 2.7 V
1.5
mW
VDD = 2.7 V, 10 kSPS throughput
2
150
W
TEMPERATURE RANGE
Specified Performance
T
MIN
to T
MAX
-40
+85
C
1
See the
section for more information.
Typical Performance Characteristics
2
With all digital inputs forced to VDD or GND, as required.
3
During acquisition phase.
AD7684
Rev. 0 | Page 4 of 16
VDD = 5 V; V
REF
= VDD; T
A
= 40C to +85C, unless otherwise noted.
Table 3.
Parameter Conditions
Min
Typ
Max
Unit
ACCURACY
No Missing Codes
16
Bits
Integral Linearity Error
-3
1
+3
LSB
Transition Noise
0.5
LSB
Gain Error
1
, T
MIN
to T
MAX
2
15
LSB
Gain Error Temperature Drift
0.3
ppm/C
Zero Error
1
, T
MIN
to T
MAX
0.4
1.6
mV
Zero Temperature Drift
0.3
ppm/C
Power Supply Sensitivity
VDD = 5 V
5%
0.05
LSB
AC ACCURACY
Signal-to-Noise f
IN
= 1 kHz
88
91
dB
2
Spurious-Free Dynamic Range
f
IN
= 1 kHz
-108
dB
Total Harmonic Distortion
f
IN
= 1 kHz
-106
dB
Signal-to-(Noise + Distortion)
f
IN
= 1 kHz
88
91
dB
Effective Number of Bits
f
IN
= 1 kHz
14.8
Bits
1
See the
section. These specifications include full temperature range variation, but do not include the error contribution from the external reference.
Terminology
2
All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
VDD = 2.7 V; V
REF
= 2.5 V; T
A
= 40C to +85C, unless otherwise noted.
Table 4.
Parameter Conditions
Min
Typ
Max
Unit
ACCURACY
No Missing Codes
16
Bits
Integral Linearity Error
-3
1
+3
LSB
Transition Noise
0.85
LSB
Gain Error
1
, T
MIN
to T
MAX
2
15
LSB
Gain Error Temperature Drift
0.3
ppm/C
Zero Error
1
, T
MIN
to T
MAX
0.7
3.5
mV
Zero Temperature Drift
0.3
ppm/C
Power Supply Sensitivity
VDD = 2.7 V
5%
0.05
LSB
AC ACCURACY
Signal-to-Noise f
IN
= 1 kHz
86
dB
2
Spurious-Free Dynamic Range
f
IN
= 1 kHz
-100
dB
Total Harmonic Distortion
f
IN
= 1 kHz
-98
dB
Signal-to-(Noise + Distortion)
f
IN
= 1 kHz
86
dB
Effective Number of Bits
f
IN
= 1 kHz
14
Bits
1
See the
section. These specifications do include full temperature range variation, but do not include the error contribution from the external reference.
Terminology
2
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
AD7684
Rev. 0 | Page 5 of 16
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; T
A
= -40C to +85C, unless otherwise noted.
Table 5.
Parameter Symbol
Min
Typ
Max
Unit
Throughput Rate
t
CYC
100
kHz
CS Falling to DCLOCK Low
t
CSD
0
s
CS Falling to DCLOCK Rising
t
SUCS
20
ns
DCLOCK Falling to Data Remains Valid
t
HDO
5 16
ns
CS Rising Edge to D
OUT
High Impedance
t
DIS
14
100
ns
DCLOCK Falling to Data Valid
t
EN
16
50
ns
Acquisition Time
t
ACQ
400
ns
D
OUT
Fall Time
t
F
11
25
ns
D
OUT
Rise Time
t
R
11
25
ns
04302-002
D
OUT
DCLOCK
COMPLETE CYCLE
POWER DOWN
CS
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(MSB)
(LSB)
Hi-Z
0
Hi-Z
t
ACQ
t
DIS
0
1
4
5
t
HDO
t
EN
t
CSD
t
SUCS
t
CYC
NOTE:
A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.
D
OUT
GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
Figure 2. Serial Interface Timing
AD7684
Rev. 0 | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Analog Inputs
+IN
1
, IN
1
GND - 0.3 V to VDD + 0.3 V
or 130 mA
REF
GND - 0.3 V to VDD + 0.3 V
Supply Voltages
VDD to GND
-0.3 V to +6 V
Digital Inputs to GND
-0.3 V to VDD + 0.3 V
Digital Outputs to GND
-0.3 V to VDD + 0.3 V
Storage Temperature Range
-65C to +150C
Junction Temperature
150C
JA
Thermal Impedance
200C/W
JC
Thermal Impedance
44C/W
Lead Temperature Range
Vapor Phase (60 sec)
215C
Infrared (15 sec)
220C
1
See the
section.
Analog Input
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
04302-003
500
A
I
OL
500
A
I
OH
1.4V
TO D
OUT
C
L
100pF
Figure 3. Load Circuit for Digital Interface Timing
0.8V
2V
2V
0.8V
0.8V
2V
t
DELAY
t
DELAY
04302-004
Figure 4. Voltage Reference Levels for Timing
04302-005
D
OUT
90%
10%
t
R
t
F
Figure 5. D
OUT
Rise and Fall Timing
AD7684
Rev. 0 | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04302-006
REF
1
+IN
2
IN
3
GND
4
VDD
8
DCLOCK
7
D
OUT
6
CS
5
AD7684
TOP VIEW
(Not to Scale)
Figure 6. 8-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type
1
Function
1 REF AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a ceramic capacitor of a few F.
2
+IN
AI
Differential Positive Analog Input.
3
IN
AI
Differential Negative Analog Input.
4
GND
P
Power Supply Ground.
5
CS
DI
Chip Select Input. On its falling edge, it initiates the conversions. The part returns in shutdown mode as
soon as the conversion is done. It also enables D
OUT
. When high, D
OUT
is high impedance.
6 D
OUT
DO
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
7
DCLOCK
DI
Serial Data Clock Input.
8 VDD P
Power
Supply.
1
AI = Analog Input; DI = Digital Input; DO = Digital Output; and P = Power.
AD7684
Rev. 0 | Page 8 of 16
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs LSB before
the first code transition. Positive full scale is defined as a level
1 LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line
(see Figure 21).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Zero error is the difference between the ideal midscale voltage,
i.e., 0 V, and the actual voltage producing the midscale output
code, i.e., 0 LSB.
Gain Error
The first transition (from 100 . . . 00 to 100 . . . 01) should occur
at a level LSB above the nominal negative full scale
(-4.999924 V for the 5 V range). The last transition (from
011...10 to 011...11) should occur for an analog voltage
1 LSB below the nominal full scale (4.999771 V for the 5 V
range.) The gain error is the deviation of the difference between
the actual level of the last transition and the actual level of the
first transition from the difference between the idea levels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula
[
]
(
)
02
.
6
/
76
.
1
/
-
+
=
dB
D
N
S
ENOB
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in dB.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is the time between the falling edge of the CS input and when
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to
accurately acquire its input after a full-scale step function
was applied.
AD7684
Rev. 0 | Page 9 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
3
2
1
0
1
2
3
0
16384
32768
49152
65536
CODE
INL (
L
SB)
04302-017
POSITIVE INL = +0.83LSB
NEGATIVE INL = 1.07LSB
Figure 7. Integral Nonlinearity vs. Code
04302-008
151
94794
18557
17388
182
0
20000
40000
60000
80000
100000
120000
FFFD FFFE FFFF 0000 0001 0002 0003 0004 0005
CODE IN HEX
COUNTS
VDD = REF = 2.5V
0
0
0
0
Figure 8. Histogram of a DC Input at the Code Center
180
160
140
120
100
80
60
40
20
0
04302-009
0
10
20
30
40
FREQUENCY (kHz)
AMP
L
ITUDE
(dB of Full S
c
a
l
e
)
50
16384 POINT FFT
VDD = REF = 5V
f
S
= 100kSPS
f
IN
= 20.43kHz
Figure 9. FFT Plot
3
2
1
0
1
2
3
0
16384
32768
49152
65536
CODE
DNL (LS
B
)
04302-010
POSITIVE DNL = +0.9LSB
NEGATIVE DNL = 0.45LSB
Figure 10. Differential Nonlinearity vs. Code
04302-011
123872
4150
3050
0
50000
100000
150000
FFFB
FFFC
FFFD
FFFE
FFFF
CODE IN HEX
COUNTS
0
0
VDD = REF = 5V
Figure 11. Histogram of a DC Input at the Code Center
180
160
140
120
100
80
60
40
20
0
04302-012
0
10
20
30
40
FREQUENCY (kHz)
AMP
L
ITUDE
(dB of Full S
c
a
l
e
)
50
16384 POINT FFT
VDD = REF = 2.5V
f
S
= 100kSPS
f
IN
= 20.43kHz
Figure 12. FFT Plot
AD7684
Rev. 0 | Page 10 of 16
ENOB (Bit
s)
13
14
15
16
17
80
85
90
95
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
REFERENCE VOLTAGE (V)
S
NR,
S
/
[N+D] (dB)
04302-013
S/[N+D]
SNR
ENOB
Figure 13. SNR, S/(N + D), and ENOB vs. Reference Voltage
70
75
80
85
90
95
100
0
50
100
150
200
FREQUENCY (kHz)
S
/
[N+D](dB)
VREF = 5V, 1dB
VREF = 2.5V, 1dB
VREF = 5V, 10dB
04302-014
Figure 14. S/[N + D] vs. Frequency
115
110
105
100
95
90
85
80
0
40
80
120
160
200
FREQUENCY (kHz)
THD (dB)
VREF = 2.5V, 1dB
VREF = 5V, 1dB
04302-015
Figure 15. THD, ENOB vs. Frequency
0
200
400
600
800
1000
1200
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY (V)
OP
E
RATING CURRE
NT (
A)
04302-016
f
S
= 100kSPS
Figure 16. Operating Current vs. Supply
0
200
400
600
800
1000
TEMPERATURE (
C)
OP
E
RATI
N
G CURRE
NT (
A)
04302-017
55
35
15
5
25
45
65
85
105
125
VDD = 5V
VDD = 2.7V
Figure 17. Operating Current vs. Temperature
0
250
500
750
1000
TEMPERATURE (
C)
P
O
WE
R-DOWN CURRE
NT (
A)
04302-018
55
35
15
5
25
45
65
85
105
125
Figure 18. Power-Down Current vs. Temperature
AD7684
Rev. 0 | Page 11 of 16
6
4
2
3
5
0
1
2
1
4
3
6
5
55
35
15
5
25
45
65
85
105
125
TEMPERATURE (
C)
ZE
RO E
RROR,
FULL-S
CALE
E
RROR (LS
B
)
04302-019
ZERO ERROR
GAIN ERROR
Figure 19. Offset and Gain Error vs. Temperature
AD7684
Rev. 0 | Page 12 of 16
APPLICATION INFORMATION
SW+
MSB
16,384C
+IN
LSB
COMP
CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
IN
4C
2C
C
C
32,768C
SW
MSB
16,384C
LSB
4C
2C
C
C
32,768C
04302-020
Figure 20. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7684 is a low power, single-supply, 16-bit ADC using a
successive approximation architecture. It is capable of convert-
ing 100,000 samples per second (100 kSPS) and powers down
between conversions. When operating at 10 kSPS, for example,
it consumes typically 150 W with a 2.7 V supply, ideal for
battery-powered applications.
The AD7684 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7684 is specified from 2.7 V to 5.5 V. It is housed in a
8-lead MSOP package.
CONVERTER OPERATION
The AD7684 is a successive approximation ADC based on a
charge redistribution DAC. Figure 20 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator's input are connected to GND via SW+ and SW-.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the +IN and -IN inputs. When the
acquisition phase is complete and the CS input goes low, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW- are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs, +IN and -IN, captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each element
of the capacitor array between GND and REF, the comparator
input varies by binary-weighted voltage steps (V
REF
/2,
V
REF
/4...V
REF
/65536). The control logic toggles these switches,
starting with the MSB, in order to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase and the control logic
generates the ADC output code.
TRANSFER FUNCTIONS
The ideal transfer function for the AD7684 is shown in
Figure 21 and Table 8.
100...000
100...001
100...010
011...101
011...110
011...111
ADC CODE
(TWOS
COMP
LE
ME
NT)
ANALOG INPUT
+FS 1.5 LSB
+
FS 1 LSB
FS + 1 LSB
FS
FS + 0.5 LSB
04302-021
Figure 21. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Description
Analog Input
V
REF
= 5 V
Digital Output Code Hexa
FSR 1 LSB
4.999847 V
7FFF
1
Midscale + 1 LSB
152.6 V
0001
Midscale
0 V
0000
Midscale 1 LSB
152.6 V
FFFF
FSR + 1 LSB
4.999847 V
8001
FSR
5 V
8000
2
1
This is also the code for an overranged analog input (V
+IN
V
IN
above
V
REF
V
GND
).
2
This is also the code for an underranged analog input (V
+IN
V
IN
below -V
REF
+ V
GND
).
AD7684
Rev. 0 | Page 13 of 16
04302-022
AD7684
REF
GND
VDD
IN
+IN
DCLOCK
D
OUT
CS
3-WIRE INTERFACE
100nF
2.7V TO 5.25V
2.2
F TO 10
F
(NOTE 2)
REF
0 TO V
REF
33
2.7nF
(NOTE 3)
(NOTE 4)
(NOTE 1)
V
REF
TO 0
33
2.7nF
(NOTE 3)
(NOTE 4)
NOTE 1: SEE REFERENCE SECTION FOR REFERENCE SELECTION.
NOTE 2: C
REF
IS USUALLY A 10
F CERAMIC CAPACITOR (X5R).
NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION.
NOTE 4: OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
NOTE 5: SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.
Figure 22. Typical Application Diagram
TYPICAL CONNECTION DIAGRAM
Figure 22 shows an example of the recommended application
diagram for the AD7684.
ANALOG INPUT
Figure 23 shows an equivalent circuit of the input structure of
the AD7684. The two diodes, D1 and D2, provide ESD protec-
tion for the analog inputs, +IN and -IN. Care must be taken to
ensure that the analog input signal never exceeds the supply
rails by more than 0.3 V, because this will cause these diodes to
become forward-biased and start conducting current. However,
these diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions could eventually
occur when the input buffer's (U1) supplies are different from
VDD. In such a case, an input buffer with a short-circuit current
limitation can be used to protect the part.
04302-023
C
IN
R
IN
D1
D2
C
PIN
+IN
OR IN
GND
VDD
Figure 23. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the differ-
ential signal between +IN and -IN. By using this differential
input, small signals common to both inputs are rejected. For
instance, by using -IN to sense a remote signal ground, ground
potential differences between the sensor and the local ADC
ground are eliminated. During the acquisition phase, the impe-
dance of the analog input +IN can be modeled as a parallel
combination of the capacitor C
PIN
and the network formed by
the series connection of R
IN
and C
IN
. C
PIN
is primarily the pin
capacitance. R
IN
is typically 600 and is a lumped component
made up of some serial resistors and the on-resistance of the
switches. C
IN
is typically 30 pF and is mainly the ADC sampling
capacitor. During the conversion phase, when the switches are
opened, the input impedance is limited to C
PIN
. R
IN
and C
IN
make a 1-pole, low-pass filter that reduces undesirable aliasing
effects and limits the noise.
When the source impedance of the driving circuit is low, the
AD7684 can be driven directly. Large source impedances signi-
ficantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance.
DRIVER AMPLIFIER CHOICE
Although the AD7684 is easy to drive, the driver amplifier
needs to meet the following requirements:
The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7684. Note that the
AD7684 has a noise much lower than most other 16-bit
ADCs and, therefore, can be driven by a noisier op amp
while preserving the same or better system performance.
The noise coming from the driver is filtered by the AD7684
analog input circuit 1-pole, low-pass filter made by R
IN
and
C
IN
or by the external filter, if one is used.
For ac applications, the driver needs to have a THD
performance suitable to that of the AD7684. Figure 15
shows the THD vs. frequency that the driver should
exceed.
For multichannel multiplexed applications, the driver
amplifier and the AD7684 analog input circuit must be able
to settle for a full-scale step of the capacitor array at a
16-bit level (0.0015%). In the amplifier's data sheet, settling
at 0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
AD7684
Rev. 0 | Page 14 of 16
Table 9. Recommended Driver Amplifiers
Amplifier
Typical Application
AD8021
Very low noise and high frequency
AD8022
Low noise and high frequency
OP184
Low power, low noise, and low frequency
AD8605
,
AD8615
5 V single-supply, low power
AD8519
Small, low power, and low frequency
AD8031
High frequency and low power
VOLTAGE REFERENCE INPUT
The AD7684 voltage reference input, REF, has a dynamic input
impedance. It should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source (e.g., an
unbuffered reference voltage like the low temperature drift
ADR43x
reference or a reference buffer using the
AD8031
or
the
AD8605
), a 10 F (X5R, 0805 size) ceramic chip capacitor is
appropriate for optimum performance.
If desired, smaller reference decoupling capacitor values down
to 2.2 F can be used with a minimal impact on performance,
especially DNL.
POWER SUPPLY
The AD7684 powers down automatically at the end of each
conversion phase and therefore the power scales linearly with
the sampling rate, as shown in Figure 24. This makes the part
ideal for low sampling rates (even of a few Hz) and low battery-
powered applications.
0.01
0.1
1
10
100
1000
100
10
1k
10k
100k
SAMPLING RATE (SPS)
OP
E
RATING CURRE
NT (
A)
04302-024
VDD = 5V
VDD = 2.7V
Figure 24. Operating Current vs. Sampling Rate
DIGITAL INTERFACE
The AD7684 is compatible with SPI, QSPI, digital hosts, and
DSPs (e.g., Blackfin ADSP-BF53x or ADSP-219x). The con-
nection diagram is shown in Figure 25 and the corresponding
timing is given in Figure 2.
A falling edge on CS initiates a conversion and the data transfer.
After the fifth DCLOCK falling edge, D
OUT
is enabled and
forced low. The data bits are then clocked MSB first by subse-
quent DCLOCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate, provided it has an acceptable hold time.
04302-025
CS
DCLOCK
D
OUT
DATA IN
CLK
CONVERT
DIGITAL HOST
AD7684
Figure 25. Connection Diagram
LAYOUT
The printed circuit board housing the AD7684 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7684 with all its analog signals on the left side and all its
digital signals on the right side eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7684 is used as a shield. Fast switching signals, such as CS or
clocks, should never run near analog signal paths. Crossover of
digital and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog section. In such a case, it
should be joined underneath the AD7684.
The AD7684 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and by connecting these pins with wide, low
impedance traces.
Finally, the power supply, VDD, of the AD7684 should be
decoupled with a ceramic capacitor, typically 100 nF, and placed
close to the AD7684. It should be connected using short and
large traces to provide low impedance paths and reduce the
effect of glitches on the power supply lines.
EVALUATING THE AD7684'S PERFORMANCE
Other recommended layouts for the AD7684 are outlined in the
evaluation board for the AD7684 (
EVAL-AD7684
). The evalua-
tion board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the
EVAL-CONTROL BRD2
.
AD7684
Rev. 0 | Page 15 of 16
OUTLINE DIMENSIONS
0.80
0.60
0.40
8
0
4
8
5
4.90
BSC
PIN 1
0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COPLANARITY
0.10
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 26. 8-Lead Micro Small Outline Package [MSOP]
(RM-8)
Dimensions Shown in Millimeters
ORDERING GUIDE
Models
Integral
Nonlinearity
Temperature Range
Package (Option)
Transport Media,
Quantity Branding
AD7684BRM
3 LSB max
40C to +85C
MSOP (RM-8)
Tube, 50
C1D
AD7684BRMRL7
3 LSB max
40C to +85C
MSOP (RM-8)
Reel, 1,000
C1D
EVAL-AD7684CB
1
Evaluation Board
EVAL-CONTROL BRD2
2
Controller Board
EVAL-CONTROL BRD3
2
Controller Board
1
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes.
2
These boards allow a PC to control and communicate with all Analog Devices' evaluation boards ending in the CB designators.
AD7684
Rev. 0 | Page 16 of 16
NOTES
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered
trademarks are the property of their respective owners.
D04302-0-10/04(0)
Document Outline
- FEATURES
- APPLICATIONS
- APPLICATION DIAGRAM
- GENERAL DESCRIPTION
- SPECIFICATIONS
- TIMING SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TERMINOLOGY
- TYPICAL PERFORMANCE CHARACTERISTICS
- APPLICATION INFORMATION
- OUTLINE DIMENSIONS
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